TWI340900B - System and method for virtualization of processor resources - Google Patents

System and method for virtualization of processor resources

Info

Publication number
TWI340900B
TWI340900B TW094131197A TW94131197A TWI340900B TW I340900 B TWI340900 B TW I340900B TW 094131197 A TW094131197 A TW 094131197A TW 94131197 A TW94131197 A TW 94131197A TW I340900 B TWI340900 B TW I340900B
Authority
TW
Taiwan
Prior art keywords
virtualization
processor resources
resources
processor
Prior art date
Application number
TW094131197A
Other languages
English (en)
Chinese (zh)
Other versions
TW200630797A (en
Inventor
Maximino Aguilarjr
Michael Norman Day
Mark Richard Nutter
James Xenidis
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200630797A publication Critical patent/TW200630797A/zh
Application granted granted Critical
Publication of TWI340900B publication Critical patent/TWI340900B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
TW094131197A 2004-09-30 2005-09-09 System and method for virtualization of processor resources TWI340900B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/955,093 US7290112B2 (en) 2004-09-30 2004-09-30 System and method for virtualization of processor resources

Publications (2)

Publication Number Publication Date
TW200630797A TW200630797A (en) 2006-09-01
TWI340900B true TWI340900B (en) 2011-04-21

Family

ID=35385802

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094131197A TWI340900B (en) 2004-09-30 2005-09-09 System and method for virtualization of processor resources

Country Status (10)

Country Link
US (1) US7290112B2 (enExample)
EP (1) EP1805629B1 (enExample)
JP (1) JP4639233B2 (enExample)
KR (1) KR100968188B1 (enExample)
CN (1) CN100421089C (enExample)
BR (1) BRPI0515920B1 (enExample)
CA (1) CA2577865C (enExample)
MX (1) MX2007003679A (enExample)
TW (1) TWI340900B (enExample)
WO (1) WO2006034931A1 (enExample)

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US9569279B2 (en) 2012-07-31 2017-02-14 Nvidia Corporation Heterogeneous multiprocessor design for power-efficient and area-efficient computing

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US9032101B1 (en) 2008-12-10 2015-05-12 Nvidia Corporation Chipset support for binding and migrating hardware devices among heterogeneous processing units
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9569279B2 (en) 2012-07-31 2017-02-14 Nvidia Corporation Heterogeneous multiprocessor design for power-efficient and area-efficient computing

Also Published As

Publication number Publication date
CN1989492A (zh) 2007-06-27
JP2008515069A (ja) 2008-05-08
CN100421089C (zh) 2008-09-24
US20060069878A1 (en) 2006-03-30
EP1805629B1 (en) 2012-09-26
KR100968188B1 (ko) 2010-07-06
EP1805629A1 (en) 2007-07-11
TW200630797A (en) 2006-09-01
MX2007003679A (es) 2007-04-19
CA2577865C (en) 2011-09-27
US7290112B2 (en) 2007-10-30
WO2006034931A1 (en) 2006-04-06
BRPI0515920B1 (pt) 2018-03-20
BRPI0515920A2 (pt) 2009-08-04
KR20070052272A (ko) 2007-05-21
CA2577865A1 (en) 2006-04-06
JP4639233B2 (ja) 2011-02-23

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