TWI340547B - Signal receiver circuit - Google Patents

Signal receiver circuit

Info

Publication number
TWI340547B
TWI340547B TW096129215A TW96129215A TWI340547B TW I340547 B TWI340547 B TW I340547B TW 096129215 A TW096129215 A TW 096129215A TW 96129215 A TW96129215 A TW 96129215A TW I340547 B TWI340547 B TW I340547B
Authority
TW
Taiwan
Prior art keywords
signal receiver
receiver circuit
circuit
signal
receiver
Prior art date
Application number
TW096129215A
Other languages
English (en)
Other versions
TW200908554A (en
Inventor
Jung Chin Lai
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to TW096129215A priority Critical patent/TWI340547B/zh
Priority to US11/955,400 priority patent/US8019393B2/en
Priority to DE102008010124A priority patent/DE102008010124B4/de
Priority to JP2008059107A priority patent/JP4717092B2/ja
Publication of TW200908554A publication Critical patent/TW200908554A/zh
Application granted granted Critical
Publication of TWI340547B publication Critical patent/TWI340547B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
TW096129215A 2007-08-08 2007-08-08 Signal receiver circuit TWI340547B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW096129215A TWI340547B (en) 2007-08-08 2007-08-08 Signal receiver circuit
US11/955,400 US8019393B2 (en) 2007-08-08 2007-12-13 Signal receiver circuit
DE102008010124A DE102008010124B4 (de) 2007-08-08 2008-02-20 Signalempfängerschaltung
JP2008059107A JP4717092B2 (ja) 2007-08-08 2008-03-10 信号受信器回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096129215A TWI340547B (en) 2007-08-08 2007-08-08 Signal receiver circuit

Publications (2)

Publication Number Publication Date
TW200908554A TW200908554A (en) 2009-02-16
TWI340547B true TWI340547B (en) 2011-04-11

Family

ID=40227091

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096129215A TWI340547B (en) 2007-08-08 2007-08-08 Signal receiver circuit

Country Status (4)

Country Link
US (1) US8019393B2 (zh)
JP (1) JP4717092B2 (zh)
DE (1) DE102008010124B4 (zh)
TW (1) TWI340547B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3116127B1 (en) 2015-07-08 2018-09-12 Power Integrations Switzerland GmbH Receiver circuit
US10581420B2 (en) * 2018-07-20 2020-03-03 Nanya Technology Corporation Semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08101260A (ja) 1994-09-30 1996-04-16 Mitsubishi Electric Corp 半導体装置
DE69619972D1 (de) * 1996-06-18 2002-04-25 St Microelectronics Srl Nichtflüchtige Speicheranordnung mit niedriger Versorgungsspannung und Spannungserhöher
JP3201276B2 (ja) * 1996-09-10 2001-08-20 日本電気株式会社 信号伝送回路
US6020769A (en) 1997-10-17 2000-02-01 Lucent Technologies, Inc. Low voltage sample and hold circuits
JP2007019966A (ja) * 2005-07-08 2007-01-25 Renesas Technology Corp 半導体集積回路装置
KR100725362B1 (ko) 2005-07-11 2007-06-07 삼성전자주식회사 동적 메모리 장치 및 이를 포함하는 통신 단말기
JP2007060582A (ja) * 2005-08-26 2007-03-08 Sharp Corp 論理回路、半導体集積回路および携帯端末装置
JP2008077705A (ja) * 2006-09-19 2008-04-03 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JP2009044711A (ja) 2009-02-26
DE102008010124A1 (de) 2009-02-12
US20090042531A1 (en) 2009-02-12
DE102008010124B4 (de) 2011-06-01
TW200908554A (en) 2009-02-16
US8019393B2 (en) 2011-09-13
JP4717092B2 (ja) 2011-07-06

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