1330059 .九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電路板結構及其製法，更詳而言 •之，係關於-種於電路板之電鍵導通孔中形成電鍍金屬柱: 增加該電鍍導通孔之電性傳導效率之電路板結構及其製法。 【先前技術】 μ ' 隨著半導體的高度發展，以及高效能晶片之運算需 要，電路板亦需提昇訊號傳導、改善頻寬控制阻抗等功 籲能。然而’為符合半導體封裝件輕薄短小、多功能、高速 度及高頻化的開發方向，電路板已朝向細線路及小孔徑發 展。現有電路板製程從傳統100微米之線路尺寸包括導線 覓度（Line width)及線路間距（Space)等，已縮減至2〇 微米’並持續朝向更小的線路精度發展。 為提高半導體晶片封裝用之電路板之佈線精密度，業 界遂發展出一種增層技術（Bui ld_up)，亦即在一核心電路 板（Core circuit board)表面利用線路增層技術交互堆疊 多層介電層及線路層，並形成電鍍導通孔（pTH)貫穿該核 心板以供該核心板上下表面之線路之間電性連接，而該電 鍍導通孔之製程係影響電路板線路密度的關鍵，該核心電 路板之製法如第1A至1F圖所示。 請參閱第1A圖，提供一係為銅箔基板（c〇pper c〇ated Laminate，CCL)之基板1〇，該基板1〇具有一第一表面 10a及相對之第二表面1 〇b，於該第一表面i〇a及第二表 面l〇b分別形成有一金屬層u，該金屬層n爲導電性佳 110198 5 1330059 之銅金屬材質。 凊麥閱第1B圖，依製程之需要對該金屬層U以化學 或物理方式進行薄化製程以形成薄化金屬層U : 後續圖案化製程中形成線路。 ； 請參閱第1C圖，於該基板10中形成一貫穿該第一表 面10a及第二表面l〇b之通孔1〇〇。 請參閱第1D圖，於該基板10之第一 '第二表面 l〇a’10b之薄化金屬層u，及通孔1〇〇中之表面形成一導 ，層m導電層！2即作爲後續電鍵製程所需之電流傳 請參閱第1E圖，進行電鍍製程以於該導電層12 電鍍形成一金屬層13。 曰 、 請參閱第1F圖，於該表面形成有金屬層13之通孔 1〇〇中填入塞孔材料14，其中’該塞孔材料14_ 環氧樹脂。 為 • 請參閱第1G圖，於該金屬層13及塞孔材料14表面 形成一阻層15,且該阻層15形成有開口 15〇以露出部份 之金屬層13表面。 • 請參閱第1H圖，以化學蝕刻方式移除未為該阻層15 •所覆蓋之金屬層13、導電層丨2及薄化金屬層丨丨^^於 該基板10之第一表面10a及第二表面1〇b上分別形成二 線路層16a，並於該通孔100處形成一電鍍導通孔 (PTH)16b。 請參閱第11圖’最後’移除該阻層i 5 Π0198 6 1330059 惟’該電鍍導通孔16b係於該通孔loo中先形成導電 層12 ’藉由該導電層12以電鍍形成該金屬層13，俾於該 通孔100中之表面形成空心之金屬層13，再以該塞孔材 料14填入該通孔1〇〇中未形成金屬層13之空洞部份，使 δ亥電鍍導通孔16b僅藉由該形成於該通孔100中之表面的 金屬層13電性導通該基板1〇之第一表面10a及第二表面 1 〇b的線路層1 6a，而形成於該通孔i 〇〇中之金屬層i 3 僅為一薄層金屬，其厚度較薄，其電鍍導通孔i 較易斷 _裂，故影響電性傳導功能。 又該電鍍導通孔16b中僅於該通孔丨〇〇中之表面形成 有金屬層13，雖在該空洞中形成有如環氧樹脂之塞孔材 料14，但該塞孔材料14並非金屬材料，其強度低於該金 屬層13,該電鍍導通孔16b之強度幾乎為該金屬層丨^所 擔當，於後續製程中容易因搬移過程中產生之暫態彎曲或 熱痛環製私中所產生之暫態變形，導致該電鍍導通孔1处 _中之金屬層13產生斷裂’致使該電鍍導通孔16b被破壞 而無法作電性傳導，而無法電性連接該基板1〇之第一表 面10a及第二表面i〇b的線路層iga。 此外，若該金屬層13形成於該通孔1〇〇中之表面時， •若電鍍時間及溫度等控制不當，則該金屬層13不容易形 成於該通孔100中之導電層12表面，或該金屬層13形成 厚薄不一，使電鍍導通孔有可靠度問題而影響基板品質。 因此，如何提出一種具有提昇電鍍導通孔強度之電路 板結構，付·^ 1¾結構強度，以避免該電鍵導通孔斷裂，並 110198 7 1330059 避免電鍍導通孔產生空洞以降低電性傳導 蛋需改進的問題。 成為 f發明内容j 鑒於上述習知技術之缺點，本發明之主 疒種電路板結構及其裂法，得增加電鍵導通孔二二 導效率。 电丨王1寻 本發明之又-目的在於提供—種電路板結構及 該電鑛導通孔之強度以避免通孔孔壁之金屬層 峤裂產生電性失效。 曰 本發明之再—目的在於提供—種電路板結構及发制 =得避免該電料通孔產生空洞導致電性傳輸效率 為達上述㈣’本發明提供一種電路板結構，係包 括：一基板，係具有一第一#餿_ 、 -表面盘第一表面… 第-表面、及貫穿該第 該基板孔；第一線路層，係形成於 二 表面及第一表面，並於該通孔中形成有一電 鑛¥通孔；以及電鑛金屬柱，係形成於該 所組成 "^ ,-八” I與文守遇孔中 〇 該第、線路層係由薄化金屬層、導電層及— 成。 不 主鴒層 復包括線路増層結構係形成於該基板及t第 ^表面，且該線路増層結構巾形成有複數導電結構電性遠 =第-線路層，其中該線路增層結構係包括有介電舞、 =於該介電層上之第二線路層，以及形成於該介電屏曰中 電結構’且該線路增層結構表面復包括有複數電二連 110198 8 1330059 .接塾’於該線路增層結構表面復包括有一絕緣保護層1 絕緣保護層表面具有複數個開孔以露出該些電性連接墊: I發明復提供-種電路板結構之製法，係包括：提供 -基板’係具有一第一表面及第二表面，於該第一及第二 表:面具有-金屬層；進行薄化製程以將該金屬層形成一 缚化金屬層；於該基板中形成—貫穿該第-表面及第二 •表面之通孔；於該薄化金屬層及通孔中之表面形成一第 金屬層’於β金屬層表面形成—阻層，且該阻層形成 •複數開口以露出部份之第一金屬層表面；於該阻層開口 中之第-金屬層表面電鍍形成一第二金屬層；移除阻 層；移除未被該第二金屬層所覆蓋之第一金屬層、導電斧 ^化金屬層；以及進行去除第—金屬層表面上之第二金 屬層，以於該通孔中形成一電鍍金屬柱及基板表面之第一 線路層。 依上述之裝法，復包括於該薄化金屬層及第一金屬層 癱^門八有導電層’藉由該導電層以電卿成該第一金屬 復包括於該具有第—線路層之基板表面形成有—線 增層結構，且該線路增層結構+形成有複數導電 .t連接該第—線路層，該線路增層結構係包括有介電層 且置於《•玄介电層上之第二線路層以及形成於該介電層中 =電結構’且該線路増層結構表面復包括有複數電性連 ，該線路增層結構表面復包括有—絕緣㈣層， 緣保護層表面具有複數個開孔以露出該些電性連接^ 110198 1330059 本發明之電路板結構及其製法，係於該基板之通孔 先電鍍形成該第-金屬層’然後形成該阻層，且該阻芦經 圖案化形成開口，以露出部份之第一金屬層及該通孔；之 .第一金屬層，然後再於該第一金屬Μ面電鍍形成該第二 金屬層，且於該通孔中之孔洞中電艘形成該電鑛金屬柱， 以於該通孔中形成實心之電鑛導通孔，使該電鑛導通孔係 由電鑛形成之第-金屬層及電鑛金屬柱組成，該第一金屬 層及電鍍金屬柱皆為金屬，俾得增加電鍍導通孔之電性傳 籲導效率’並提高結構強度以避免該電Μ導通孔孔壁金屬層 斷裂，以防止電性連接失效。 【實施方式】 以下之實施例係進一步詳細說明本發明之觀點，但並 非以任何觀點限制本發明之範疇。 如第2Α至第2J圖所示，係詳細說明本發明之電路板 結構之製法較佳實施例之剖面示意圖。 籲 凊苓閱第2Α圖，提供一基板20，且該基板20具有 第表面20a及第二表面20b，於該第一表面20a及第 二表面20b分別形成有一金屬層21，該金屬層21爲導電 •性佳之銅金屬材質。其中該基板20係為一銅箔基板 (Copper Clad Laminates : CCL)及内已形成有線路層且第 一、第二表面壓合有背膠銅箔（Resin C〇ated Copper)之 基板之其中一者。 請參閱第2B圖，對該金屬層21以化學或物理方式進 行濤化製程以形成一薄化金屬層21，，以利於後續線路圖 10 110198 1330059 案化製程中提供形成線路。 。月參閱第2C圖’於該基板2〇中形成至少一貫穿該第 一表面別a及第二表面2〇b之通孔2〇〇。 叫麥閱第2D圖’於該薄化金屬層21，及通孔200中 之表面以化學沉積形成一導電層22，該導電層22主要作 為後述電鑛金屬材料所需之電流傳導路徑，其可由金屬或 沉積數。層金屬層所構成，如選自銅、錫、鎳、鉻、鈦、銅1330059. IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board structure and a method of fabricating the same, and more particularly to forming a plated metal column in a keyhole of a circuit board : A circuit board structure that increases the electrical conduction efficiency of the plated via and a method of fabricating the same. [Prior Art] μ ' With the development of semiconductors and the computational needs of high-performance chips, boards need to improve signal transmission and improve bandwidth control impedance. However, in order to meet the development trend of thin, versatile, high-speed and high-frequency semiconductor packages, the board has been developed toward thin lines and small apertures. Existing circuit board processes have been reduced from conventional 100 micron line sizes including line width and space spacing to 2 微米 micron and continue to develop toward smaller line accuracy. In order to improve the wiring precision of the circuit board for semiconductor chip packaging, the industry has developed a layering technology (Bui ld_up), that is, a layer-on-layer multilayer dielectric is alternately stacked on the surface of a core circuit board by a line build-up technology. a layer and a circuit layer, and forming a plating via (pTH) penetrating the core board for electrically connecting the lines of the lower surface of the core board, and the process of the plating via hole affects the circuit board density, the core The circuit board is manufactured as shown in Figures 1A to 1F. Referring to FIG. 1A, a substrate 1A of a copper foil substrate (CCL) having a first surface 10a and an opposite second surface 1 〇b is provided. The first surface i〇a and the second surface 10b are respectively formed with a metal layer u, which is a copper metal material with good conductivity of 110198 5 1330059. Referring to Figure 1B, the metal layer U is chemically or physically thinned to form a thinned metal layer U as required by the process to form a line in a subsequent patterning process. Referring to FIG. 1C, a through hole 1 through the first surface 10a and the second surface 10b is formed in the substrate 10. Referring to FIG. 1D, a thin metal layer u on the first 'second surface l〇a' 10b of the substrate 10, and a surface in the via hole 1 形成 form a conductive layer m conductive layer! 2, the current required for the subsequent key processing. Referring to FIG. 1E, an electroplating process is performed to electroplate the conductive layer 12 to form a metal layer 13. 、 , Referring to FIG. 1F, a via hole 1 is formed in the through hole 1 of the surface on which the metal layer 13 is formed, wherein the plug material 14_ epoxy resin. For example, referring to FIG. 1G, a resist layer 15 is formed on the surface of the metal layer 13 and the plug material 14, and the resist layer 15 is formed with an opening 15 to expose a portion of the surface of the metal layer 13. • Referring to FIG. 1H, the metal layer 13, the conductive layer 及2, and the thinned metal layer not covered by the resist layer 15 are removed by chemical etching to the first surface 10a of the substrate 10 and A second wiring layer 16a is formed on the second surface 1b, and a plating via (PTH) 16b is formed in the via 100. Please refer to FIG. 11 'final' to remove the resistive layer i 5 Π 0198 6 1330059. Only the electroplated via 16b is formed in the via loo first to form a conductive layer 12'. The conductive layer 12 is used to form the metal layer by electroplating. 13. A hollow metal layer 13 is formed on the surface of the through hole 100, and the hole portion 14 is filled with the hole portion of the through hole 1 and the metal layer 13 is not formed. 16b is formed in the through hole i only by the metal layer 13 formed on the surface of the through hole 100 electrically electrically connecting the first surface 10a of the substrate 1 and the wiring layer 16a of the second surface 1 〇b. The metal layer i 3 in the crucible is only a thin layer of metal, and its thickness is thin, and the electroplated via hole i is relatively easy to break and crack, thus affecting the electrical conduction function. Further, in the plating via hole 16b, a metal layer 13 is formed only on the surface of the via hole, and although a plug material 14 such as an epoxy resin is formed in the cavity, the plug material 14 is not a metal material. The strength of the electroplated via hole 16b is almost the same as that of the metal layer. In the subsequent process, it is easy to be generated by the transient bending or heat pain generated during the moving process. The transient deformation causes the metal layer 13 in the plating via 1 to be broken, so that the plating via 16b is broken and cannot be electrically conducted, and the first surface 10a of the substrate 1 cannot be electrically connected. The circuit layer iga of the second surface i〇b. In addition, if the metal layer 13 is formed on the surface of the through hole 1 , if the plating time and temperature are not properly controlled, the metal layer 13 is not easily formed on the surface of the conductive layer 12 in the through hole 100. Or the metal layer 13 is formed to have different thicknesses, so that the plating vias have reliability problems and affect the quality of the substrate. Therefore, how to propose a circuit board structure with improved plating via strength, paying the structural strength to avoid the breakage of the conductive via hole, and 110198 7 1330059 to avoid voiding in the plating via hole to reduce the need for improvement of the electrically conductive egg problem. In view of the above-mentioned shortcomings of the prior art, the main circuit board structure of the present invention and the cracking method thereof have to increase the efficiency of the conductive vias. Further, the present invention aims to provide a circuit board structure and the strength of the electroconductive via hole to prevent electrical failure of the metal layer of the through hole wall. A further object of the present invention is to provide a circuit board structure and a manufacturing system to avoid the occurrence of voids in the through hole of the electric material, thereby causing electrical transmission efficiency to reach the above (4). The present invention provides a circuit board structure including: a substrate , having a first #馊_, a first surface of the surface disk, a first surface, and a through hole of the substrate; a first circuit layer formed on the two surfaces and the first surface, and in the through hole Forming an electric ore through hole; and an electric ore metal column formed in the composition of the "^, -8" I and Wenshouyu hole, the first, the circuit layer is made of a thinned metal layer, a conductive layer and The non-main layer layer includes a circuit layer structure formed on the substrate and the t-th surface, and the line layer structure towel is formed with a plurality of conductive structures electrically far=the first line layer, wherein the line layer is formed The structure includes a dielectric dance, a second circuit layer on the dielectric layer, and an electrical structure formed in the dielectric screen, and the surface of the circuit build-up structure includes a plurality of electrical interconnections 110198 8 1330059 The interface is included in the surface of the added structure of the line. An insulating protective layer 1 has a plurality of openings on the surface of the insulating protective layer to expose the electrical connecting pads: 1. The invention provides a method for manufacturing a circuit board structure, comprising: providing a substrate having a first surface and a surface having a - metal layer on the first and second surfaces; a thinning process to form the metal layer into a metallization layer; forming in the substrate - through the first surface and the second surface a through hole; a surface of the thin metal layer and the through hole is formed with a first metal layer forming a resist layer on the surface of the β metal layer, and the resist layer forms a plurality of openings to expose a portion of the surface of the first metal layer Forming a second metal layer on the surface of the first metal layer in the opening of the resist layer; removing the resist layer; removing the first metal layer not covered by the second metal layer, and the conductive metal layer; And removing the second metal layer on the surface of the first metal layer to form a first metal layer of the plated metal pillar and the surface of the substrate in the through hole. According to the above method, the thin metal layer is included The first metal layer 瘫^门八 has a conductive layer' Forming, by the conductive layer, the first metal compound, the surface of the substrate having the first circuit layer is formed with a line-enhanced structure, and the line build-up structure + is formed with a plurality of conductive lines. a layer, the line build-up structure includes a dielectric layer and is disposed on the "the second circuit layer on the mysterious dielectric layer and formed in the dielectric layer = electrical structure" and the surface layer structure includes In the plurality of electrical connections, the surface of the line-increasing structure includes an insulating (four) layer, and the surface of the edge protective layer has a plurality of openings to expose the electrical connections. 110198 1330059 The circuit board structure of the present invention and the method for manufacturing the same are The through hole of the substrate is first plated to form the first metal layer and then the resist layer is formed, and the resist is patterned to form an opening to expose a portion of the first metal layer and the through hole; the first metal layer And forming the second metal layer by electroplating on the first metal surface, and forming an electric ore metal pillar in the hole in the through hole to form a solid electric ore conduction hole in the through hole. Making the electric ore conduction hole system formed by electric ore The first metal layer and the electroplated metal column are composed of a metal, and the first metal layer and the electroplated metal column are all metal, so as to increase the electrical transmission efficiency of the electroplated via hole and improve the structural strength to avoid the electric conduction via hole. The wall metal layer breaks to prevent electrical connections from failing. [Embodiment] The following examples are intended to describe the present invention in further detail, but do not limit the scope of the invention in any way. As shown in Figs. 2 to 2J, a cross-sectional view showing a preferred embodiment of the method of manufacturing the circuit board structure of the present invention will be described in detail. Referring to FIG. 2, a substrate 20 is provided, and the substrate 20 has a first surface 20a and a second surface 20b. A metal layer 21 is formed on the first surface 20a and the second surface 20b, respectively. Conductive and good copper metal. The substrate 20 is a copper foil substrate (CCL) and one of the substrates on which the circuit layer is formed and the first and second surfaces are laminated with a backing copper foil (Resin C〇ated Copper). By. Referring to FIG. 2B, the metal layer 21 is chemically or physically subjected to a structuring process to form a thin metal layer 21 to facilitate the formation of a wiring in the subsequent circuit diagram 10110198 1330059. . Referring to FIG. 2C, at least one through hole 2〇〇 penetrating through the first surface a and the second surface 2〇b is formed in the substrate 2A. The surface of the thinned metal layer 21 and the through hole 200 is chemically deposited to form a conductive layer 22, which is mainly used as a current conduction path required for an electric ore metal material to be described later. Can be metal or deposited. Layer metal layer, such as selected from copper, tin, nickel, chromium, titanium, copper
釔等單層或多層結構’亦可選用例如聚乙炔、聚苯胺或 有機k聚合物等導電高分子材料；其中該化學沉積係如 無電電鑛（electrQless plating)或化學氣相沈積 (chemical vapor dep〇siti〇n)，物理沉積係如物理氣相 ，積（physicai vap〇r dep〇siti〇n)或濺鍍 & 卯 ttering) 等方式分別形成。 凊參閱第2E圖，於該基板2〇之第一、第二表面 2〇a’20b之薄化金屬層21，及通孔200中之導電層22表 籲面，藉由該導電層22作為電鍍之電流傳導路徑以形成一 第金屬層23 ’該第一金屬層23之材料可為諸如鉛、錫、 銀鋼、金、纽、銻、鋅、錄、錯、鎂、銦、碲以及鎵等 .金Ϊ之其中—者；惟’依實際操作之經驗，由於銅為成熟 .之電鍍材料且成本較低，但非以此為限。 請參閱第2F圖，於該第一金屬層23表面形成一阻層 24,且進行圖案化製程以於該阻層24中形成複數開口日 以路出部份之第一金屬層23表面，並露出該通孔 中之第一金屬層23。 110198 11 1330059 凊參閱第2G圖，藉由該導電層22及第一金屬層23 作為電流傳導路徑以於該阻層24之開口 24〇中電鍍a形成 二第二金屬層25，並於該通孔200之孔洞中電鍍升^成一' 電鍍金屬柱251;該第二金屬層25之材料可 錫 '銀、銅、金、-、錄、辞、錄、錐、鎮、鋼、碲:及 t!金屬之其中一者；·准，依實際操作之經驗，由於鋼： 成熟之電鍍材料且成本較低，但非以此為限。 請參閱第2H圖，接著，移除該阻層24，並 _金屬層25當化學姓刻之阻層，以移除未被該第二 25所覆蓋之第一金屬層23、導電層22及薄化金屬層：層。 凊參閱第21圖’移除該第一金屬層23表面上之 金屬層25,俾於該基板2〇之第一表面2叱及 一 鍍導通孔26b。 Μ成-電 請參閱第2J圖’於該具有第一線路層咖之基板表 ♦勺二面&成有線路增層結構27，該線路增層結構27係 ^有”電層271、豐置於該介電層上之第二線路層。 =，以及形成於該介電層271中之係如導電盲孔之導電 :構Π3,其中部份之複數導電結構⑺電 ^層咖’且該線路增層結構27表面復包 二 塾:74，：該線路增層結構-表面形成有-係Γ /之、，，巴緣保4層28,該絕緣保護層28表面形成有複 28==°以露出該些電性連接塾274;該絕緣保護層 別係為有機及無機之抗氧化膜之任一具有縮錫特性之/ 110198 12 1330059 焊層材料所製成，並非以綠漆為限。 本發明復提供一種電路板結構，係包括：基板2〇， 係具有一第一表面20a及第二表面20b;至少一通孔 2〇〇,係貫穿該基板20之第一表面20a及第二表面施； 第一線路層26a，係形成於該基板2〇之第一表面2〇&及 第二表面20b，並於該通孔200中形成有一電料通孔 26b;以及電鍍金屬柱251，係形成於該電鐘導通孔_ 中。 該第-線路層26a係包括有薄化金屬層21，、導電層 22及第一金屬層23。 復包括線路增層結構27係形成於該具有第一線路層 a之基板20表面，該線路增層結構打係包括有介電層 271、疊置於該介電層上 第_ 电層上之弟一線路層272，以及形成於 ^電層271中之係如導電盲孔之導電結構m，其中部 =複數導電結構273電性連接該第—線路層咖，且該 、.增層結構27表面復包括有複數電性連接塾m，於 層結構27表面形成有—係如防焊層之絕緣保護 ^此二、邑緣保4層28表面形成有複數個開孔280以露 保4層28係為有機及無 几 膜之任一具有縮錫特性之防焊層材料所f 成，並非以綠漆為限。 先電1發Γ之電路板結構及其製法，係於該基板之通孔中 圖案化形成開口，以露出背^成該=且該阻層經 邛伤之弟一金屬層及該通孔中之 110198 13 1330059 * · 第一金屬層，然後再於該第一金屬層表面電鍍形成該第二 金屬層，且於該通孔中之孔洞電鍍形成該電鍍金屬柱，以 =該通孔中形成實心之電鍍導通孔，使該電鍍導通孔係由 電鍍形成之第一金屬層及電鍍金屬柱組成，該第一金屬層 及皂鑛金屬柱皆為金屬，俾得增加電鐘導通孔之電性傳導 效率’並提高結構強度以避免該電鍍導通孔孔壁斷裂，以 防止電性連接失。 上述實施例僅例示性說明本發明之原理及其功效，而 •非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與改 變。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 【圖式簡單說明】 第1A至II圖係為習知電路板中形成電鍍導通孔之製 法剖視圖；以及 鲁 苐2A至第2 J圖係為本發明之電路板結構及其製法之 剖視示意圖。 【主要元件符號說明】 10、20 基板 10a ' 20a 第一表面 l〇b 、 20b 第二表面 100 、 200 通孔 11， 、 21, 薄化金屬層 12、22 導電層 110198 14 1330059 « 4 11 、 2卜 13 金屬層 14 基孔材料 15、24 阻層 150 ' 240 開口 16a 線路層 16b、26b 電鍍導通孔 173 、 273 導電結構 23 第一金屬層 25 第二金屬層 251 電鍍金屬柱 26a 第一線路層 27 線路增層結構 271 介電層 272 第二線路層 274 電性連接墊 28 絕緣保護層 280 開孔 15 110198Conductive polymer materials such as polyacetylene, polyaniline or organic k polymer may also be selected as a single layer or a multilayer structure; the chemical deposition system such as electrQless plating or chemical vapor dep 〇siti〇n), physical deposition systems such as physical gas phase, physicai vap〇r dep〇siti〇n or sputtering & 卯ttering) are formed separately. Referring to FIG. 2E, the thinned metal layer 21 on the first and second surfaces 2〇a'20b of the substrate 2 and the conductive layer 22 in the via 200 are surface-surfaced by the conductive layer 22 Electroplating current conduction path to form a first metal layer 23'. The material of the first metal layer 23 may be, for example, lead, tin, silver steel, gold, neon, antimony, zinc, germanium, germanium, magnesium, indium, germanium, and gallium. Etc. Among them, there is only one of them; however, due to the experience of actual operation, copper is a mature electroplating material with low cost, but not limited to this. Referring to FIG. 2F, a resist layer 24 is formed on the surface of the first metal layer 23, and a patterning process is performed to form a plurality of opening days in the resist layer 24 to form a surface of the first metal layer 23. The first metal layer 23 in the via hole is exposed. 110198 11 1330059 第 Referring to FIG. 2G, the conductive layer 22 and the first metal layer 23 are used as current conduction paths to form a second metal layer 25 by electroplating a in the opening 24 of the resist layer 24, and The hole in the hole 200 is plated into a 'plated metal column 251; the material of the second metal layer 25 can be tin 'silver, copper, gold, -, recorded, reciting, recorded, cone, town, steel, 碲: and t One of the metals; quasi-, based on practical experience, due to steel: mature plating materials and low cost, but not limited to this. Referring to FIG. 2H, the resist layer 24 is removed, and the metal layer 25 is chemically resisted to remove the first metal layer 23 and the conductive layer 22 not covered by the second 25 and Thinned metal layer: layer. Referring to Fig. 21, the metal layer 25 on the surface of the first metal layer 23 is removed, and the first surface 2 of the substrate 2 and a plating via 26b are formed. Μ成-电, please refer to the 2J figure 'in the substrate with the first circuit layer, the table ♦ scoop two sides & into the line-added structure 27, the line build-up structure 27 system has "electric layer 271, Feng a second circuit layer disposed on the dielectric layer. =, and a conductive layer formed in the dielectric layer 271, such as a conductive via hole: a structure 3, wherein a portion of the plurality of conductive structures (7) The surface of the line build-up structure 27 is covered with two turns: 74: the line build-up structure - the surface is formed with - system / /,, the edge of the edge of the 4 layers 28, the surface of the insulating protective layer 28 is formed with a complex 28 = = ° to expose the electrical connection 塾 274; the insulating protective layer is made of any of the organic and inorganic anti-oxidation film having a tin-reducing property / 110198 12 1330059 solder layer material, not in green paint The present invention further provides a circuit board structure comprising: a substrate 2 having a first surface 20a and a second surface 20b; at least one through hole 2〇〇 extending through the first surface 20a of the substrate 20 and a first surface layer 26a is formed on the first surface 2〇& and the second surface 20b of the substrate 2 An electric material through hole 26b is formed in the through hole 200; and an electroplated metal post 251 is formed in the electric clock through hole_. The first circuit layer 26a includes a thinned metal layer 21, a conductive layer 22 and a first a metal layer 23. The circuit-generating structure 27 is formed on the surface of the substrate 20 having the first circuit layer a, and the circuit-generating structure includes a dielectric layer 271 and is stacked on the dielectric layer. a circuit layer 272 on the electrical layer, and a conductive structure m formed in the electrical layer 271, such as a conductive blind hole, wherein the middle portion = the plurality of conductive structures 273 are electrically connected to the first circuit layer, and The surface of the build-up structure 27 includes a plurality of electrical connections 塾m, and the surface of the layer structure 27 is formed with an insulation protection such as a solder resist layer. 2. The surface of the layer 4 is formed with a plurality of openings 280. It is not limited to green paint, and it is not limited to green paint. It is not limited to green paint. The circuit board structure and its manufacturing method are the first one. Forming an opening in the through hole of the substrate to expose the back of the hole and the resisting layer a layer of 110198 13 1330059* in the via layer and a first metal layer, and then electroplating the surface of the first metal layer to form the second metal layer, and the holes in the via hole are plated to form the plated metal pillar, Forming a solid electroplated via hole in the through hole, the electroplating via hole is composed of a first metal layer and a plated metal pillar formed by electroplating, and the first metal layer and the soap metal pillar are all metal, and the crucible is increased. The electrical conduction efficiency of the conductive vias of the electric clock increases the structural strength to prevent the electroplated via hole from being broken to prevent electrical connection loss. The above embodiments merely exemplify the principle and function of the present invention, and are not used. To limit the invention. Modifications and alterations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1 are a cross-sectional view showing a method of forming a plating via hole in a conventional circuit board; and a retrusion 2A to a second J diagram showing a schematic diagram of a circuit board structure and a manufacturing method thereof according to the present invention. . [Major component symbol description] 10, 20 substrate 10a ' 20a first surface l〇b, 20b second surface 100, 200 through hole 11, 21, thinned metal layer 12, 22 conductive layer 110198 14 1330059 « 4 11 2 13 13 metal layer 14 base material 15, 24 resist layer 150 '240 opening 16a circuit layer 16b, 26b plating via 173, 273 conductive structure 23 first metal layer 25 second metal layer 251 electroplated metal column 26a first line Layer 27 Line build-up structure 271 Dielectric layer 272 Second line layer 274 Electrical connection pad 28 Insulation protection layer 280 Opening 15 110198