TWI324382B - Apparatus having reduced warpage in an over-molded ic package and method of reducing warpage in an over-molded ic package - Google Patents

Apparatus having reduced warpage in an over-molded ic package and method of reducing warpage in an over-molded ic package Download PDF

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Publication number
TWI324382B
TWI324382B TW095123541A TW95123541A TWI324382B TW I324382 B TWI324382 B TW I324382B TW 095123541 A TW095123541 A TW 095123541A TW 95123541 A TW95123541 A TW 95123541A TW I324382 B TWI324382 B TW I324382B
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Taiwan
Prior art keywords
dummy circuit
circuit pattern
substrate
stress
dummy
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Application number
TW095123541A
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Chinese (zh)
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TW200721417A (en
Inventor
Hem Takiar
Shrikar Bhagath
Ken Jian Ming Wang
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Sandisk Corp
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Publication date
Priority claimed from US11/171,095 external-priority patent/US20070004094A1/en
Priority claimed from US11/170,883 external-priority patent/US20070001285A1/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200721417A publication Critical patent/TW200721417A/en
Application granted granted Critical
Publication of TWI324382B publication Critical patent/TWI324382B/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.

Description

工324382 九、發明說明： 【發明所屬之技術領域】 本發明之具體實施例係關於一種形成一晶片載體基板以 防止翹曲之方法以及藉此形成之晶片載體。 【先前技術】 可攜式消費電子產品之需求強勁增長，從而推動對高容 量儲存裝置之需求。非揮發性半導體記憶體裝置（例如， 決閃5己憶體儲存卡）之使用趨於廣泛’以滿足對數位資訊 儲存及交換之日益增長的需求。其可攜性、通用性及堅固 的設計，連同其較高的可靠性及大容量，使得此類記憶體 裝置成為應用於各種電子裝置（例如，包括數位相機、數 位音樂播放器、視訊遊戲器、PDA及蜂巢式電話）的理想 選擇。 〜 快閃記憶卡之-範例性標準係所謂的SD(安全數位）快閃 記憶卡。過去’諸如SD卡之類的電子器件已包括由若干個 別封裝的積體電路組成之一積體電路（&quot;ic”）系統，盆中每 :積體電路處置不同功能，包括用於資訊處理之邏輯電 I/O用於儲存資訊之記憶體及用於與外界進行資訊交換之 (例如/該等個別封裝的積體電路係分別安裝於一基板 卩刷電路板)上以形成該積體電路系統 ^系統級封裝（，，SiP”)及多晶片额（&quot;M = 複數個積體電路組件封 中已將 完整的電子系絶一 一封裝中提供- 板上而-後封二 一 _包括並排安裝於-基 裝起來的複數個晶片。—Sip-般包括複數 112492.doc 1324382 個晶片’該複數個晶片中的部分或全部晶片可以係堆疊於 一基板上而然後封裝起來。 上面可安裝該等晶粒及被動組件之基板一般包括一剛性 或軟性&quot;電基底’該基底具有在一或二側上受到钱刻之一 導電層。在該晶粒與該（等）導電層之間形成電連接，而該 (等）導電層提供一電氣引線結構以將該晶粒整合進一電子 系統。一旦形成該晶粒與基板之間的電連接，一般便將該 裝配件包覆於一模製化合物内以提供一保護性封裝。 圖1顯示包括一經蝕刻導電層之一傳統基板20之一表 面。該基板20包括一用以在安裝於該基板上的各組件之間 以及在該等基板組件與外部環境之間傳輸電氣信號之電導 圖案22。該電導圖案可具有任何數目的組態並在該基板上 佔據各種數量的空間。過去，已認識到若從不形成該電導 圖案之部分的區域完全蝕刻掉該基板之一表面上的導電 層，則此會導致各區域具有不同的熱膨脹特性，而且在積 體電路封裝製造期間會因加熱該基板而引起該基板内的機 械應力積聚。該電導圖案之金屬往往會因受熱而膨脹，且 由於有些區埠有金屬而有些區域沒有金屬，因此導致該基 板内產生應力。在不形成該導電層之部分的導電層區域完 全保持原狀之情況下，觀察到同樣的現象。此等應力往往 令該基板產生翹曲。翹曲的基板可產生機械應力，並在將 該半導體晶粒黏接至該基板之時或之後導致該半導體晶粒 破裂。 因此，人所皆知應在該基板上不用於該電導圖案之區域 H2492.doc 1324382 中钱刻—所謂的虛擬圖案。例如，料Tsai的名稱為，，基板 • 中=圖案佈局結構&quot;之美國專利案第6,38〇,633號揭示形成 交叉陰衫虛δ又圖案，例如圖i所示在基板2〇上不用於電 導圖案22之區域26、28及3〇中形成的虛設圖案24。虛設圖 案24藉由減低該基板上具有—電導圖案的區域與該基板上 不具有電導圖案的區域之間的不同熱性特性，來提供更高 的半導體良率。 本發明之發明者已進一步認識到當該虛設圖案24係置放 ^ 於長直線中時，仍會產生熱應力。特定言之，已發現熱應 力積聚於一虛設圖案跡線之一直線區段上，在此情況下， 隨著該熱應力增加，該直線區段之長度變長。頒予[以叫 . 等人的名稱為'1翹曲防止電路板及其製造方法，，之美國專利 案第6,864,434號揭示如Tsai申請案中所提出之一交叉陰影 . 虛設圖案，但Chang等人將該虛設圖案分成複數個區域。 儘管Chang等人與Tsai相比有提高，但Chang等人仍揭示在 該基板上具有直線區段之一系統，該等直線區段導致該基 板内產生應力。隨著半導體晶粒變得更薄而且更精緻，最 小化該基板内的應力變得更加重要。 【發明内容】 大致說明的本發明之具體實施例係關於一種形成一晶片 ' 載體基板以防止翹曲之方法以及藉此形成之晶片載體。該 &gt; 基板包括一用以在晶粒與該基板上的組件之間傳輸電氣信 號之電導圖案以及一用於防止該基板在該電導未佔據的區 域中產生翹曲之虛設電路圖案》 I12492.doc 1324382 該虛設電路圖案可具有直線區段，該等直線區段之一長 * 度受控制以至於不會在該等線區段内產生高於一所需應力 ，之應力。可用實驗方法藉由決定一直線區段内與長度成函 數關係之應力來決定一直線區段之所需長度，並接著將該 長度没疋為低於一給定直線區段内之一所需最大應力。或 者，可依據該基板中所用材料之已知特性來估計一線區段 之所需長度。 該虛設電路圖案可形成為複數個線、形狀及尺寸。在一 • 項具體實施例中，該虛設電路圖案可由複數個多邊形（例 如六邊形）形成。該等多邊形可能彼此相鄰，或者該等多 邊形可能彼此間隔。此外，該等多邊形中的每一多邊形之 尺寸可能彼此相同，或者該虛設電路圖案可包括不同尺寸 的多邊形。 . 在替代性具體實施例中，該虛設電路圖案可由形成於該 基板上具有隨機形狀之多邊形形成。該等隨機形狀還可以 係隨機定向及/或隨機定位於該基板上。該等隨機形狀可 能係彼此相鄰，或者在替代性具體實施例中其可能係彼此 間隔。 作為隨機形狀之一替代形狀，該虛設電路圖案進一步可 以係由該基板上的隨機線形成。在替代性具體實施例中， 該等線在該虛設電路圖案上可具有一隨機定向、隨機長度 及/或一隨機位置。 該虛設電路圖案可以係與該電導圖案一起形成於一光罩 上，而接著係在一已知的蝕刻程序中蝕刻進該基板頂部及 112492.doc -9- 1324382 /或底部上的導電層β 【實施方式】 現將參考圖2至12來說明本發明之具體實施例，其係關 於形成一減低翹曲的半導體封裝之一方法以及藉此形成之 半導體封裝。應瞭解，本發明可具體化為許多不同形式， 而不應將其解釋為受限於此處所提出的具體實施例。實際 上，所提供的此等具體實施例使得此揭示内容將更為詳盡 而完整，並將完全傳達本發明之範圍給熟習此項技術者。 的確，本發明意欲涵蓋隨附申請專利範圍所定義的本發明 範嘴及精神内所包括的此等具體實施例之替代方案、修改 方案及等效方案。此外，在下面關於本發明之詳細說明 中’提出許多特定細節以便於完全地瞭解本發明β但是， 熟習此項技術者將明白’即使不使用此類特定細節亦可實 施本發明。 圖2係一晶片載體基板1〇〇之一俯視圖，而圖3係透過與 該基板100的頂部及底部平面正交之一平面之一斷面圖。 從圖3看出，基板1〇〇可具有一頂部表面ι〇2與一底部表面 1 〇4。基板1 〇〇可由一電性絕緣的核心1 〇6形成，該核心具 有一形成於該核心之一頂部表面上的頂部導電層1〇8與一 形成於該核心之一底部表面上的底部導電層110。該核心 可由各種介電材料（例如，聚醯亞胺層壓物、包括FR4與 FR5之環氧樹脂、馬來酿亞胺三嗪（ΒΤ)及類似物）形成。儘 管對於本發明而言並非關鍵，但核心106厚度可介於4〇微 米（μηι)至200 μιη之間，但在替代性具體實施例中該核心之 112492.doc -10· 厚度可變化超出該範圍。在替代性具體實施例中，該核心 可能係陶瓷或有機材料。 該等導電層108及110可由銅、銅合金或其他低電阻電性 導體形成’且可以係如下文所說明依據本發明之具體實施 例圖案化為一電導圖案及虛設電路。該等層1〇8及/或11〇 之厚度可約為10 μπι至24 μιη ’但在替代性具體實施例中該 等層108及11〇之厚度可變化超出該範圍。一旦圖案化，該 4頂部及底部導電層便可分別與一焊料遮罩U2、114層壓 在一起’此在此項技術中已為人所知。 可將基板100圖案化並配置用於各種半導體封裝。一此 類封裝係一所謂的平臺柵格陣列（LGA)半導體封裝，其係 用於（例如）SD快閃記憶卡。但是，應瞭解下文所說明的虛 設電路圖案可用於任何基板上，一電導圖案可形成於該基 板内並裝配進一半導體器件。 再來參考圖2，可如下文之說明將該等導電層108與11〇 中的一或二層蝕刻或以其他方式處理成包括一電導圖案 120 ’以在安裝於基板100的組件之間以及基板100上的組 件與外部器件之間提供電連接。有些具體實施例在基板 100的頂部表面102及底部表面1〇4上以及在包括複數個頂 部及底部層之基板中包括電導圖案（如下文結合圖9之說 明）’則在此等具體實施例中可提供通道（未顯示）以在不同 層中的電導圖案之間發射電氣信號。 基板100進一步包括不具有一電導圖案的複數個區域 122、124 ' 126，本文中稱為虛設電路區域。可在該等虛 112492.doc 1324382 设電路區域122、124、126之一或多個區域中形成依據本 發明之具體實施例之一虛設電路圖案13〇 β應瞭解，在本 發明之替代性具體實施例中基板1〇〇之尺寸及形狀以及電 導圖案102之尺寸及形狀可有很大改變，以便定義任何尺 寸或形狀之一或多個虛設電路區域。虛設電路可以係 提供於此等虛設電路區域之任一或任何多個區域中。在具 體實施例中，依據下文所說明的任一具體實施例之一虛設 電路圖案可以係提供於該基板之二側上，即使在一電導圖 案係僅提供於該基板之一側上之情況下。可構思一基板可 用於一半導體器件，該器件在該基板之第一或第二相對表 面上不包括一電導圖案《此一基板可以係形成為具有依據 本發明之具體實施例之一虛設電路圖案。 在下文S兒明的母一具體實施例中，該虛設電路圖案係由 線及/或形狀組成。該等線及/或形狀係以一給定密度提供 於該一或該等多個虛設電路區域中。密度表示就該基板上 每一單位面積而言，形成一虚設電路圖案或該電導圖案之 導電跡線中的材料數目、長度及/或數量。 一虛設電路圖案之一部分中之一直線區段内的應力位準 將係線性或非線性’此與該基板受熱時該直線區段之長度 有關。一般地，該長度越長，則因加熱而產生的應力越 大。 對於依據下文所S兑明具體實施例之一虛設電路圖案之任 何部分中一直線區段之最大長度，可將該直線區段長度設 定成讓該直線區段内的應力保持低於一所需位準。特定令 112492.doc •12· 1324382 之，可憑經驗及/或與所用材料類型呈函數關係的該基板 材料之已知實體特徵及行為、所用材料之厚度及該等材料 將經歷的溫度範圍，來決定該虛設電路之一部分之一直線 區段之每一單位長度的應力。在分析中還可包括其他特 徵》 給疋此負訊’可將該虛設電路之一部分之一直線區段之 最大長度選擇成讓該區段内的應力保持低於任何所需的預 定位準。換言之，由於知道每一單位長度積聚的應力，因 此可選擇一所需的最大應力，而因此可將一虛設電路中直 線區段之全部或一部分之長度設定成讓一應力保持處於或 低於所選擇的應力位準。應瞭解，無需對每一單位長度的 應力作定篁分析，而在本發明之具體實施例中可替代地估 汁一直線區段之最大長度。還應瞭解，本發明之具體實施 例中一虛設電路圖案可包括直線區段，該等直線區段中超 過一預定最大值的應力可導致該些區段受熱膨脹。 對於一虛設電路圖案之密度，不考慮對一基板内的應力 可能有作用之其他因素，當該虛設圖案之密度接近該電導 圖案之密度時可使得該基板内的應力最小化。因此，在本 發明之具體實施例中可將一虛設電路圖案之密度選擇為接 近-基板上-給；t的電導圖案之密度。或者，可將該虛設 電路圖案之密度選擇為大於或小於該電導圖案之密度，以 使得該基板上所產生的應力保持於預定的可接受位準内。 應瞭解，無需對由於該虛設電路圖案與電導圖案之間的密 度差異而產生之應力作-定量分析，而在本發明之具體實 112492.doc 13 1324382 施例中可替代地估計該虛設電路圖案之密度。 在圖2所示具體實施例中，該虛設電路圖案130係由姓刻 進層108及/或11〇之複數個相鄰對齊單元13〇，形成。該等相 鄰單兀中的每一單元之形狀可一致，而且適配在一起以至 於在該等單元之間不留下任何間隔。應瞭解，在替代性具 體實知I»例中個別早元可適配在一起以至於在其間留下一間 隔°將圖案130蝕刻或以其他方式處理成沒有任何直線延 伸穿過任何兩個相鄰單元13〇，。在圖2所示具體實施例中， 該等個別單元130,係六邊形，從而形成一蜂房圖案130。但 是’應瞭解，在替代性具體實施例中可使用其他形狀，例 如相鄰的圓形、八邊形及其他多邊形（除三角形、矩形及 方形以外）^ (在相鄰形狀互不對齊以至於沒有任何直線延 伸穿過任何兩個相鄰形狀之情況下可使用三角形、矩形及 方形）》 如圖所示’可將形成該圖案13〇的各種直線區段跡線之 長度控制為讓該等直線區段内產生的應力保持低於一預定 的所需應力位準。但是，在具體實施例中，形成每一單元 130之直線區段之長度範圍可在約5〇 與250 μιη之間，而 更特疋5之在70 μιη與150 μιη之間。應瞭解，在替代性具體 貫施例中，單元13〇’區段之最大長度可具有一大於25〇卩爪 而小於50 μιη之最大直徑。在具體實施例中，形成每一單 凡130’各側之個別跡線之寬度可介於約7〇 0111與15〇 ^瓜之 間’但在本發明之替代性具體實施例中每一單元之寬度可 大於或小於此。該等虛設電路區域122至126中的每一區域 H2492.do, 1324382 可包括相同尺寸的單元130，。或者，如圖2所示，一或多個 . 區域（122、124)中的單元可大於其他虛設電路區域（126)中 t 的單元130,。如上所示，可從該等虛設電路區域之一或多 個區域省略虛設電路單元130。此外，如下文所說明，一 給定的虛設電路區域内的個別單元13〇'可具有不同尺寸。 在圖2之具體實施例中，每一個別單元13〇，之形狀一 致。在圖4所示之一第二替代性具體實施例中，該等虛設 區域122、124及126之一或多個區域可包括一虛設電路圖 參 案140，該虛設電路圖案14〇包括複數個不規則的隨機形狀 單元140'。如下文之說明，可在置放於該基板上的圖案遮 罩中產生單元140’之隨機形狀。用於產生該圖案遮罩之一 控制器可包括用以產生隨機形狀之軟體。或者可建立該 . 等隨機形狀之組態，而接著將該資訊傳輸給產生該圖案遮 罩之系統。儘管圖4顯示隨機形狀、直線邊緣的多邊形， 但在本發明之替代性具體實施例中該等單元之一或多 個單元可具有圓形邊緣。 鲁 在具體實施例中，每-隨機形狀單元140,皆可以係定位 於一給定的處設電路區域内之一隨機位置。或者，可將每 -虛設電路區域細分成狀義的子區域，而橫跨各子區域 的單元分佈受到控制，但一給定子區域内一單元14〇|之定 .&amp;㈣機決定。作為另—替代方案，每—隨機形狀單元之 位置可以係預定於一虛設電路區域内。 广圖2之具體實施例中一樣，一般而言，任何兩個相鄰 單元140’皆不會有一延伸穿過其中之連續直線。儘管在此 U2492.doc 15· 具體實施例中兩個隨機 β _ 逍機I狀的早疋之邊緣將對齊，但任何 兩個隨機形狀的相鄰單亓1古 ㈣早疋具有對齊側以至於在其間形成一 直，之機率極h在本㈣之-具體實施例中，_隨機形 單7L 140申任何側之平均長度之範圍可在〇 3咖與i _ 之間。但疋，應日月自，—隨機形狀單元140,中任何側之平 均尺寸可大於或小於本發明之替代性具體實施财的該範 圍此外，應瞭解，在本發明之替代性具體實施例中，與 該平均尺寸的標準偏差可以改變。在具體實施例中，該等 線140,之厚度可約為5〇吨，但在本發明之具體實施例中 此厚度可以改變。 在不同的虛設電路區域122至126令，該等隨機形狀單元 140之平均尺寸可旎相同或不同。同樣，可從該等虛設電 路區域之一或多個區域省略虛設電路圖案14〇。可將該虛 設電路圖案140之密度控制為一般等於、小於或大於如上 所述的電導圖案120之密度。. 在圖4所示具體實施例中，該等單元14〇，之全部或大部 分係封閉的六邊形。在圖5所示之一第三具體實施例中， 一晶片承載基板100可包括一電導圖案12〇與一或多個虛設 電路區域122至126，每一區域包括由隨機定向的線15〇，組 成之一虛設電路圖案150。線150'可以係直的或彎曲的。在 直線情況下，每一線150'之長度可以係選擇為小於一預定 長度。或者’所有線150'之平均長度可以係選擇為低於一 預定值。同樣’一虛設電路圖案150内的線密度可接近該 電導圖案之密度’或可以大於或小於如上所述之電導圖宰 112492.doc •16- 1324382324382 IX. Description of the Invention: [Technical Field] The present invention relates to a method of forming a wafer carrier substrate to prevent warpage and a wafer carrier formed thereby. [Prior Art] Demand for portable consumer electronics has grown strongly, driving demand for high-capacity storage devices. The use of non-volatile semiconductor memory devices (e.g., a flash memory 5 memory card) tends to be broad enough to meet the growing demand for digital information storage and exchange. Its portability, versatility and rugged design, together with its high reliability and large capacity, make such memory devices suitable for use in a variety of electronic devices (for example, including digital cameras, digital music players, video game players). Ideal for PDAs and cellular phones. ~ Flash Memory Card - The exemplary standard is the so-called SD (Safe Digital Digital) flash memory card. In the past, electronic devices such as SD cards have included an integrated circuit (&quot;ic" system consisting of a number of individually packaged integrated circuits, each of which: the integrated circuit handles different functions, including for information processing. The logic electrical I/O is used for storing the information memory and for exchanging information with the outside world (for example, the integrated circuit circuits of the individual packages are respectively mounted on a substrate brush circuit board) to form the integrated body. Circuit system ^ system-in-package (,, SiP) and multi-chip (&quot;M = multiple integrated circuit component packages have been provided in a complete electronic package - on-board and post-sealing _ includes a plurality of wafers mounted side-by-side. - Sip-like includes a plurality of 112492.doc 1324382 wafers. Some or all of the plurality of wafers may be stacked on a substrate and then packaged. The substrate on which the die and passive components can be mounted generally comprises a rigid or flexible &quot;electrical substrate' having one of the conductive layers on one or both sides. The die and the (etc.) conductive layer between Electrically connected, and the conductive layer provides an electrical lead structure to integrate the die into an electronic system. Once the electrical connection between the die and the substrate is formed, the assembly is typically wrapped in a mold. A protective package is provided to provide a protective package. Figure 1 shows a surface of a conventional substrate 20 comprising an etched conductive layer. The substrate 20 includes a substrate for mounting between the components on the substrate and on the substrate A conductance pattern 22 for transmitting electrical signals between the component and the external environment. The conductance pattern can have any number of configurations and occupy a variety of spaces on the substrate. In the past, it has been recognized that if portions of the conductance pattern are never formed The region completely etches away the conductive layer on one surface of the substrate, which in turn causes the regions to have different thermal expansion characteristics, and the mechanical stress accumulation in the substrate is caused by heating the substrate during the manufacture of the integrated circuit package. The metal of the conductance pattern tends to expand due to heat, and since some areas have metal and some areas have no metal, the substrate is The same phenomenon is observed in the case where the region of the conductive layer where the conductive layer is not formed is completely maintained. Such stress tends to cause warpage of the substrate. The warped substrate can generate mechanical stress and When the semiconductor die is bonded to the substrate or after, the semiconductor die is broken. Therefore, it is known that the substrate should not be used in the region of the conductive pattern H2492.doc 1324382 - so-called virtual For example, the name of the material Tsai is, the substrate • medium = pattern layout structure &quot; US Patent No. 6, 38 〇, 633 discloses the formation of a cross-yellow crease δ pattern, such as shown in Figure i on the substrate 2 The dummy pattern 24 formed in the regions 26, 28, and 3 of the conductive pattern 22 is not used. The dummy pattern 24 provides higher semiconductor yield by reducing the different thermal characteristics between the region having the -conducting pattern on the substrate and the region on the substrate having no conductance pattern. The inventors of the present invention have further recognized that thermal stress is still generated when the dummy pattern 24 is placed in a long straight line. In particular, it has been found that thermal stress accumulates on a straight line segment of a dummy pattern trace, in which case the length of the straight line segment becomes longer as the thermal stress increases. [Calling the name of the '1 warpage prevention circuit board and its manufacturing method, U.S. Patent No. 6,864,434 discloses a cross shadow as proposed in the Tsai application. Faux pattern, but Chang et al. The person divides the dummy pattern into a plurality of regions. Although Chang et al. have improved compared to Tsai, Chang et al. disclose a system having a linear section on the substrate that causes stress in the substrate. As semiconductor dies become thinner and more refined, minimizing stress within the substrate becomes more important. SUMMARY OF THE INVENTION A generally illustrated embodiment of the present invention is directed to a method of forming a wafer 'carrier substrate to prevent warpage and a wafer carrier formed thereby. The substrate includes a conductance pattern for transmitting electrical signals between the die and the components on the substrate, and a dummy circuit pattern for preventing warpage of the substrate in an unoccupied region of the conductance" I12492. Doc 1324382 The dummy circuit pattern can have straight sections, one of which is controlled such that no stress is generated above the required stress in the line segments. The experimental method can be used to determine the desired length of the straight section by determining the stress in the straight section as a function of length, and then the length is not reduced to less than the required maximum stress in a given straight section. . Alternatively, the desired length of the line segment can be estimated based on the known characteristics of the materials used in the substrate. The dummy circuit pattern can be formed in a plurality of lines, shapes, and sizes. In a specific embodiment, the dummy circuit pattern can be formed by a plurality of polygons (e.g., hexagons). The polygons may be adjacent to one another or the polygons may be spaced apart from each other. Furthermore, the size of each of the polygons may be the same as each other, or the dummy circuit pattern may include polygons of different sizes. In an alternative embodiment, the dummy circuit pattern may be formed by a polygon having a random shape formed on the substrate. The random shapes can also be randomly oriented and/or randomly positioned on the substrate. The random shapes may be adjacent to each other or they may be spaced apart from each other in alternative embodiments. The dummy circuit pattern may be further formed by a random line on the substrate as an alternative shape to one of the random shapes. In an alternative embodiment, the lines may have a random orientation, a random length, and/or a random location on the dummy circuit pattern. The dummy circuit pattern may be formed on the reticle together with the conductive pattern, and then etched into the top of the substrate and the conductive layer β on the bottom of the substrate at 112492.doc -9-1324382/or in a known etching process. [Embodiment] A specific embodiment of the present invention will now be described with reference to Figs. 2 through 12, which relate to a method of forming a semiconductor package for reducing warpage and a semiconductor package formed thereby. It is understood that the invention may be embodied in many different forms and should not be construed as being limited to the specific embodiments set forth herein. In fact, these specific embodiments are provided so that this disclosure will be more complete and complete, and will fully convey the scope of the invention to those skilled in the art. The present invention is intended to cover alternatives, modifications, and equivalents of the embodiments of the present invention as defined by the appended claims. In addition, many specific details are set forth in the <Desc/Clms Page number>>> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2 is a top plan view of a wafer carrier substrate 1 and FIG. 3 is a cross-sectional view through one plane orthogonal to the top and bottom planes of the substrate 100. As seen in Figure 3, the substrate 1A can have a top surface ι2 and a bottom surface 1 〇4. The substrate 1 〇〇 may be formed by an electrically insulating core 1 〇 6 having a top conductive layer 1 〇 8 formed on a top surface of one of the cores and a bottom conductive layer formed on a bottom surface of one of the cores Layer 110. The core can be formed from a variety of dielectric materials (e.g., polyimide laminates, epoxy resins including FR4 and FR5, maleimide triazine (oxime), and the like). Although not critical to the present invention, the core 106 thickness may be between 4 〇 micrometers (μηι) to 200 μιη, but in alternative embodiments the core 112492.doc -10· thickness may vary beyond this range. In an alternative embodiment, the core may be a ceramic or organic material. The conductive layers 108 and 110 may be formed of copper, copper alloy or other low resistance electrical conductors&apos; and may be patterned into a conductive pattern and dummy circuitry in accordance with embodiments of the present invention as described below. The thickness of the layers 1 〇 8 and/or 11 。 may be from about 10 μm to about 24 μ', but in alternative embodiments the thickness of the layers 108 and 11 may vary beyond this range. Once patterned, the top and bottom conductive layers can be laminated to a solder mask U2, 114, respectively, which is known in the art. The substrate 100 can be patterned and configured for use in various semiconductor packages. One such package is a so-called Platform Grid Array (LGA) semiconductor package for use with, for example, SD flash memory cards. However, it should be understood that the dummy circuit patterns described below can be applied to any substrate, and a conductive pattern can be formed in the substrate and assembled into a semiconductor device. Referring again to FIG. 2, one or both of the conductive layers 108 and 11 can be etched or otherwise processed to include a conductive pattern 120' between the components mounted on the substrate 100 and as described below. An electrical connection is provided between the components on the substrate 100 and the external device. Some embodiments include a conductive pattern on the top surface 102 and the bottom surface 1〇4 of the substrate 100 and in a substrate including a plurality of top and bottom layers (as described below in connection with FIG. 9), then in particular embodiments Channels (not shown) may be provided to transmit electrical signals between conductance patterns in different layers. Substrate 100 further includes a plurality of regions 122, 124' 126 that do not have a conductance pattern, referred to herein as dummy circuit regions. The dummy circuit pattern 13 〇β may be formed in one or more of the circuit regions 122, 124, 126 in one or more regions of the circuit region 122, 124, 126. It should be understood that the alternative embodiment of the present invention is specific. The size and shape of the substrate 1 and the size and shape of the conductive pattern 102 in the embodiment can vary widely to define one or more dummy circuit regions of any size or shape. The dummy circuit can be provided in any one or any of a plurality of regions of such dummy circuit regions. In a specific embodiment, a dummy circuit pattern may be provided on both sides of the substrate in accordance with any of the embodiments described below, even in the case where a conductive pattern is provided only on one side of the substrate. . It is contemplated that a substrate can be used in a semiconductor device that does not include a conductive pattern on the first or second opposing surface of the substrate. "This substrate can be formed to have a dummy circuit pattern in accordance with one embodiment of the present invention. . In the parent embodiment of the following S, the dummy circuit pattern is composed of lines and/or shapes. The lines and/or shapes are provided in the one or more of the plurality of dummy circuit regions at a given density. Density indicates the number, length, and/or amount of material in a dummy circuit pattern or conductive traces of the conductance pattern for each unit area on the substrate. The level of stress in one of the linear sections of a dummy circuit pattern will be linear or non-linear&apos; which is related to the length of the straight section when the substrate is heated. Generally, the longer the length, the greater the stress due to heating. For the maximum length of the straight section in any portion of the dummy circuit pattern according to one of the specific embodiments below, the length of the straight section can be set such that the stress in the straight section remains below a desired level. quasi. Specific order 112492.doc •12· 1324382, known empirical characteristics and/or known physical characteristics and behavior of the substrate material as a function of the type of material used, the thickness of the material used, and the temperature range over which the materials will experience, To determine the stress per unit length of a straight section of one of the dummy circuits. Other features may also be included in the analysis. The maximum length of one of the linear sections of one of the dummy circuits may be selected such that the stress within the section remains below any desired pre-positioning. In other words, since the stress accumulated per unit length is known, a desired maximum stress can be selected, and thus the length of all or a portion of the straight section in a dummy circuit can be set such that a stress remains at or below The selected stress level. It will be appreciated that there is no need to perform a enthalpy analysis of the stress per unit length, but in the particular embodiment of the invention the maximum length of the juice line segment can alternatively be estimated. It will also be appreciated that a dummy circuit pattern in a particular embodiment of the invention may include straight sections in which stresses exceeding a predetermined maximum may cause the sections to be thermally expanded. For the density of a dummy circuit pattern, other factors that may have an effect on the stress in a substrate are not considered, and the stress in the substrate can be minimized when the density of the dummy pattern is close to the density of the conductive pattern. Thus, in a particular embodiment of the invention, the density of a dummy circuit pattern can be selected to be close to the density of the conductance pattern on the substrate. Alternatively, the density of the dummy circuit pattern can be selected to be greater or less than the density of the conductance pattern such that the stress generated on the substrate remains within a predetermined acceptable level. It should be understood that there is no need to perform a quantitative analysis of the stress due to the difference in density between the dummy circuit pattern and the conductance pattern, and the dummy circuit pattern can be alternatively estimated in the embodiment of the present invention. The density. In the embodiment shown in FIG. 2, the dummy circuit pattern 130 is formed by a plurality of adjacent alignment units 13A having a surname of 108 and/or 11 Å. The shape of each of the adjacent cells can be uniform and fit together so that no gaps are left between the cells. It will be appreciated that in alternative specific embodiments, the individual elements may be adapted so as to leave a space therebetween to etch or otherwise process the pattern 130 without any straight line extending through any two phases. The adjacent unit is 13〇. In the particular embodiment illustrated in FIG. 2, the individual units 130 are hexagonal to form a honeycomb pattern 130. However, it should be understood that other shapes may be used in alternative embodiments, such as adjacent circles, octagons, and other polygons (other than triangles, rectangles, and squares)^ (the adjacent shapes are not aligned with each other so that The triangles, rectangles, and squares can be used without any straight line extending through any two adjacent shapes. The length of the various straight segment traces that form the pattern 13〇 can be controlled as such. The stress generated in the straight section remains below a predetermined desired stress level. However, in a particular embodiment, the length of the straight section forming each unit 130 can range between about 5 〇 and 250 μηη, and more specifically between 70 μηη and 150 μηη. It will be appreciated that in alternative embodiments, the maximum length of the unit 13'' section may have a maximum diameter greater than 25 jaws and less than 50 μηη. In a particular embodiment, the individual traces forming each of the 130' sides may have a width between about 7〇0111 and 15〇', but in each alternative embodiment of the invention, each unit The width can be larger or smaller than this. Each of the dummy circuit regions 122 to 126, H2492.do, 1324382, may include a unit 130 of the same size. Alternatively, as shown in FIG. 2, the cells in one or more of the regions (122, 124) may be larger than the cells 130 in t of the other dummy circuit regions (126). As indicated above, the dummy circuit unit 130 can be omitted from one or more of the dummy circuit regions. Moreover, as will be explained below, individual cells 13A' within a given dummy circuit region can have different sizes. In the particular embodiment of Figure 2, each individual unit 13 is of a uniform shape. In a second alternative embodiment shown in FIG. 4, one or more of the dummy regions 122, 124, and 126 may include a dummy circuit pattern reference 140, and the dummy circuit pattern 14 includes a plurality of Regular random shape unit 140'. As will be explained below, the random shape of the unit 140' can be created in a pattern mask placed on the substrate. One of the controllers for generating the pattern mask may include a soft body for generating a random shape. Alternatively, the configuration of the random shape can be established, and then the information is transmitted to the system that produced the pattern mask. Although Figure 4 shows polygons of random shapes, straight edges, in one alternative embodiment of the invention one or more of the units may have rounded edges. In a specific embodiment, each of the random shape units 140 may be positioned at a random location within a given circuit area. Alternatively, the per-virtual circuit region can be subdivided into sub-regions of the meaning, and the cell distribution across the sub-regions is controlled, but a unit 14 〇| is determined in a given sub-region. Alternatively, the location of each of the randomly shaped cells may be predetermined within a dummy circuit region. As in the specific embodiment of FIG. 2, in general, any two adjacent units 140' will not have a continuous line extending therethrough. Although in this U2492.doc 15· the specific embodiment, the edges of the two random β _ I I-shaped early 将 will be aligned, but any two random shapes of adjacent single 亓 1 ancient (four) early 疋 have aligned sides so that In the meantime, the probability h is in the present invention. In the specific embodiment, the average length of any side of the _ random form 7L 140 can be between 咖3 coffee and i _. However, it should be understood that, in the alternative embodiment of the present invention, the average size of any of the sides may be greater or less than the range of alternative embodiments of the present invention. The standard deviation from this average size can vary. In a particular embodiment, the line 140 may have a thickness of about 5 tons, although in a particular embodiment of the invention the thickness may vary. The average size of the random shape cells 140 may be the same or different at different dummy circuit regions 122 to 126. Also, the dummy circuit pattern 14A can be omitted from one or more of the dummy circuit regions. The density of the dummy circuit pattern 140 can be controlled to be generally equal to, smaller than, or greater than the density of the conductance pattern 120 as described above. In the particular embodiment illustrated in Figure 4, all or most of the elements 14 are closed hexagons. In a third embodiment illustrated in FIG. 5, a wafer carrier substrate 100 can include a conductive pattern 12A and one or more dummy circuit regions 122-126, each region including a randomly oriented line 15A, One of the dummy circuit patterns 150 is composed. Line 150' can be straight or curved. In the case of a straight line, the length of each line 150' may be selected to be less than a predetermined length. Or the average length of 'all lines 150' may be selected to be below a predetermined value. Similarly, the line density within the dummy circuit pattern 150 can be close to the density of the conductance pattern or can be greater or less than the conductance pattern as described above. 112492.doc • 16-1324382

之密度。在具體實施例中，該等線1 50,之厚声可认A τ欠』巧為5〇 μπι，但在本發明之具體實施例中此厚度可以改變。The density. In a particular embodiment, the thick line of the line 150 is arbitrarily 5 〇 μπι, although in a particular embodiment of the invention the thickness may vary.

在所示具體實施例中，該等線150,係隨機定向、隨機調 節尺寸（在一給定範圍内）並隨機定位。應瞭解，在替代性 具體實施例中該等線150’之定向、長度及位置中的—咬夕 者受控制成非隨機。因此，例如，定向及位置可以係^ 機，但圖案150内線的長度可受控制。或者，圖案15〇中線 的方向及位置可以係隨機，但該位置係部分或完全受栌 制。同樣，線150,之長度及位置可以係隨機，而其定 控制。對於每一虛設電路區域，線150,之上述特性中每: 特性皆相同’或者上述特性可因^ 丄k竹氐』囚不冋虛设電路區域而改 圖6顯示本發明之另-具體實施例，其包括具有一電 圖案120與虛設電路區域122至126之〜基板_。在至此 說明的具體實施例中，圖中顯示為虛設電路圖案之線及|In the particular embodiment shown, the lines 150 are randomly oriented, randomly adjusted in size (within a given range) and randomly positioned. It will be appreciated that in alternative embodiments the orientation, length and position of the lines 150&apos; are controlled to be non-random. Thus, for example, the orientation and position can be controlled, but the length of the line within the pattern 150 can be controlled. Alternatively, the direction and position of the center line of the pattern 15 may be random, but the position is partially or completely controlled. Similarly, the length and position of line 150 can be random and controlled. For each dummy circuit region, line 150, each of the above characteristics: the characteristics are the same 'or the above characteristics may be changed due to the 冋k bamboo 氐 囚 冋 冋 冋 冋 冋 冋 改 改 改 改 改 改 改 改 改 改 改 改 改For example, it includes a substrate _ having an electrical pattern 120 and dummy circuit regions 122 to 126. In the specific embodiment described so far, the figure shows the line of the dummy circuit pattern and |

狀表示在將該圖案蝕刻或以其他方式形成於 在該基板上的跡線材料。相比而令後 叩。在圖ό之具體實施〈 二。Λ 路區域之每—區域皆包括-虛設電㈣ 160 ’其中該圖中的白始矣 &quot;'、在製程期間蝕刻掉的材料 而黑色背景表示央白μ 3 〇 (其係在形成該虛設電ϋ 圖案後留下的層）之好粗 ^ 為圖5所干卜Φ , ® 6中的虛設電路圖案160可; 圃所不虛設電路圖案150之备圄安&quot; 代性具體實施例中，負圖案。在本發明之， 說明的圖7及8所-/ 圖案可包含圖2至4及下^ 所不之虛設電路圖案之負圖案。 H2492.doc 17 1324382 虚設電路圖案160包括蝕刻線160'。蝕刻線160·可具有來 自圖5中虛設電路圖案150的線150’之任何特性。在圖6之具 體實施例中，該等線160’之長度及密度較佳的係選擇成減 低製造後層108或110中的材料數量以讓虛設電路圖案16〇 及基板100内的應力位準一般保持為如上所述之預定的可 接受位準。 圖7顯示本發明之另一具體實施例，其包括具有一電導 圖案120與虛設電路區域122至i26之一基板1〇〇。該等虛設 電路區域中的一或多個區域可包括由複數個形狀17〇，組成 之一虛設電路圖案170。在圖7所示具體實施例中，形狀 170中的每一形狀接近字母&quot;c”之輪廓，並且在該製程期間 蝕刻掉來自該輪廓内的材料。此外，應瞭解，在本發明之 替代性具體實施例中，提供各種其他輪靡形狀。該等形狀 或可以係，，填合&quot;形狀。#，在該钱刻程序後可保留來自該 形狀的外部輪廓内之材料。The shape indicates the trace material that is etched or otherwise formed on the substrate. Compared with the latter. The specific implementation in Figure 〈. Each area of the Λ road area includes - dummy electricity (four) 160 'where the white 矣 矣 ' in the figure, the material etched away during the process and the black background indicates the central white μ 3 〇 (the system is forming the dummy The layer left after the pattern of the eMule is as good as the thickness of the pattern Φ, and the dummy circuit pattern 160 in the ? 6 can be used in the embodiment of the present invention. , negative pattern. In the present invention, the illustrated patterns of FIGS. 7 and 8 may include the negative patterns of the dummy circuit patterns of FIGS. 2 to 4 and the lower portions. H2492.doc 17 1324382 The dummy circuit pattern 160 includes an etch line 160'. Etch line 160 can have any of the characteristics of line 150' from dummy circuit pattern 150 in FIG. In the embodiment of FIG. 6, the length and density of the lines 160' are preferably selected to reduce the amount of material in the post-manufacture layer 108 or 110 to allow the dummy circuit pattern 16 and the stress level in the substrate 100. It is generally maintained at a predetermined acceptable level as described above. Figure 7 shows another embodiment of the present invention comprising a substrate 1 having a conductance pattern 120 and dummy circuit regions 122 to i26. One or more of the dummy circuit regions may include a dummy circuit pattern 170 composed of a plurality of shapes 17A. In the particular embodiment illustrated in Figure 7, each shape in shape 170 approximates the outline of the letter &quot;c&quot; and the material from within the profile is etched away during the process. Further, it should be understood that instead of the present invention In various embodiments, various other rim shapes are provided. The shapes may or may be filled with a shape that retains material from the outer contour of the shape after the process.

在圖不具體實施例中，形成形狀⑽之區段大部分係彎 彎曲形狀之一優點係該形狀内的應力係最小化。此 ^半導體晶粒及其他㈣對該基板上沿該晶粒與該（等） ::之轴而對齊的圖案更加敏感。彎曲的形狀減低應力， 板上^應力可導致—半導體晶粒或其他組件安裝於該基 板上的該形狀之上。 體實施例中，可c解，在本發明之替代性具 170,。 9由所有或部分直線來界定該等形狀 如圖7所示 該等形狀170,中 的每一形狀係與該等形狀 H2492.doc 1324382 170’中的每一其他形狀間隔。應瞭解，在本發明之替代性 具體實施例中’該等形狀可重疊。此外，肖等形狀中的每 一形狀可處於相同定向（如同在虛設電路區域122及124 中）或者該荨形狀170'之定向可不同（如同在虛設電路區 域126中）。該等形狀17〇，中每一形狀在一給定的虛設電路 區域内之尺寸可能彼此相同或不同，而該等形狀1 70'從一 虛設區域至下一虛設區域的尺寸可能相同或不同（如圖7所 示）。在每一虛設電路區域中該等形狀17〇，之數目、尺寸及/ 或位置可受到控制，或可以係隨機。 圖8說明本發明之另一具體實施例，其包括一具有一電 導圖案120與一或多個虛設電路區域122至126之基板1〇〇。 該等虛設電路區域122至126中的一或多個區域可包括由複 數個單元180’形成之一電導圖案18〇β圖8類似於上述圖2之 具體實施例’而不同之處在於形成虛設電路圖案18〇之單 元180中的母一單元之尺寸或形狀可能並非與每一其他單 兀180’相同。在圖8所示具體實施例中，複數個較大的六邊 形單元180’係藉由複數個較小的六邊形單元18〇，而接合。 该等單元180:可具有上面相對於圖2之單元13〇，而說明之特 性。 如上所示，在本發明之具體實施例中，可在基板1〇〇中 核心106的個別上部與下部表面上提供複數個層ι〇8及 110。圖9以斷面顯示此一具體實施例。在所示具體實施例 中’核心包括三層108’每一層係藉由頂部表面1〇2上之一 層焊料遮罩112而層壓’而基板1〇〇包括三層丨1〇，每一層 U2492.doc •19· 1324382 除該光阻。接下來，在步驟16〇中使用一蝕刻劑（例如氣化 鐵）來姓刻掉該等曝光區域，以定義該核心上的電導及虛 设電路圖案。接下來，在步驟162中移除該光阻，而在步 驟164中施塗該焊料遮罩層。 參考圖12之流程圖來說明一用以形成所完成的晶粒封裝 182之整個程序。該基板100最初係作為一大面板而出現， 該大面板在製造後係分成個別的基板。在一步驟22〇中， 將該面板鑽孔以提供參考孔來定義個別基板之位置。然 後，在步驟222中，在該面板之個別表面上形成該電導圖 案及虛設電路圖案，如上面之說明。然後，在步称224中 檢查及測试該圖案化的面板。一旦經過檢查，便在步驟 220中將該焊料遮罩施塗於該面板。然後，在步驟228中， 起槽機將該面板分成個別基板。然後，在一自動化步驟 (步驟230)中以及在一最終視覺檢查（步驟232)中再次檢查 並測試個別基板，以檢查電性操作，並檢查污染、刮擦及 變色。然後在步驟234中透過晶粒附著程序而傳送通過檢 查的基板，並接著在步驟236中在一已知的注模程序中封 裝該基板及晶粒以形成一 JEDEC標準（或其他）封裝。應瞭 解，在替代性具體實施例中，可藉由其他程序來形成包括 一虛設電路圖案之晶粒封裝1 82。 前述關於本發明的詳細說明係基於圖解及說明之目的而 &amp;出並不希望包攬無遺或將本發明限於所揭示的具體 形式。根據以下教導内容，可有許多修改及變更。選擇上 述具體實施例，以便更好地說明本發明之原理及其實際應 112492.doc •22· 1324382 用’從而使得熟習此項技術者能在各項具體實施例中結合 適合預期特定用途之各種修改來更好地運用本發明。希望 藉由隨附申請專利範圍來定義本發明之範疇。 【圖式簡單說明】 圖1係包括一交又陰影虛設電路圖案之一先前技術基板 之&quot;&quot;&quot;俯視圖。 圖2係在該電導圖案未佔據之區域中包括依據本發明之 具體實施例之一電導圖案與一虛設電路圖案之一基板之一 俯視圖。 圖3係圖2所不基板之一斷面圖。 圖4係包括依據本發明之一替代性具體實施例之一電導 圖案與一虛設電路圖案之一基板之一俯視圖。 圖5係包括依據本發明之一第二替代性具體實施例之一 電導圖案與一虛設電路圖案之一基板之一俯視圖。 圖6係包括依據本發明之一第三替代性具體實施例之一 電導圖案與一虛設電路圖案之一基板之一俯視圖。 圖7係包括依據本發明之一第四替代性具體實施例之一 電導圖案與一虛設電路圖案之一基板之一俯視圖。 圖8係包括依據本發明之一第五替代性具體實施例之一 電導圖案與一虛設電路圖案之一基板之一俯視圖。 圖9係包括複數個導電層之一基板之一側視斷面圖，其 中一或多層可包括上述任何具體實施例中所示之一虛設電 路圖案。 圖10係包括一基板之一半導體封裝之一斷面側視圖，該 112492.doc •23- 1324382 基板具有依據本發明之一具體實施例之一虛設電路圖案。 圖11係說明用以在一基板上製造該電導圖案及虛設電路 圖案程序之一流程圖。 圖12係用以製造一半導體封裝之一程序之一整體流程 圖，該半導體封裝包括依據本發明之具體實施例之一虛設 電路圖案。 【主要元件符號說明】In the non-specific embodiment, one of the advantages of forming a portion of the shape (10) that is mostly curved and curved is that the stress within the shape is minimized. The semiconductor die and the other (4) are more sensitive to patterns on the substrate that are aligned along the die and the axis of the ::. The curved shape reduces stress and the stress on the board can cause the semiconductor die or other component to be mounted over the shape of the substrate. In an embodiment, an alternative is provided in the present invention 170. 9 is defined by all or a portion of the line. Each of the shapes 170 is shown in Fig. 7 as being spaced from each of the other shapes in the shape H2492.doc 1324382 170'. It will be appreciated that in alternative embodiments of the invention, the shapes may overlap. Moreover, each of the shapes of the shawl or the like may be in the same orientation (as in the dummy circuit regions 122 and 124) or the orientation of the 荨 shape 170' may be different (as in the dummy circuit region 126). The shapes of each of the shapes 17 〇 may be the same or different from each other in a given dummy circuit region, and the sizes of the shapes 1 70 ′ from one dummy region to the next dummy region may be the same or different ( As shown in Figure 7). The number, size and/or position of the shapes 17 〇 in each dummy circuit region may be controlled or may be random. Figure 8 illustrates another embodiment of the present invention including a substrate 1 having a conductive pattern 120 and one or more dummy circuit regions 122-126. One or more of the dummy circuit regions 122 to 126 may include a conductive pattern 18 〇β formed by a plurality of cells 180 ′. FIG. 8 is similar to the specific embodiment of FIG. 2 described above except that a dummy is formed. The size or shape of the parent cell in unit 180 of circuit pattern 18 may not be the same as every other cell 180'. In the particular embodiment illustrated in Figure 8, a plurality of larger hexagonal cells 180' are joined by a plurality of smaller hexagonal cells 18'. The unit 180: may have the characteristics described above with respect to the unit 13A of Fig. 2. As indicated above, in a particular embodiment of the invention, a plurality of layers ι 8 and 110 may be provided on the individual upper and lower surfaces of the core 106 in the substrate 1 . Figure 9 shows this embodiment in cross section. In the illustrated embodiment, the 'core includes three layers 108' each layer is laminated by a layer of solder mask 112 on the top surface 1 〇 2 and the substrate 1 〇〇 includes three layers 〇 1 〇, each layer U2492 .doc •19· 1324382 In addition to the photoresist. Next, an etchant (e.g., gas iron) is used in step 16 to erase the exposed regions to define the conductance and dummy circuit patterns on the core. Next, the photoresist is removed in step 162 and the solder mask layer is applied in step 164. The overall procedure for forming the completed die package 182 is illustrated with reference to the flow chart of FIG. The substrate 100 initially appears as a large panel that is divided into individual substrates after fabrication. In a step 22, the panel is drilled to provide a reference hole to define the location of the individual substrates. Then, in step 222, the conductance pattern and the dummy circuit pattern are formed on individual surfaces of the panel, as explained above. The patterned panel is then inspected and tested in step 224. Once inspected, the solder mask is applied to the panel in step 220. Then, in step 228, the grooving machine divides the panel into individual substrates. The individual substrates are then inspected and tested again in an automated step (step 230) and in a final visual inspection (step 232) to check for electrical operation and to check for contamination, scratches and discoloration. The substrate being inspected is then transferred through the die attach process in step 234, and then the substrate and die are packaged in a known injection molding process in step 236 to form a JEDEC standard (or other) package. It should be understood that in an alternative embodiment, a die package 182 comprising a dummy circuit pattern can be formed by other processes. The foregoing detailed description of the present invention is intended to Many modifications and variations are possible in light of the following teachings. The specific embodiments described above are chosen to better illustrate the principles of the invention and the actual application of the application of the present invention to the specific embodiments. Modifications to better utilize the invention. It is intended that the scope of the invention be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a &quot;&quot;&quot; top view of a prior art substrate including one of a cross-hatched dummy circuit pattern. 2 is a top plan view of one of the substrates including a conductive pattern and a dummy circuit pattern in accordance with an embodiment of the present invention in an area where the conductive pattern is not occupied. Figure 3 is a cross-sectional view of a substrate not shown in Figure 2. 4 is a top plan view of a substrate including a conductive pattern and a dummy circuit pattern in accordance with an alternative embodiment of the present invention. Figure 5 is a top plan view of a substrate including a conductive pattern and a dummy circuit pattern in accordance with a second alternative embodiment of the present invention. Figure 6 is a top plan view of a substrate including a conductive pattern and a dummy circuit pattern in accordance with a third alternative embodiment of the present invention. Figure 7 is a top plan view of a substrate including a conductive pattern and a dummy circuit pattern in accordance with a fourth alternative embodiment of the present invention. Figure 8 is a top plan view of a substrate including a conductive pattern and a dummy circuit pattern in accordance with a fifth alternative embodiment of the present invention. Figure 9 is a side cross-sectional view of one of a plurality of substrates including a plurality of conductive layers, one or more of which may include one of the dummy circuit patterns shown in any of the above embodiments. Figure 10 is a cross-sectional side view of a semiconductor package including a substrate having a dummy circuit pattern in accordance with one embodiment of the present invention. Figure 11 is a flow chart showing a procedure for fabricating the conductance pattern and dummy circuit pattern on a substrate. Figure 12 is an overall flow diagram of one of the procedures for fabricating a semiconductor package including a dummy circuit pattern in accordance with a particular embodiment of the present invention. [Main component symbol description]

20 基板 22 電導圖案 24 虛設圖案 26, 28, 30 區域 100 晶片載體基板 102 頂部表面 104 底部表面 106 核心 108 頂部導電層 110 底部導電層 112, 114 焊料遮罩 120 電導圖案 122, 124, 126 虛設電路區域 130 虛設電路圖案 130' 相鄰單元 140 虛設電路圖案 140' 隨機形狀單元 112492.doc • 24-20 substrate 22 conductance pattern 24 dummy pattern 26, 28, 30 region 100 wafer carrier substrate 102 top surface 104 bottom surface 106 core 108 top conductive layer 110 bottom conductive layer 112, 114 solder mask 120 conductance pattern 122, 124, 126 dummy circuit Area 130 dummy circuit pattern 130' adjacent unit 140 dummy circuit pattern 140' random shape unit 112492.doc • 24-

Claims (1)

1324382 ---------— 日修(更)正替換買 *....... ......... 第095123541號專利申請案 中文申請專利範圍替換本(98年11月） 十、申請專利範圍： -種減低用於-半導體封裝之—基板上㈣之—虛設電 路圖案之至少-部分内的應力之方法，該方法包含以下 步驟： (a)確認該虛設電路圖案之一直線區段之應力產生； 形成該虛設電路圖案，在該虛設電路圖案中之每一直 線區段之該長度受限於一長度，該長度係根據步驟⑷ 確認該虛設電路圖案之-直線區段之應力產生並經確認 不會造成超過一臨界值之一應力。 2_如請求項丨之減低用於一半導體封裝之一基板上形成之 一虛設電路圖案之至少一部分内的應力之方法其中直 線區段之經該步驟（a)所確認的該長度内的該應力係藉由 實驗來決定。 3. 如請求項1之減低用於一半導體封裝之一基板上形成之 一虛設電路圖案之至少一部分内的應力之方法，其中直 線區段之經該步驟（a)所確認的該長度内的該應力係藉由 估計來決定。 4. 如請求項丨之減低用於一半導體封裝之一基板上形成之 一虛設電路圖案之至少一部分内的應力之方法，其進一 步包含將該虛設電路圖案之—部分連接至接地電位或電 源電位中的一者之步驟。 5. 如請求項丨之減低用於一半導體封裝之一基板上形成之 一虛設電路圖案之至少一部分内的應力之方法，其進一 步包含將該虛設電路圖案之—部分連接至一半導體晶粒 112492-981120.doc ==電性組件中的至少一者以向該半導體晶粒 從；二板：：電性組件中的至少一者载送電氣信號及/或 等—者中的至少一者載送電氣信號之步驟。 6.如請求们之減低用於一半導體封裝之_基板上形成之 -虛設電路圖案之至少一部分内的應力之方法，&quot;在 該虛設電路圖案中-虛設區域内的每—直線區段之長度 相同。 .一種虛設電路圖案，形成於用於—半導體封裝之一基板 之一表面上，該虛設電路圖案包含： 一直線區段，其包含： 一寬度；以及 —長度，其根據一經確認以維持應力 段中且低於—已知應力位準。 8.如明求項7之虛設電路圖案，其中該已知應力位準係估 計的。 9. 如請求項7之虛設電路圖案，其中該直線形成依據有等 邊長的多邊形之一部分。 10. 如請求項7之虛設電路圖案，其中該直線區段具有在該 虛5又電路圖案中之一隨機方向、在該虛設電路圖案中之 隨機長度及在該虛設電路圖案中之一隨機位置中之至 少一者。 11. 如請求項7之虛設電路圖案，其另包含複數個附加線區 &amp; ’ 5亥直線區段及該複數個附加線區段具有一密度，該 密度近似於也形成於該基板之該表面上之一傳導圖案的 密度。 112492-981120.doc1324382 ---------- Japanese repair (more) is replacing the purchase *....... ......... Patent application No. 095123541 Replacement of the Chinese patent application scope (98 November, the application scope of the patent: - a method for reducing the stress in at least part of the dummy circuit pattern on the substrate (semiconductor package), the method comprising the following steps: (a) confirming the dummy Forming the dummy circuit pattern, the length of each of the straight line segments in the dummy circuit pattern is limited by a length, and determining the length of the dummy circuit pattern according to step (4) The stress of the segment is generated and confirmed to not cause stress exceeding one of the critical values. 2_ a method for reducing stress in at least a portion of a dummy circuit pattern formed on a substrate of a semiconductor package, wherein the line segment is within the length identified by the step (a) Stress is determined by experimentation. 3. The method of claim 1, wherein the method for forming a stress in at least a portion of a dummy circuit pattern on a substrate of a semiconductor package, wherein the straight line segment is within the length confirmed by the step (a) This stress is determined by estimation. 4. The method of reducing a stress in at least a portion of a dummy circuit pattern formed on a substrate of a semiconductor package, wherein the method further comprises: connecting the portion of the dummy circuit pattern to a ground potential or a power supply potential One of the steps. 5. The method of reducing a stress in at least a portion of a dummy circuit pattern formed on a substrate of a semiconductor package, wherein the method further comprises: connecting the portion of the dummy circuit pattern to a semiconductor die 112492 -981120.doc == at least one of the electrical components carrying at least one of the semiconductor die from: the second board:: electrical component carrying an electrical signal and/or the like The step of sending an electrical signal. 6. A method of reducing stress in at least a portion of a dummy circuit pattern formed on a substrate of a semiconductor package, as claimed by the requester, &quot; in the dummy circuit pattern - each line segment in the dummy region The length is the same. A dummy circuit pattern formed on a surface of a substrate for a semiconductor package, the dummy circuit pattern comprising: a linear segment comprising: a width; and a length, which is confirmed to maintain the stress segment And below - known stress level. 8. The dummy circuit pattern of claim 7, wherein the known stress level is estimated. 9. The dummy circuit pattern of claim 7, wherein the straight line forms part of a polygon having an equilateral length. 10. The dummy circuit pattern of claim 7, wherein the straight line segment has a random direction in the dummy circuit pattern, a random length in the dummy circuit pattern, and a random position in the dummy circuit pattern At least one of them. 11. The dummy circuit pattern of claim 7, further comprising a plurality of additional line regions &amp; '5 Hai straight segments and the plurality of additional line segments having a density similar to that also formed on the substrate The density of one of the conductive patterns on the surface. 112492-981120.doc
TW095123541A 2005-06-30 2006-06-29 Apparatus having reduced warpage in an over-molded ic package and method of reducing warpage in an over-molded ic package TWI324382B (en)

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