TW200721417A - Apparatus having reduced warpage in an over-molded ic package and method of reducing warpage in an over-molded ic package - Google Patents
Apparatus having reduced warpage in an over-molded ic package and method of reducing warpage in an over-molded ic packageInfo
- Publication number
- TW200721417A TW200721417A TW095123541A TW95123541A TW200721417A TW 200721417 A TW200721417 A TW 200721417A TW 095123541 A TW095123541 A TW 095123541A TW 95123541 A TW95123541 A TW 95123541A TW 200721417 A TW200721417 A TW 200721417A
- Authority
- TW
- Taiwan
- Prior art keywords
- package
- molded
- over
- warpage
- circuit pattern
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09681—Mesh conductors, e.g. as a ground plane
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Abstract
A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern includmg straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also he formed with an orientation, size and position that are randomly selected.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/171,095 US20070004094A1 (en) | 2005-06-30 | 2005-06-30 | Method of reducing warpage in an over-molded IC package |
US11/170,883 US20070001285A1 (en) | 2005-06-30 | 2005-06-30 | Apparatus having reduced warpage in an over-molded IC package |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200721417A true TW200721417A (en) | 2007-06-01 |
TWI324382B TWI324382B (en) | 2010-05-01 |
Family
ID=37432379
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095123541A TWI324382B (en) | 2005-06-30 | 2006-06-29 | Apparatus having reduced warpage in an over-molded ic package and method of reducing warpage in an over-molded ic package |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1905080A1 (en) |
JP (1) | JP2009500830A (en) |
KR (1) | KR101015265B1 (en) |
TW (1) | TWI324382B (en) |
WO (1) | WO2007005492A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100263914A1 (en) * | 2009-04-16 | 2010-10-21 | Qualcomm Incorporated | Floating Metal Elements in a Package Substrate |
US20100270061A1 (en) * | 2009-04-22 | 2010-10-28 | Qualcomm Incorporated | Floating Metal Elements in a Package Substrate |
KR101472660B1 (en) * | 2013-02-22 | 2014-12-12 | 삼성전기주식회사 | Substrate strip |
US20230076844A1 (en) * | 2021-09-09 | 2023-03-09 | Qualcomm Incorporated | Semiconductor die module packages with void-defined sections in a metal structure(s) in a package substrate to reduce die-substrate mechanical stress, and related methods |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0439991A (en) * | 1990-06-05 | 1992-02-10 | Sony Corp | Multilayer printed board |
KR100273499B1 (en) * | 1995-05-22 | 2001-01-15 | 우찌가사끼 이사오 | Semiconductor device having a semiconductor chip electrically connected to a wiring substrate |
JP2003168848A (en) | 2001-11-30 | 2003-06-13 | Nec Kansai Ltd | Wiring board |
US6784531B2 (en) * | 2002-06-13 | 2004-08-31 | Hewlett-Packard Development Company, L.P. | Power distribution plane layout for VLSI packages |
TWI229574B (en) * | 2002-11-05 | 2005-03-11 | Siliconware Precision Industries Co Ltd | Warpage-preventing circuit board and method for fabricating the same |
-
2006
- 2006-06-28 JP JP2008519547A patent/JP2009500830A/en active Pending
- 2006-06-28 EP EP06785812A patent/EP1905080A1/en not_active Withdrawn
- 2006-06-28 WO PCT/US2006/025303 patent/WO2007005492A1/en active Application Filing
- 2006-06-28 KR KR1020077030881A patent/KR101015265B1/en not_active IP Right Cessation
- 2006-06-29 TW TW095123541A patent/TWI324382B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1905080A1 (en) | 2008-04-02 |
JP2009500830A (en) | 2009-01-08 |
KR101015265B1 (en) | 2011-02-18 |
WO2007005492A1 (en) | 2007-01-11 |
TWI324382B (en) | 2010-05-01 |
KR20080024492A (en) | 2008-03-18 |
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Legal Events
Date | Code | Title | Description |
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MM4A | Annulment or lapse of patent due to non-payment of fees |