KR101015265B1 - Method of reducing warpage in an over-molded ic package - Google Patents

Abstract

Dummy circuit patterns are formed on the surface of a substrate for a semiconductor package. The length of this dummy circuit pattern is controlled such that no stress is generated above the desired stress in the straight segments. The dummy circuit pattern is formed of a plurality of lines or formed of adjacent or spaced polygons (eg, hexagonal). In addition, a portion of the dummy circuit pattern may be formed having an arbitrarily selected orientation, size, and position.

Semiconductor package, dummy circuit pattern, stress, polygon, stress control

Description

METHOOD OF REDUCING WARPAGE IN AN OVER-MOLDED IC PACKAGE

Related application

This application is filed by Hem Takiar et al., And is entitled US Patent Application entitled "APPARATUS HAVING REDUCED WARPAGE IN AN OVER-MOLDED IN PACKAGE." In connection with this, it is filed concurrently with this application and is hereby incorporated by reference in its entirety.

This application is also filed by Cheeman Yu et al. And filed under US patent application entitled " SUBSTRATE WARPAGE CONTROL AND CONTINUOUS ELECTRICAL ENHANCEMENT. &Quot; In connection with this, it is filed concurrently with this application and is hereby incorporated by reference in its entirety.

Embodiments of the present invention relate to a method of forming a chip carrier substrate for preventing warpage and a chip carrier formed thereby.

As the demand for portable consumer electronic devices increases greatly, a large amount of storage devices are required. Nonvolatile semiconductor memory devices, such as flash memory storage cards, are widely used to meet the ever-increasing demands on digital information storage and exchange. In addition to the high reliability and large capacity of nonvolatile semiconductor memory devices, as well as their portability, versatility and robust design, these memory devices are, for example, digital cameras, digital music players, video game consoles. It is ideal for use in a variety of electronic devices such as, PDAs, and cellular telephones.

One exemplary standard for flash memory cards is the so-called SD (Secure Digital) flash memory card. In the past, electronic devices such as SD cards used several individually packaged ICs, each of which was logic circuits for information processing, memory for storing information, and I / O circuitry for exchanging information with the outside world. And integrated circuit ("IC") systems consisting of < RTI ID = 0.0 > a < / RTI > Individually packaged ICs are individually mounted to a substrate, such as a printed circuit board, to form an IC system. More recently, system packages (system-in-a-package, "SiP") and multichip modules ("MCM") have been developed, where multiple integrated circuit components are packaged together to form a complete electronic system in a single package. to provide. Typically, an MCM includes a plurality of chips, which are mounted side by side over a substrate and then packaged. SiP typically includes a plurality of chips, some or all of which are stacked on a substrate and then packaged.

Generally, the substrate on which the die and passive components can be mounted includes a rigid or soft dielectric base with a conductive layer etched on one or both sides. An electrical connection is made between the die and the at least one conductive layer (s), the conductive layer (s) providing an electrical lead structure for integrating the die into the electronic system. Once the electrical connection is made between the die and the substrate, the assembly is wrapped in a molding compound to provide a protective package.

1 shows one surface of a conventional substrate 20 including an etched conductive layer. Substrate 20 includes conductance pattern 22 for transmitting electrical signals between various components mounted on the substrate and between such substrate components and the external environment. This conductance pattern has any number of configurations and occupies a large amount of space on the substrate. Conventionally, when the conductive layer on the surface of the substrate is completely etched away from regions that do not form part of the conductance pattern, regions with different thermal expansion characteristics are caused, and heating the substrate during fabrication of the IC package It was recognized that mechanical stress builds up on the substrate. The metal of the conductance pattern tends to expand upon heating, with some regions having a metal and some regions having no metal, causing stress in the substrate. The same phenomenon was observed even when regions of the conductive layer which did not form part of the conductive layer were left completely intact. This stress tends to warp the substrate. The curved substrate can cause cracks and mechanical stress in the semiconductor die when or after the semiconductor die is bonded to the substrate.

Thus, it is known to etch a so-called dummy pattern on semiconductor substrates in regions that are not used as conductance patterns. For example, US Pat. No. 6,380,633 to Tsai, entitled " Pattern Layout Structure in Substrate, " The formation of a dummy pattern (e.g., a dummy pattern 24 shown in FIG. 1) is described. Dummy pattern 24 provides improved semiconductor yield by reducing different thermal characteristics between regions on a substrate having a conductance pattern and regions on a substrate having no conductance pattern.

The inventors have also found that thermal stress is still caused when the dummy pattern 24 is laid in a long straight line. In particular, it was found that this thermal stress is concentrated on the straight segments of the dummy pattern trace and increases with the length of the straight segments. US Pat. No. 6,864,434 to Chang et al., Entitled “Warpage-Preventive Circuit Board And Method For Fabricating The Same,” discloses a dummy pattern of cross hatches proposed in Tsai's patent, while Chang et al. Disassemble into Although Chang et al suggest improvements over Tsai, Chang et al still initiate a system of straight segments on the substrate, causing stress on the substrate. As semiconductor dies become thinner and more delicate, minimizing stress in the substrate becomes more important.

Generally, embodiments of the present invention relate to a method of forming a chip carrier substrate for preventing warpage and a chip carrier formed thereby. The substrate includes a conductance pattern for transmitting electrical signals between the die and components on the substrate, and a dummy circuit pattern for preventing warpage of the substrate in areas not occupied by such conductance pattern.

The dummy circuit pattern has straight segments, which are length controlled so as not to generate stresses in the straight segments above the desired stress. The desired length of the straight segment is determined experimentally by determining the stress in the straight segment as a function of length and then setting the length to less than the desired maximum stress in the given straight segment. Alternatively, the desired length of the line segment is estimated based on known properties of the materials used in the substrate.

The dummy circuit pattern is formed in a plurality of lines, shapes and sizes. In one embodiment, the dummy circuit pattern is formed of a plurality of polygons, for example hexagons. The polygons may be continuous with one another or may be spaced apart from one another. In addition, each of the polygons may have the same size as each other, or the dummy circuit pattern may include polygons of different sizes.

In an alternative embodiment, the dummy circuit pattern may be formed of polygons of any shapes formed on the substrate. These arbitrary shapes can also be optionally oriented and / or positioned arbitrarily on the substrate. In alternative embodiments, these arbitrary shapes may be continuous with one another or spaced apart from one another.

As an alternative to any shapes, the dummy circuit pattern can be formed from any lines on the substrate. In alternative embodiments, these lines may have any orientation, any length and / or any location over the dummy circuit pattern.

The dummy circuit pattern is formed on the photomask together with the conductance pattern and then etched into conductive layers on the top and / or bottom of the substrate by conventional etching processes.

1 is a plan view of a conventional substrate including a dummy circuit pattern of a cross hatch.

2 is a plan view of a substrate including a conductance pattern in accordance with embodiments of the present invention and a dummy circuit pattern in regions not occupied by such conductance pattern.

3 is a cross-sectional view of the substrate shown in FIG. 2.

4 is a plan view of a substrate including a conductance pattern and a dummy circuit pattern according to an alternative embodiment of the present invention.

5 is a plan view of a substrate including a conductance pattern and a dummy circuit pattern according to a second alternative embodiment of the present invention.

6 is a plan view of a substrate including a conductance pattern and a dummy circuit pattern according to a third alternative embodiment of the present invention.

7 is a plan view of a substrate including a conductance pattern and a dummy circuit pattern according to a fourth alternative embodiment of the present invention.

8 is a plan view of a substrate including a conductance pattern and a dummy circuit pattern according to an alternative embodiment of FIG. 5 of the present invention.

9 is a cross-sectional view of a substrate including a plurality of conductive layers, one or more of which include dummy circuit patterns shown in any of the embodiments described above.

10 is a cross-sectional view of a semiconductor package including a substrate having a dummy circuit pattern according to an embodiment of the present invention.

11 is a flowchart illustrating a process for fabricating a conductance pattern and a dummy circuit pattern on a substrate.

12 is an overall flowchart of a process for manufacturing a semiconductor package including a dummy circuit pattern according to an embodiment of the present invention.

Embodiments of the present invention will now be described with reference to FIGS. 2 to 12. Embodiments of the present invention relate to a method of forming a semiconductor package with reduced warpage and a semiconductor package formed thereby. The invention may be embodied in many other forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments that fall within the spirit and scope of the invention as defined by the appended claims. In addition, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details.

2 is a plan view of the chip carrier substrate 100, and FIG. 3 is a cross-sectional view viewed through a plane perpendicular to the top and bottom surfaces of the substrate 100. As shown in FIG. 3, the substrate 100 has an upper surface 102 and a lower surface 104. The substrate 100 may be formed of an electrically insulating core 106, and an upper conductive layer 108 is formed on an upper surface of the electrically insulating core 106, and a lower conductive layer 110 is formed on a lower surface thereof. The core may be formed of various dielectric materials such as, for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like. Although not critical to the invention, the core 106 may have a thickness of 40 μm to 200 μm, and in alternative embodiments the thickness of the core may deviate outside this range. In alternative embodiments, the core may be ceramic or organic.

Conductive layers 108 and 110 may be formed of copper, copper alloy or other low resistance electrical conductors, and may be patterned in conductance patterns and dummy circuit patterns in accordance with embodiments of the present invention described below. Layers 108 and / or 110 may have a thickness of about 10 μm to 24 μm, but in other embodiments the thickness of layers 108 and 110 may deviate outside this range. Once patterned, as is known in the art, the top and bottom conductive layers are covered by solder masks 112 and 114, respectively.

Substrate 100 may be patterned and configured for use in various semiconductor packages. One such package is, for example, a so-called land grid array (LGA) semiconductor package used in SD flash memory cards. However, the dummy circuit pattern described below may be used on any substrate that has a conductance pattern formed and then assembled into a semiconductor device.

Referring again to FIG. 2, one or both of the conductive layers 108 and 110 provide electrical connections between components mounted to the substrate 100 and between components on the substrate 100 and external devices. It is etched or otherwise processed as described below to include the providing conductance pattern 120. In embodiments including conductance patterns in substrates comprising a plurality of top and bottom layers (as described below with reference to FIG. 9), and over both top 102 and bottom 104 of substrate 100. Vias (not shown) may be provided to transmit electrical signals between conductance patterns in other layers.

The substrate 100 further includes a plurality of regions 122, 124, and 126 (herein referred to as dummy circuit regions) having no conductance pattern. The dummy circuit pattern 130 according to embodiments of the present invention may be formed in one or more dummy circuit regions 122, 124, and 126. In alternative embodiments of the present invention, the size and shape of the conductance pattern 102 as well as the size and shape of the substrate 100 can vary greatly to define one or more dummy circuit regions of any size or shape. The dummy circuit 130 may be provided in any one or more of the dummy circuit regions. In embodiments, the dummy circuit pattern according to any of the embodiments described below may be provided on both sides of the substrate, even if the conductance pattern is provided on only one side of the substrate. It can be appreciated that a substrate that does not include a conductance pattern on its first surface or on a second surface opposite to the first surface may be used in a semiconductor device. Such a substrate may be formed with a dummy circuit pattern according to embodiments of the present invention.

In each of the embodiments described below, the dummy circuit pattern consists of lines and / or shapes. These lines and / or shapes are provided at one density in one or more dummy circuit regions. Density refers to the number, length and / or amount of material of conductive traces that form a dummy circuit pattern or conductance pattern per unit area on a substrate.

The stress level in a straight segment of a portion of the dummy circuit pattern is linearly or nonlinearly related to the length of the straight segment when the substrate is heated. In general, the longer the length, the greater the stress upon heating.

Regarding the maximum length of the straight segments in any portion of the dummy circuit pattern according to the embodiments described below, the length of the straight segments is set to keep the stress in the straight segments below the desired level. In particular, the stress per unit length of a straight segment of a portion of a dummy circuit is experimental and / or as a function of existing physical properties, and the type of materials used, the thickness of materials used, and the temperature range applied to the materials. It can be determined by the action of the substrate materials. This analysis may include other features.

Given this information, the maximum length of a straight segment of a portion of the dummy circuit is selected to keep the stress within that segment below any desired predetermined level. That is, by knowing the stress accumulated per unit length, one can select the desired maximum stress and then set the length of some or all of the straight segments of the dummy circuit to maintain the stress at or below the selected stress level. In embodiments of the present invention, a quantitative analysis of stress per unit length need not be performed, but instead the maximum length of the straight segment can be estimated. In addition, in embodiments of the present invention, the dummy circuit pattern includes straight segments, and upon heating these segments are subject to stresses that exceed a predetermined maximum.

Regardless of other factors that can cause stress in the substrate, with respect to the density of the dummy circuit pattern, the stress in the substrate can be minimized when the density of the dummy pattern becomes similar to the density of the conductance pattern. Thus, in embodiments of the present invention, the density of the dummy circuit pattern may be selected to be similar to the density of certain conductance patterns on the substrate. Alternatively, the density of the dummy circuit pattern may be selected to be greater or less than the density of the conductance pattern so that the resulting stress on the substrate is maintained within some acceptable level. In embodiments of the present invention, it can be appreciated that a quantitative analysis of the stress resulting from the density difference between the dummy circuit pattern and the conductance pattern need not be performed, and instead the density of the dummy circuit pattern can be estimated.

In the embodiment shown in FIG. 2, dummy circuit pattern 130 is formed of a plurality of adjacent alignment cells 130 ′ that are etched into layer 108 and / or 110. Each of the adjacent cells may have a uniform shape and may be fitted together so that no space is left between the cells. In alternative embodiments, it can be appreciated that the individual cells can be fitted together to leave a space between them. The pattern 130 is etched or otherwise processed so that no straight line extends through any two adjacent cells 130 '. In the embodiment shown in FIG. 2, the individual cells 130 ′ are hexagonal, forming a honeycomb pattern 130. However, it is to be understood that in alternative embodiments, other shapes may be used, such as, for example, adjacent circles, octagons, and other polygons except triangular, rectangular and square. (Triangles, rectangles, and squares can be used in a form in which two adjacent shapes are adjacent to each other so that a straight line extending over their shapes is not formed.)

As shown, the length of the various straight segment traces forming the pattern 130 can be controlled to maintain the stress generation within the straight segments below a certain desired stress level. However, in embodiments, the length of the straight segments forming each cell 130 ′ may be in the range of about 50 μm to 250 μm, more specifically in the range of 70 μm to 150 μm. In alternative embodiments, the maximum length of the cell 130 'segment may have a maximum diameter of greater than 250 μm or less than 50 μm. In embodiments, the width of the individual traces that form the various sides of each cell 130 ′ ranges from about 70 μm to 150 μm, but in alternative embodiments of the present invention the width of each cell is greater than this range. It can be large or small. Each of the dummy circuit regions 122 to 126 may include cells 130 ′ having the same size. Alternatively, as shown in FIG. 2, the cells in one or more regions 122, 124 may be larger than the cells 130 ′ in the remaining dummy circuit regions 126. As indicated above, the dummy circuit pattern 130 may be omitted from one or more dummy circuit regions. In addition, as described below, the individual cells 130 'in a given dummy circuit region may have different sizes.

In the embodiment of FIG. 2, each individual cell 130 ′ has a uniform shape. In a second alternative embodiment shown in FIG. 4, the one or more dummy regions 122, 124, and 126 may include a dummy circuit pattern 140 that includes a plurality of irregularly shaped cells 140 ′. Include. Any shape of the cells 140 'may be created with a pattern mask disposed on the substrate as described below. The controller for generating such a pattern mask may include software for generating arbitrary shapes. Alternatively, a configuration of arbitrary shapes is generated and then the information is passed to a system that creates a pattern mask. Although FIG. 4 shows polygons of any shape, straight edges, in other embodiments of the invention one or more cells 140 ′ may have curved edges.

In embodiments, each arbitrary shaped cell 140 ′ may be disposed at any location within a given dummy circuit area. Alternatively, each dummy circuit region may be subdivided into predetermined subregions, and cell distribution is controlled through the various subregions, but positioning of the cell 140 'within the predetermined subregion is arbitrarily determined. . As a further alternative, the position of each arbitrary shaped cell is predetermined within the dummy circuit area.

In general, as in the embodiment of FIG. 2, no two adjacent cells 140 ′ have adjacent straight lines extending through them. In this embodiment, although the edges of two arbitrary shaped cells can be aligned, the probability that any two arbitrary shapes of adjacent cells have an alignment side is very small to form a straight line between them. In one embodiment of the present invention, the average length of any side of any shaped cell 140 'may range from 0.3 mm to 1 mm. However, in alternative embodiments of the present invention, it can be appreciated that the average length of any side of any shaped cell 140 'may be larger or smaller than this range. It can also be seen that the standard deviation from this average size may vary in alternative embodiments of the present invention. In embodiments, the thickness of lines 140 ′ may be about 50 μm, but this thickness may vary in embodiments of the present invention.

The average size of cells 140 'of any shape may be the same or different in other dummy circuit regions 122-126. Similarly, dummy circuit pattern 140 may be omitted from one or more dummy circuit regions 122-126. In general, the density of the dummy circuit pattern 140 may be controlled to be equal to, smaller or larger than the density of the conductance pattern 120 as described above.

In the embodiment shown in FIG. 4, all or most of the cells 140 ′ are closed polygons. In the third embodiment shown in FIG. 5, the chip carrier substrate 100 includes a conductance pattern 120 and one or more dummy circuit regions 122 to 126, each of which is a line of arbitrary orientation. And a dummy circuit pattern 150 composed of the fields 150 '. Lines 150 ′ may be straight or curved. In the case of a straight line, the length of each line 150 'may be selected to be smaller than a predetermined length. Alternatively, the average length of all lines 150 'may be selected to be less than a predetermined length. Similarly, as described above, the density of the lines in the dummy circuit pattern 150 may be similar to, or greater than or less than the density of the conductance pattern. In embodiments, the thickness of lines 150 ′ may be about 50 μm, but this may vary in embodiments of the present invention.

In the above embodiment, the lines 150 'are arranged in any orientation, have any size (within a predetermined range), and are arbitrarily positioned. In alternative embodiments, one or more of the orientation, length, and position of the lines 150 'may be controlled to be not arbitrary. Thus, for example, the orientation and position of the lines in pattern 150 are arbitrary and the length can be controlled. Alternatively, the orientation and position of the lines in pattern 150 may be arbitrary and the position may be partially or fully controlled. Similarly, the length and position of the lines 150 'are arbitrary and their orientation can be controlled. Each feature of the lines 150 ′ described above may be the same for each dummy circuit region, or the features described above may vary in one dummy circuit region and the next dummy circuit region.

6 illustrates another embodiment of the present invention that includes a substrate 100 having a conductance pattern 120 and dummy circuit regions 122-126. In the embodiments described so far, the lines and shapes shown as dummy circuit patterns in the figures represent trace materials that are left behind the substrate or otherwise formed on the substrate after the pattern is etched. In contrast, in the embodiment of FIG. 6, each of the dummy circuit regions includes a dummy circuit pattern 160, where the white lines in the figure represent material that is etched away during the manufacturing process, and the dark background indicates that the dummy circuit pattern is missing. Represents material from layers 108 or 110 that are left behind after it is formed. The dummy circuit pattern 160 of FIG. 6 may become the idea of “negative” of the dummy circuit pattern 150 shown in FIG. 5. In alternative embodiments of the present invention, the dummy circuit pattern may include the negative (ie, negative structure) of the dummy circuit patterns shown in FIGS. 2-4 and FIGS. 7 and 8 described below.

The dummy circuit pattern 160 includes etched lines 160 ′. Etched lines 160 ′ may have any of the features of lines 150 ′ from dummy circuit pattern 150 of FIG. 5. In the embodiment of FIG. 6, preferably, the length and density of the lines 160 ′ generally allow for certain acceptable levels of stress in the dummy circuit pattern 160 and the substrate 100 as described above. It is selected to reduce the amount of material in layer 108 or 110 after manufacture to maintain levels.

FIG. 7 illustrates another embodiment of the present invention including a substrate 100 having a conductance pattern 120 and dummy circuit regions 122-126. One or more of the dummy circuit regions includes a dummy circuit pattern 170 composed of a plurality of shapes 170 ′. In the embodiment shown in FIG. 7, each of the shapes 170 ′ is close to the outline of the letter “C”, and material from within that outline is etched away during the manufacturing process. In alternative embodiments of the present invention, various other contour shapes are provided. Alternatively, these shapes can be "filled". That is, material from within the outer contour of the shape may be left after the etching process.

In the above embodiment, most of the segments forming shapes 170 'are bent. Curved shapes have an advantage in that stress in the shape is minimized. In addition, semiconductor die and other components are more sensitive to patterns on the substrate that are aligned along the axis of the die and the component (s). The bent shape reduces stress, which would cause stress to the semiconductor die or other component mounted over the shape on the substrate if the shape was not bent. However, in alternative embodiments of the present invention, the shapes 170 ′ may be defined by a complete straight line or a partial straight line.

As shown in FIG. 7, each of the shapes 170 ′ is spaced from each other. In alternative embodiments of the invention, the shapes may overlap. In addition, each of the shapes (as in dummy circuit regions 122 and 124) may have the same orientation, or the orientation of the shapes 170 ′ (as in dummy circuit region 126) may be different. The size of each of the shapes 170 'in a given dummy circuit area may be the same or different from each other, and the sizes of the shapes 170' in the next dummy area from one dummy area may be the same or different (Fig. 7). The number, size, and / or position of the shapes 170 'may be controlled or arbitrary in each dummy circuit area.

8 illustrates another embodiment of the present invention including a substrate 100 having a conductance pattern 120 and one or more dummy circuit regions 122-126. At least one of the dummy circuit regions 122 to 126 includes a dummy circuit pattern 180 formed of a plurality of cells 180 '. FIG. 8 is similar to the embodiment of FIG. 2 described above except that each of the cells 180 'forming the dummy circuit pattern 180 does not have the same size or shape as each other cell 180'. . In the embodiment shown in FIG. 8, the plurality of larger hexagonal cells 180 ′ are combined with the plurality of smaller hexagonal cells 180 ′. Cells 180 'have the features described above with respect to cells 130' of FIG.

As indicated above, in embodiments of the present invention, a plurality of layers 108 and 110 may be provided on each of the top and bottom surfaces of the core 106 in the substrate 100. This embodiment is shown in the cross section of FIG. In the above embodiment, the core comprises three layers 108 (each of which is formed in a thin layer by the solder mask layer 112 at the top surface 102), and the substrate 100 has three layers ( 110, each of which is formed in a thin layer by the solder mask layer 114 at the bottom surface 104. One or more layers 108 and 110 include conductance pattern 120 and a dummy circuit pattern according to any of the embodiments described above. The dummy circuit patterns in the various layers 108 are aligned with each other, or not with each other in other embodiments of the present invention. The same is true for the dummy circuit patterns formed in the layers 110.

10 is a cross-sectional view of a semiconductor package 182 that may be formed using a substrate 100 including a dummy circuit pattern in accordance with any of the embodiments described above. While not critical to the present invention, FIG. 10 shows two semiconductor dies 184 stacked on top surface 102 of substrate 100. Embodiments of the present invention may operate on a single die or on three to eight or more stacked dies in SiP, MCM or other type of alignment. Also, although not critical to the present invention, one or more dies 184 may be controller chips such as flash memory chips (NOR / NAND), SRAM, or DDT, and / or ASICs. Other silicon chips may also be considered.

The dummy circuit pattern according to the embodiments of the present invention described above controls and / or minimizes mechanical stress on the substrate 100 and warpage of the substrate 100. This improves overall yield by controlling and / or minimizing the stresses occurring on die 184.

Using existing die attach compounds 186, one or more dies 184 may be mounted to the top surface 102 of the substrate 100 by conventional adhesive or eutectic die bond processes. One or more die 108 may be electrically connected to conductive layers 108, 110 of substrate 100 by wire bonds 188 through a conventional wire bond process. After the wire bond process, the circuit is packaged in the molding compound 190 by an existing molding process, thereby completing the package 182.

In addition to reducing stress and warpage, the dummy circuit pattern according to various embodiments described above may also perform an electrical function. The dummy circuit pattern may be connected to the power supply VDD to provide a path to ground VSS or to power the semiconductor die and / or other components mounted on the substrate. Alternatively, the dummy circuit pattern can carry signals to and from semiconductor die and substrate components. In other embodiments, the dummy circuit pattern may not be “floating”, ie have no electrical function.

There are many existing processes for forming various embodiments of the conductance pattern 120 and the dummy circuit pattern on the substrate 100. One such process is described with reference to the flowchart of FIG. 11. In step 150, the surfaces of the conductive layers 108 and 110 are cleaned. In step 152, a photoresist film is applied to the surfaces of the layers 108 and 110. In step 154, a pattern photomask comprising the contour of the electrical conductance pattern and the dummy circuit pattern is placed over the photoresist film. Using existing processes, dummy circuit patterns and conductance patterns are formed on the photomask. As indicated above, where the dummy circuit pattern includes the formation of any lines or shapes on the substrate, any existing existing production process may include a photomask to include any lines or shapes in accordance with an embodiment of the invention. May be associated with formation.

Once the photomask is applied over the photoresist film, the photoresist film is exposed (step 156) and developed (step 158) to remove the photoresist film from the areas on the conductive layers to be etched. The exposed areas are then etched using an etchant, such as ferric chloride, in step 160 to define the conductance pattern and the dummy circuit pattern on the core. Next, in step 162 the photoresist film is removed, and in step 164 a solder mask layer is formed.

The overall process for forming the finished die package 182 is described with reference to the flowchart of FIG. Substrate 100 begins as a large panel that is separated into individual substrates after manufacture. In step 220, the panel is drilled to provide reference holes, from which the positions of the respective substrates are defined. Then, as described above, in step 222, a conductance pattern and a dummy circuit pattern are formed on each surface of the panel. Thereafter, in step 224, the patterned panel is inspected and tested. Once inspected, in step 226, a solder mask is formed in the panel. Then, in step 228, the router separates the panel into individual substrates. The individual substrates are then inspected and tested once again in an automated step (step 230) and final visual inspection (step 232) to check for electrical operation, contamination, scratches and discoloration. The die attach process is then performed at step 234 on the inspected substrate, and then at step 236 the JEDEC standard (or other) package is formed by packaging the substrate and die into an existing injection mold process. In alternative embodiments, die package 182 that includes a dummy circuit pattern may be formed by other processes.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. This description is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The disclosed embodiments best explain the principles of the present invention and its practical applications to enable those skilled in the art to best utilize the present invention in various embodiments and for various modifications as are suited to the particular use contemplated. It is selected. The scope of the invention is defined by the appended claims.

Claims (16)

A dummy circuit pattern formed on a surface of a substrate for a semiconductor package, A first plurality of line segments forming a first shape on a surface of the substrate; And A second plurality of line segments forming a second shape adjacent to the first shape on a surface of the substrate, Here, the outlines of the first and second shapes do not include any straight line segments that cross over other line segments in a straight line, Wherein each line segment of the adjacent first and second shapes comprises a length based on a length determined to maintain the stress in the straight line segment below a predetermined stress level. Dummy circuit pattern formed on the surface. The method of claim 1, And a portion of the dummy circuit pattern is connected to at least one of a ground potential and a power supply potential. The method of claim 1, A portion of the dummy circuit pattern is configured to transmit electrical signals to at least one of the semiconductor die and the electronic components on the substrate, and to transmit electrical signals from at least one of the semiconductor die and the electronic components on the substrate. A dummy circuit pattern formed on a surface of a substrate for a semiconductor package, the semiconductor die being connected to at least one of the semiconductor die and the electronic components thereon. The method of claim 1, And a portion of the dummy circuit pattern is floated, the dummy circuit pattern formed on a surface of a substrate for a semiconductor package. delete delete The method of claim 1, And wherein the first and second shapes are polygons each having sides of the same length, respectively. The method of claim 1, Wherein the first and second shapes have arbitrary shapes. The method of claim 1, The first and second shapes are defined by a material from the conductive layer on the substrate, which material is left on the surface of the substrate for the semiconductor package, characterized in that it remains after etching away the peripheral portions of the conductive layer. Dummy circuit pattern. delete The method of claim 1, Wherein the first and second shapes are one of a hexagon, an octagon, and a circle. A method of reducing stress in at least a portion of a dummy circuit pattern formed on a substrate for a semiconductor package, the method comprising: Determining stress generation for straight length segments of the dummy circuit pattern; And Forming the dummy circuit pattern; Here, the length of the straight segment of the dummy circuit pattern is limited to the length determined to not cause stress exceeding a threshold value based on determining the occurrence of stress on the straight length segment of the dummy circuit pattern. To reduce stress in at least a portion of the dummy circuit pattern. 13. The method of claim 12, Wherein the stress on the straight length segment is determined by experiment. 13. The method of claim 12, Stress for the straight-length segment is determined by estimation. 13. The method of claim 12, Coupling a portion of the dummy circuit pattern to one of a ground potential or a power supply potential. 13. The method of claim 12, A portion of the dummy circuit pattern is transferred to the substrate to transmit electrical signals to at least one of the semiconductor die and the electronic components on the substrate, and to transmit electrical signals from at least one of the semiconductor die and the electronic components. Coupling to at least one of the semiconductor die and the electronic components on the device.

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