1320852 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝構造，特別係有 用以檢測一半導想測试機台之迴路阻抗之封| 【先前技術】 在半導體製程中’通常會利用一半導體測 一半導體封裝構造進行測試，以確保產品之品 既有半導趙封裝構造之型態’概可區分為側面 和底面具有外接端子等兩大類型，前述中具引 體封裝構 k 包含 S Ο P (s m a 11 〇 u 11 i n e p a c k a g e， 裝）、TSOP(thin small outline package,薄型小 y 及 TSSOP(thin shrink small outline package， 小尺寸封裝）等多種形式。此外，依據引腳數 可進一步區分為 TS0P 54_piri、TS〇p 66_pin 86-pin 等等。 在測試過程中，受測的半導體封裝構造會 一半導體測試機台之測試槽座内，槽座内之複 係一對一對應接觸該半導體封裝構造之該些引 行電性測試。然而，在重複的使用下，該半 台之該些探針會有銹化、歪斜、磨損或接 象，導致連續的測試錯誤。在測試進行中無 根或那一些探針會先行損傷而影響測試正確 在連續且固定的不良產生 試板）並重新測試先前誤測 才更換新的測試； 之半導體封裝構造 關於一種 :構造。 試機台對 質。目前 具有引腳 腳之半導 小尺寸封 L寸封裝） 薄型收縮 量之不同 及 TSOP 被裝載在 數個探針 腳，以進 體測試機 不良等現 預測那一 .’通常是 i座（或測 ’造成測 5 1320852 試時間的浪費。以往為了避免測試時間的浪費，會定期 且提前地更換所有的測試槽座以避免連續的測試錯 誤。所有被更換下來的測試槽座仍有部份良好的探針存 在’導致耗費的測試成本提高。 【發明内容】 本發明之主要目的係在於提供一種檢測半導體測 試機台之封裝構造’用以檢測該半導體測試機台之迴路 阻抗’另可依據檢測結果並分析比對以釐清或判斷迴路 阻抗是否有微斷裂、開路或短路之問題，以在預定排程 中獲得探針之變化資訊並判斷是否堪用。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明揭示一種檢測半導體測試機台 之封裝構ie用於測试該半導體測試機台之迴路阻抗，該 封裝構造主要包含一導線架之複數個引腳、一擬晶基 板、複數個被動元件以及一封膠體。其中每一引腳係具 有一内引腳與一外引腳。該擬晶基板係具有一上表面、 一下表面以及複數個設置於該上表面之第一銲墊與第 二鲜整*。該些被動元件係表面黏著於該擬晶基板之該下 表面，每一被動元件係具有一第一電極與一第二電極， 每一第一電極係電性連接至至少兩個之該些第一銲 墊，每一第二電極係電性連接至至少兩個之該些第二銲 整。該封膠趙係密封該擬晶基板、該些被動元件與該些 内引腳，且顯露該些外引腳。 發月的目的及解決其技術問題還可採用以下技術 6 -LJZU0DZ* 措施進一半也 步實現。 . 在前塊的封裝構造中，該擬晶基板係可共用迆，該 些第一銲墊與該些第二銲墊係區分為複數組晶月模擬 銲墊。 — 在前述的封裝構造中，該些第一銲墊與該些第二銲 墊係可為中央銲墊。 在前述的封裝構造中，該些第一銲墊與該些第二銲 % 墊係可為周邊銲墊。 在前述的封裝構造中，該擬晶基板可另包含有複數 個導通孔，以供雙面電性連接。 在前述的封裝構造中，可另包含有複數個銲線，其 係電性連接該擬晶基板與該導線架。 在前述的封裝構造中，可另包含一非導電膠材，其 係黏設該擬晶基板之該上表面於該導線架。 在前述的封襞構造中，該擬晶基板之厚度係可不大 I 於 0·26mm。 在前述的封裝構造中，該些被動元件之高度係可不 大於 0.27mm。 在前述的封裝構造中，該導線架係可另包含有一晶 片承座，該些被動元件係黏貼於該晶片承座。 在前述的封裝構造中，可另包含一非導電膠材，其 係黏設該些被動元件於該晶月承座。 在前述的封裝構造中，該些外引腳係可沿該封膠體 之周緣而下彎形成鷗型接腳。 7 1320852 在前述的封裝構造中，該些被動元件係Ί 晶片型被動元件。 【實施方式】 依據本發明之第一具體實施例，揭示一 體測試機台之封裝構造。請參閱第1圖所示 造100主要包含一導線架之複數個引腳ηο 擬晶基板130、複數個被動元件140以及一 j 該封裝構造1 00係用於測試一半導體測試 探針之迴路阻抗。在本實施例中，該導線架 承座，而是LOC(Lead-On-Chip，引腳在晶} 以該些引腳110與120黏接該擬晶基板130 係包含位於兩側之複數個第一引腳11 〇與 引腳120。依該封膠體150之内外作區分， 腳110係具有一第一内引腳111與一第一外 每一第二引腳120係具有一第二内引腳121 引腳122 。 該擬晶基板130係具有一上表面131、一 以及複數個設置於該上表面131之第一銲墊 銲墊134。該擬晶基板130不具有傳統晶片 或其它主動元件，該擬晶基板130之尺寸係 之尺寸，該擬晶基板130之第一銲墊133 1 34之數量與位置係可模擬至少一種以上晶 置。在本實施例中，該些第一銲墊133與該 134係可為中央銲墊。其中該擬晶基板130 T選自〇2〇1 種檢測半導 ，該封裴構 與 12〇 、 一 ΐ朦體1 5 0。 機台中包含 並未有晶片 ί上）型態， 。該些引腳 複數個第二 每一第一引 引腳112 ; 與一第二外 下表面1 3 2 133與第二 之積體電路 模擬一晶片 與第二銲墊 片之銲墊配 些第二銲墊 之具有銲墊 8 1320852· 之表面尺寸係為7.0 mm X 3.8mm。 較佳地’該擬晶基板130係可共用型，該些第一銲 墊133與該些第二銲墊134係區分為複數組晶片模擬銲 整’以供製成不同之封裝構造。例如，該些第一銲墊 133或該些第一鲜塾134在相同功能的部分係為串連， 由内而外分為三排，該些第一銲墊133與該些第二銲墊1320852 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a package structure, particularly useful for detecting a loop impedance of a half-test test machine. [Prior Art] In a semiconductor process, 'generally It will be tested by a semiconductor test semiconductor package structure to ensure that the product has both a semi-conductive package structure type, which can be divided into two types: the side and the bottom have external terminals, and the above has a pull-on package. k includes S Ο P (sma 11 〇u 11 inepackage, installed), TSOP (thin small outline package, thin small y and TSSOP (thin shrink small outline package), etc. In addition, depending on the pin count Further divided into TS0P 54_piri, TS〇p 66_pin 86-pin, etc. During the test, the tested semiconductor package structure will be in the test socket of a semiconductor test machine, and the one-to-one correspondence in the socket The electrical conductivity tests of the semiconductor package structure. However, under repeated use, the probes of the half are rusted. , skewing, wear or jointing, resulting in continuous test errors. No roots or probes in the test will be damaged first, affecting the test in a continuous and fixed bad test plate) and retesting the previous misdetection before replacing the new one. Test; the semiconductor package construction relates to one: construction. The test machine is opposite. At present, there are semi-conductor small-size L-packages with pin-outs.) The difference in the amount of thin shrinkage and the TSOP are loaded on several probe pins, and the defect in the test machine is predicted. It is usually the i-seat (or Test 'causes the waste of the test time of 3 1320852. In the past, in order to avoid the waste of test time, all test sockets will be replaced regularly and in advance to avoid continuous test errors. All the test sockets that have been replaced are still partially good. The present invention is directed to providing a package structure for detecting a semiconductor test machine 'to detect the loop impedance of the semiconductor test machine'. The result is analyzed and compared to clarify or judge whether the loop impedance has a slight break, open circuit or short circuit to obtain the change information of the probe in a predetermined schedule and judge whether it is applicable. The object of the present invention and the technical problem thereof are The following technical solutions are adopted. According to the present invention, a package structure for detecting a semiconductor testing machine is used for testing. The circuit impedance of the semiconductor test machine is tested. The package structure mainly comprises a plurality of leads of a lead frame, a pseudo-crystal substrate, a plurality of passive components and a glue body, wherein each pin has an inner pin and An outer lead having an upper surface, a lower surface, and a plurality of first pads and second finishes disposed on the upper surface. The passive components are adhered to the surface of the crystal substrate Each of the passive components has a first electrode and a second electrode, each of the first electrodes is electrically connected to at least two of the first pads, and each of the second electrodes is electrically connected And at least two of the second soldering. The sealant seals the crystal substrate, the passive components and the inner leads, and exposes the outer leads. The purpose of the moon and the solution of the technology The problem can also be achieved by the following technique 6 - LJZU0DZ* measures. In the package structure of the front block, the crystal substrate can share the 迤, and the first pads are distinguished from the second pads. Simulate solder pads for complex arrays of crystals. — at In the package structure, the first pads and the second pads may be central pads. In the foregoing package structure, the first pads and the second pads may be In the foregoing package structure, the crystal substrate may further include a plurality of via holes for electrically connecting the two sides. In the foregoing package structure, a plurality of bonding wires may be further included. Electrically connecting the crystal substrate to the lead frame. In the foregoing package structure, a non-conductive rubber material may be further included, which is to adhere the upper surface of the crystal substrate to the lead frame. In the configuration, the thickness of the crystal substrate may be less than 0.16 mm. In the foregoing package structure, the height of the passive components may be no more than 0.27 mm. In the foregoing package structure, the lead frame may be another A wafer holder is included, and the passive components are adhered to the wafer holder. In the foregoing package construction, a non-conductive adhesive material may be further included, which is used to adhere the passive components to the crystal moon socket. In the foregoing package construction, the outer leads may be bent down along the circumference of the sealant to form a gull-type pin. 7 1320852 In the aforementioned package construction, the passive components are wafer type passive components. [Embodiment] According to a first embodiment of the present invention, a package structure of an integrated testing machine is disclosed. Referring to FIG. 1 , a plurality of pins including a lead frame ηο a crystal substrate 130 , a plurality of passive components 140 , and a package structure 100 are used to test the loop impedance of a semiconductor test probe. . In this embodiment, the lead frame is seated, but the LOC (Lead-On-Chip) is bonded to the pins 110 and 120. The crystal substrate 130 includes a plurality of sides on both sides. The first pin 11 〇 and the pin 120. According to the inside and outside of the sealant 150, the leg 110 has a first inner pin 111 and a first outer second pin 120 has a second inner The pinned substrate 130 has an upper surface 131, a plurality of first pad pads 134 disposed on the upper surface 131. The crystal substrate 130 does not have a conventional wafer or other active The size of the crystal substrate 130 is such that the number and position of the first pads 133 1 34 of the crystal substrate 130 can simulate at least one crystal. In this embodiment, the first solders The pad 133 and the 134 series may be a central pad. The crystal substrate 130 T is selected from the group consisting of 检测2〇1 detection semiconductors, and the sealing structure is 12 〇, one 1 body 150. The machine includes There is no wafer 上 on the type, . The plurality of pins are second and each of the first lead pins 112; and the second outer lower surface 1 3 2 133 and the second integrated circuit simulate a pad of the first and second solder pads. The surface of the two pads with pads 8 1320852· is 7.0 mm X 3.8 mm. Preferably, the crystal substrate 130 is of a common type, and the first pads 133 and the second pads 134 are divided into a plurality of wafers for analog soldering to make different package configurations. For example, the first pads 133 or the first fresh slabs 134 are connected in series in the same function, and are divided into three rows from the inside to the outside, and the first pads 133 and the second pads are
134之總數量可分別為86、66與54，以模擬TSOP 86-pin(thin small outline package 86 pins，具有 86 根引 腳之薄型小尺寸封裝）、TSOP 66-pin(thin sman outnne package 66 pins，具有66根引腳之薄型小尺寸封裝）與 TSOP 54-pin(thin small outline package 54 pins,具有 54根引腳之薄型小尺寸封裝）。故該封裝構造loo可直 接配合 TSOP 54-pin、TSOP 66-pin 或 TSOP 86-pin 之半 導禮測试機台之測試槽座作適當打線變化之封裝，不需 要因該擬晶基板130之銲整數量變更與線路設計重新 設另一種基板，故能對不同產品測試槽内探針作迴路阻 抗檢測。請參閱第2圖所示’該擬晶基板13〇可另包含 有複數個導通孔1 3 5，以達到雙面電性連接。 請再參閲第1圖所示，該封裝構造1〇〇可另包含有 一非導電膠材170’其係黏設該擬晶基板13〇之該上表 面131於該導線架之該些第一引腳11〇與該些第二引腳 12〇，且不遮蓋所預定打線之部分之該些第一銲塾m 與該些第二銲墊134«另可利用打線形成之複數個第一 銲線1 6 1係電性連接該擬晶基板丨3〇之該些第一銲墊 9 1320852 U3至該些第一引腳11()之該些第一内引腳111β複數 個第二銲線162係電性逹接該擬晶基板130之該些第二 銲墊134至該些第二引腳12〇之該些第二内引腳121。 在不同實施例中，亦可以熱壓合或是點焊方式使該擬晶 基板130與該導線架之該些第一引腳η〇與該些第二引 腳1 2 0之間達成内部電性互連。 請再參閱第1及3圖所示，該些被動元件丨4〇係表The total number of 134 can be 86, 66 and 54 respectively to simulate TSOP 86-pin (thin small outline package 86 pins, thin and small package with 86 pins), TSOP 66-pin (thin sman outnne package 66 pins) , thin and small package with 66 pins) and TSOP 54-pin (thin small outline package 54 pins, small package with 54 pins). Therefore, the package structure loo can be directly matched with the test socket of the TSOP 54-pin, TSOP 66-pin or TSOP 86-pin semi-guide test machine for proper wire change packaging, without the need for the crystal substrate 130 The welding quantity change and the circuit design are re-set another substrate, so the loop impedance detection can be performed on the probes in different product test slots. Referring to Fig. 2, the crystal substrate 13 can further include a plurality of via holes 135 to achieve a double-sided electrical connection. Referring to FIG. 1 again, the package structure 1 further includes a non-conductive adhesive material 170' for attaching the upper surface 131 of the crystal substrate 13 to the first portion of the lead frame. The first soldering wire m and the second soldering pads 134 of the pin 11 〇 and the second pin 12 〇, and not covering the portion of the predetermined wire, and the plurality of first solders formed by the wire bonding The wire 161 is electrically connected to the first pads 9 1320852 U3 of the susceptor substrate 至3, to the first inner leads 111β of the first pins 11(), and the plurality of second bonding wires The 162 is electrically connected to the second pads 134 of the crystal substrate 130 to the second inner leads 121 of the second pins 12 . In different embodiments, the pseudo-crystal substrate 130 and the first pins η 该 of the lead frame and the second pins 1 2 0 can be electrically connected to each other by thermal pressing or spot welding. Sexual interconnection. Please refer to Figures 1 and 3 again, the passive components 丨4〇
面黏著於該擬晶基板130之該下表面132，每一被動元 件140係具有一第一電極141與一第二電極142。在本 實施例中’該些被動元件1 40係為低成本且大量取得之The surface of the dummy substrate 140 has a first electrode 141 and a second electrode 142. In the present embodiment, the passive components 140 are low cost and are obtained in large quantities.
規格品’例如可選自0201晶片型電阻被動元件或更小 規格該些被動元件140之尺寸係為X 0.5mm* tb ^ , 、甲該些被動元件14〇之間之間距係約為 0.5mm。請表 ** 閱第4圖所示’該擬晶基板13 0之厚度係 可不大於The specification can be selected, for example, from a 0201 wafer type resistive passive component or a smaller size. The passive components 140 have a size of X 0.5 mm* tb ^ , and a passive component 14 is spaced apart by about 0.5 mm. . Please refer to Table **, as shown in Figure 4, the thickness of the crystal substrate 130 can be no more than
。該些被動元件14〇之高度係可不大 於 0.27mm，蚀# 災焊設該些被動元件140之高度可控制在 小於 0.3 m m，t 而能封裝在該封膠體150内部。. The height of the passive components 14〇 may be no more than 0.27 mm, and the passive components 140 may be controlled to be less than 0.3 mm, and can be packaged inside the encapsulant 150.
該封膠雜1 c Λ P i5〇係密封該擬晶基板130、該些被動元 件1 4 0、該此笛 ~第一内引腳111與該些第二内引腳121， 且顯露該班*第 , —乐〜外引腳112與該些第二外引腳122，以 供該半導趙泡丨 機台之測試槽座之複數個探針之雷姓 測觸《通常該此# ^些第一外引腳112與該些第二外引腳 係可沿該封腰_ 趙150之周緣而下彎形成鷗型接腳。 此外，請：Ha λ* 月麥閱第5圖所示，該些被動元件之每 10 Ι32Θ852 因此，該封裝構造1 Ο 0係可檢測該半導體測試機台 之迴路阻抗是否正常，由迴路阻抗辨識測試迴路中，該 些探針與該些第一引腳110及該些第二引腳120接觸比 率及該半導體測試機台之測試迴路校正》也就是說’利 用封閉迴路檢測電性特性，藉由電性特性以釐清或判斷 封閉迴路是否有微斷裂、開路或短路。此外，該封裝構 造100亦可檢測出是否有異常之探針，故僅需替換具異 常探針之測試槽座即可繼續使用，以降低測試時間與成 〇 在第二具體實施例中，揭示另一種檢測半導體測試 機台之封裝構造用於測試一半導體測試機台之迴路阻 抗。請參閲第6圖所示，該封裝構造200主要包含一導 線架之複數個引腳21〇與220、一擬晶基板230、複數 個被動元件240以及一封膠體250。在本實施例中，該 導線架係可另包含有一晶片承座280，以供設置該些被 動元件240 »該些引卿係包含位於兩側之複數個第一引 腳210與複數個第二引腳220。每一第一引腳210係具 有一第一内引腳211與一第一外引腳212;每一第二引 腳220係具有一第二内引腳221與一第二外引腳222 〇 該擬晶基板230係具有一上表面231、一下表面232 以及複數個設置於該上表面231之第一銲墊233與第一 銲墊234。可利用複數個第一銲線261係電性連接該擬 晶基板230之該些第一銲墊233至該些第一 5丨腳21〇之 該些第一内引腳211。複數個第二銲線262係電性連接 12 1320852· 該擬晶基板230之該些第二銲墊234至該些第二引腳 220之該些第二内引腳221。 請參閱第7圖所示，該擬晶基板230係可共用型， 該些第一銲墊233與該些第二銲墊234係區分為複數組 晶片模擬銲墊。在本實施例中，該些第一銲墊233與該 些第二銲墊234係可為周邊銲墊。其中該擬晶基板230 另包含有複數個導通孔235，以供雙面電性連接。 請參閱第6及8圖所示，該些被動元件240係表面 黏著於該擬晶基板230之該下表面232，每一被動元件 240係具有一第一電極241與一第二電極242，每一第 一電極241係電性連接至至少兩個之該些第一銲墊 233，每一第二電極242係電性連接至至少兩個之該些 第二銲墊234。請再參閱第6圖所示，該些被動元件240 可利用一非導電膠材270之黏貼，使該些被動元件240 黏貼於該晶片承座280»藉由該非導電膠材270之非導 電避免該些被動元件240之第一電極241與第二電極 242產生電性短路’進而影響測試結果。 該封膠體250係密封該擬晶基板23〇、該些被動元 件240、該些第一内引腳211與該些第二内引腳221， 且顯露該些第一外引腳212與該些第二外引腳222，以 供該半導體測試機台之複數個探針進行電性探測。故該 封裝構造200係可用以檢測該半導體測試機台之迴路 阻抗是否正常β 以上所述’僅是本發明的較佳實施例而已，並非對 13 本發明作任何形式上的 限制， 雖然本發明已以較佳實施The sealant 1 c Λ P i5 密封 seals the crystal substrate 130, the passive components 1400, the flute first inner lead 111 and the second inner leads 121, and reveals the class *, -, Le ~ outer pin 112 and the second outer pin 122, for the plurality of probes of the test slot of the semi-conductive bubble machine, the name of the probe is "usually this # ^ The first outer leads 112 and the second outer leads are bent down along the circumference of the waist _ _ 150 to form a gull-type pin. In addition, please: Ha λ* Month, as shown in Figure 5, each of the passive components is 10Θ32Θ852. Therefore, the package structure 1 Ο 0 can detect whether the loop impedance of the semiconductor test machine is normal, and the loop impedance is recognized. In the test loop, the ratio of the probes to the first pins 110 and the second pins 120 and the test loop of the semiconductor test machine are corrected, that is, the electrical characteristics are detected by using a closed loop. The electrical characteristics are used to clarify or determine whether the closed loop is slightly broken, open or shorted. In addition, the package structure 100 can also detect whether there is an abnormal probe, so it is only necessary to replace the test socket with the abnormal probe to continue to use, so as to reduce the test time and the formation in the second embodiment, revealing Another package configuration for detecting a semiconductor test machine is used to test the loop impedance of a semiconductor test machine. Referring to FIG. 6, the package structure 200 mainly includes a plurality of pins 21 and 220 of a wire frame, a crystal substrate 230, a plurality of passive components 240, and a colloid 250. In this embodiment, the lead frame may further include a wafer holder 280 for disposing the passive components 240. The guiding system includes a plurality of first pins 210 and a plurality of second portions on both sides. Pin 220. Each of the first pins 210 has a first inner pin 211 and a first outer pin 212. Each second pin 220 has a second inner pin 221 and a second outer pin 222. The crystal substrate 230 has an upper surface 231, a lower surface 232, and a plurality of first pads 233 and first pads 234 disposed on the upper surface 231. A plurality of first bonding wires 261 are electrically connected to the first pads 233 of the dummy substrate 230 to the first inner leads 211 of the first and second legs 21 。. The plurality of second bonding wires 262 are electrically connected to the second bonding pads 234 of the second substrate 220 to the second inner leads 221 of the second pins 220. Referring to FIG. 7, the crystal substrate 230 is of a common type, and the first pads 233 and the second pads 234 are divided into a plurality of wafer dummy pads. In this embodiment, the first pads 233 and the second pads 234 may be peripheral pads. The microcrystal substrate 230 further includes a plurality of via holes 235 for electrical connection on both sides. Referring to FIGS. 6 and 8, the passive components 240 are adhered to the lower surface 232 of the crystal substrate 230. Each of the passive components 240 has a first electrode 241 and a second electrode 242. A first electrode 241 is electrically connected to at least two of the first pads 233, and each of the second electrodes 242 is electrically connected to at least two of the second pads 234. Referring to FIG. 6 again, the passive components 240 can be adhered to the wafer holder 280 by using a non-conductive adhesive 270 to be non-conductive by the non-conductive adhesive 270. The first electrode 241 of the passive component 240 and the second electrode 242 generate an electrical short circuit' to affect the test result. The encapsulant 250 seals the crystal substrate 23 , the passive components 240 , the first inner leads 211 and the second inner leads 221 , and exposes the first outer leads 212 and the The second outer lead 222 is electrically probed by a plurality of probes of the semiconductor testing machine. Therefore, the package structure 200 can be used to detect whether the loop impedance of the semiconductor test machine is normal or not. The above is merely a preferred embodiment of the present invention, and does not impose any form limitation on the present invention, although the present invention Better implemented
容，依據本發明的技術實質對以上實施例所作的任 何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：依據本發明之第一具體實施例，一種檢測半導 體測试機台之封裝構造之截面示意圖。 第2圖.依據本發明之第一具體實施例，該封裝構造中 一擬晶基板之上表面示意圖。 第3圖：依據本發明之第一具體實施例，該封裝構造中 該擬晶基板之下表面示意圖。 第4圖：依據本發明之第一具體實施例，該封裝構造中 複數個被動元件設置於該擬晶基板之側面示 意圖。 第5圖：依據本發明之第一具體實施例，繪示該封裝構 造中該些被動元件連接該擬晶基板之複數個 銲墊之線路示意圖。 第6圖：依據本發明之第二具體實施例’另一種檢測半 導體測試機台之封裝構造之截面示意圖。 第7圖：依據本發明之第二具體實施例’該封裝構造中 1320852 一擬晶基板之上表面示意圖。 第8圖：依據本發明之第二具體實施例，該封裝構造中 該擬晶基板之下表面示意圖。Any simple modifications, equivalent changes and modifications made to the above embodiments in accordance with the technical spirit of the present invention are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a package structure for detecting a semiconductor test machine in accordance with a first embodiment of the present invention. Fig. 2 is a schematic view showing the upper surface of a crystal substrate in the package structure according to the first embodiment of the present invention. Fig. 3 is a schematic view showing the lower surface of the crystal substrate in the package structure according to the first embodiment of the present invention. Figure 4: In accordance with a first embodiment of the present invention, a plurality of passive components in the package configuration are disposed on a side of the crystal substrate. Figure 5 is a schematic view showing the circuit of a plurality of pads of the passive component connected to the crystal substrate in the package structure according to the first embodiment of the present invention. Figure 6 is a cross-sectional view showing another package structure for detecting a semiconductor test machine in accordance with a second embodiment of the present invention. Figure 7 is a schematic view showing the upper surface of a 1320852 mesomorphic substrate in the package structure according to a second embodiment of the present invention. Figure 8 is a schematic view showing the lower surface of the crystal substrate in the package structure in accordance with a second embodiment of the present invention.
【主要元件符號說明】 100 封裝構造 110 第一引腳 111 第 一内引腳 112 第 一外引腳 120 第二引腳 121 第 二内引腳 122 第 二外引腳 130 擬晶基板 131 上 表面 132 下表面 133 第一鲜堅 134 第 二銲墊 135 導通孔 140 被動元件 141 第 一電極 142 第 二電極 150 封膠體 161 第 一銲線 162 第 二銲線 170 非導電膠材 200 封裝構造 210 第一引腳 211 第 一内引腳 212 第 一外引腳 220 第二引腳 221 第 二内引腳 222 第 二外引腳 230 擬晶基板 231 上 表面 232 下表面 233 第一銲墊 234 第 二銲墊 235 導通孔 240 被動元件 241 第 一電極 242 第 一·電極 250 封膠體 261 第 一銲線 262 第 二銲線 270 非導電膠材 280 晶片承座 15[Main component symbol description] 100 package structure 110 first pin 111 first inner pin 112 first outer pin 120 second pin 121 second inner pin 122 second outer pin 130 top surface of the crystal substrate 131 132 lower surface 133 first fresh 134 second solder pad 135 via hole 140 passive element 141 first electrode 142 second electrode 150 sealant 161 first bond wire 162 second bond wire 170 non-conductive adhesive material 200 package structure 210 a pin 211 a first inner pin 212 a first outer pin 220 a second pin 221 a second inner pin 222 a second outer pin 230 a crystal substrate 231 upper surface 232 a lower surface 233 a first pad 234 second Solder pad 235 via 240 passive element 241 first electrode 242 first electrode 250 sealant 261 first bond wire 262 second bond wire 270 non-conductive adhesive 280 wafer carrier 15