TWI317878B - Systems with variable link widths - Google Patents

Systems with variable link widths

Info

Publication number
TWI317878B
TWI317878B TW095121605A TW95121605A TWI317878B TW I317878 B TWI317878 B TW I317878B TW 095121605 A TW095121605 A TW 095121605A TW 95121605 A TW95121605 A TW 95121605A TW I317878 B TWI317878 B TW I317878B
Authority
TW
Taiwan
Prior art keywords
systems
variable link
link widths
widths
variable
Prior art date
Application number
TW095121605A
Other languages
English (en)
Other versions
TW200708968A (en
Inventor
James Mccall
Bruce Christenson
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200708968A publication Critical patent/TW200708968A/zh
Application granted granted Critical
Publication of TWI317878B publication Critical patent/TWI317878B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Circuits Of Receivers In General (AREA)
  • Power Sources (AREA)
  • Memory System (AREA)
  • Communication Control (AREA)
TW095121605A 2005-06-17 2006-06-16 Systems with variable link widths TWI317878B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/155,857 US7694060B2 (en) 2005-06-17 2005-06-17 Systems with variable link widths based on estimated activity levels

Publications (2)

Publication Number Publication Date
TW200708968A TW200708968A (en) 2007-03-01
TWI317878B true TWI317878B (en) 2009-12-01

Family

ID=37571304

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095121605A TWI317878B (en) 2005-06-17 2006-06-16 Systems with variable link widths

Country Status (8)

Country Link
US (1) US7694060B2 (zh)
JP (1) JP4954991B2 (zh)
KR (1) KR100941023B1 (zh)
CN (1) CN101198942B (zh)
DE (1) DE112006001541T5 (zh)
GB (1) GB2440076B (zh)
TW (1) TWI317878B (zh)
WO (1) WO2006138740A2 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7782805B1 (en) 2005-02-08 2010-08-24 Med Belhadj High speed packet interface and method
US7596742B1 (en) * 2006-03-28 2009-09-29 Advanced Micro Devices, Inc. Error detection in a communication link
US8861952B2 (en) * 2007-02-28 2014-10-14 Finisar Corporation Redundancy and interoperability in multi-channel optoelectronic devices
US8526810B2 (en) * 2007-04-30 2013-09-03 Finisar Corporation Eye safety and interoperability of active cable devices
US8649262B2 (en) * 2008-09-30 2014-02-11 Intel Corporation Dynamic configuration of potential links between processing elements
US8135972B2 (en) 2009-03-10 2012-03-13 Cortina Systems, Inc. Data interface power consumption control
DE102009021944A1 (de) * 2009-05-19 2010-12-02 Texas Instruments Deutschland Gmbh Elektronische Vorrichtungen und Verfahren zum Speichern von Daten in einem Speicher
KR101548891B1 (ko) * 2010-11-19 2015-09-01 샤프 가부시키가이샤 데이터 전송 회로, 데이터 전송 방법, 표시 장치, 호스트측 장치 및 전자 기기
US9417687B2 (en) * 2011-07-12 2016-08-16 Rambus Inc. Dynamically changing data access bandwidth by selectively enabling and disabling data links
DE112013007751B3 (de) * 2012-10-22 2023-01-12 Intel Corporation Hochleistungs-Zusammenschaltungs-Bitübertragungsschicht
US9430434B2 (en) * 2013-09-20 2016-08-30 Qualcomm Incorporated System and method for conserving memory power using dynamic memory I/O resizing
JP6085739B1 (ja) * 2016-04-12 2017-03-01 株式会社セレブレクス 低消費電力表示装置
KR102576159B1 (ko) * 2016-10-25 2023-09-08 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396635A (en) 1990-06-01 1995-03-07 Vadem Corporation Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system
JPH04359335A (ja) 1991-06-06 1992-12-11 Fujitsu Ltd メモリアクセス方式
US5781784A (en) 1992-07-09 1998-07-14 Zilog, Inc. Dynamic power management of solid state memories
JPH08223390A (ja) 1995-02-10 1996-08-30 Murata Mach Ltd 全二重モデムを有したファクシミリ装置
US5911053A (en) * 1996-09-30 1999-06-08 Intel Corporation Method and apparatus for changing data transfer widths in a computer system
US5881013A (en) * 1997-06-27 1999-03-09 Siemens Aktiengesellschaft Apparatus for controlling circuit response during power-up
US6009488A (en) 1997-11-07 1999-12-28 Microlinc, Llc Computer having packet-based interconnect channel
DE19822259C2 (de) 1998-05-18 2000-07-06 Siemens Ag Sendeeinrichtung und Bussystem zur Datenübertragung
JP2000261435A (ja) 1999-03-05 2000-09-22 Nec Corp 最小帯域保証接続方法及び装置
JP2001022690A (ja) 1999-07-09 2001-01-26 Canon Inc 装置間のデータ通信方法及びそのシステム
US6681285B1 (en) * 1999-07-22 2004-01-20 Index Systems, Inc. Memory controller and interface
US6526469B1 (en) 1999-11-12 2003-02-25 International Business Machines Corporation Bus architecture employing varying width uni-directional command bus
US6665742B2 (en) 2001-01-31 2003-12-16 Advanced Micro Devices, Inc. System for reconfiguring a first device and/or a second device to use a maximum compatible communication parameters based on transmitting a communication to the first and second devices of a point-to-point link
JP2002259327A (ja) 2001-02-28 2002-09-13 Hitachi Ltd バス制御回路
JP3523616B2 (ja) 2001-07-24 2004-04-26 松下電器産業株式会社 バス最適化方法及び通信ノード
US20030088799A1 (en) 2001-11-05 2003-05-08 Bodas Devadatta V. Method and apparatus for regulation of electrical component temperature and power consumption rate through bus width reconfiguration
US7137018B2 (en) 2002-12-31 2006-11-14 Intel Corporation Active state link power management
US7111108B2 (en) * 2003-04-10 2006-09-19 Silicon Pipe, Inc. Memory system having a multiplexed high-speed channel
US7136953B1 (en) * 2003-05-07 2006-11-14 Nvidia Corporation Apparatus, system, and method for bus link width optimization
US8046488B2 (en) 2004-05-21 2011-10-25 Intel Corporation Dynamically modulating link width
US7197591B2 (en) 2004-06-30 2007-03-27 Intel Corporation Dynamic lane, voltage and frequency adjustment for serial interconnect

Also Published As

Publication number Publication date
WO2006138740A2 (en) 2006-12-28
DE112006001541T5 (de) 2008-04-30
JP4954991B2 (ja) 2012-06-20
CN101198942A (zh) 2008-06-11
KR100941023B1 (ko) 2010-02-05
GB2440076A (en) 2008-01-16
GB2440076B (en) 2010-12-29
CN101198942B (zh) 2010-12-22
US7694060B2 (en) 2010-04-06
GB0721287D0 (en) 2007-12-12
US20060285847A1 (en) 2006-12-21
KR20080016639A (ko) 2008-02-21
WO2006138740A3 (en) 2007-03-29
JP2008544378A (ja) 2008-12-04
TW200708968A (en) 2007-03-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees