TWI314031B - Stack structure of circuit board with semiconductor component embedded therein - Google Patents

Stack structure of circuit board with semiconductor component embedded therein Download PDF

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Publication number
TWI314031B
TWI314031B TW095119330A TW95119330A TWI314031B TW I314031 B TWI314031 B TW I314031B TW 095119330 A TW095119330 A TW 095119330A TW 95119330 A TW95119330 A TW 95119330A TW I314031 B TWI314031 B TW I314031B
Authority
TW
Taiwan
Prior art keywords
circuit board
layer
conductive
circuit
embedded
Prior art date
Application number
TW095119330A
Other languages
English (en)
Other versions
TW200803677A (en
Inventor
Shih Ping Hsu
Chung Cheng Lien
Chia Wei Chang
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW095119330A priority Critical patent/TWI314031B/zh
Priority to US11/756,403 priority patent/US7656040B2/en
Publication of TW200803677A publication Critical patent/TW200803677A/zh
Application granted granted Critical
Publication of TWI314031B publication Critical patent/TWI314031B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
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    • H01L2224/48091—Arched
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/078—Adhesive characteristics other than chemical
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Description

1314031 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種嵌埋有半導體元件之電路 =二指一種電路板嵌埋有半導體元件’再疊接:電 【先前技術】 著化已是現今電子產業發展之趨勢，而隨 者包子產口口製作之縮小化，對於各種不同功能之 件鑲嵌在-電路板上則有朝更高密度之需求。因此 用需求，而在單一封裝件之晶片承載件(例如基 曰反或ν、Ή)上接置並電性連接有至少二個以上之半導體 ^曰片，且晶片與承載件間之接置方式係將半導體晶片一 向上豐接在承載件上，再以焊線進行電性連接。 片半圖，係為美國專利第5,323，_號之多晶 +¥體封褎件！之剖面示意圖，係將一第一半 12a接置於一電路板u上，並 日日 接至兮+炊k ·μ e由弟一知線13a以電性連 接至遠I路板U，且採料疊方式（咖㈣以將 導體晶片12b間隔一膠層14堆疊於該 — 上，而該膠層14之材質一俨為产气腴 ’曰日片12a 貝叙為％^|(ep〇xy)或膠帶 (tape)，之後再藉由一第__ M ^ 〃 弟一坏線13b電性連接至該電路板 。惟该第一半導體晶片12之焊 在該第二半導體曰以广：線衣私(咖需 aH w ¥“日片Ub堆豐1^完成先進行，亦即每-厚 曰曰片之4 (che bGnding)製似料 曰 因而增加額外之製程複雜产.以& j而刀別進订， 程稷^度，再者，由於該第一半導體晶 5 19375 1314031 片12a、膠層μ與第二半導么 聂於兮年， ¥體曰曰片1213係一—順序向上堆 广亥電路板11JL，且為有效 二隹 觸碰至筮—μ日Μ , 〇 卞夺篮晶片12b 線 、干線13a’該膠層Μ厚度必須增高至該第一焊 :之線弧高度以上’如此’不僅增加該多晶片之 -封裝件1之整體厚度，而不利於半導體 ， 同睹R1兮_ k? 置之fe缚化， 守口 δ亥膝層14之整體厚度 二半導俨曰H ㈣易’甚而導致該第 J體;，b觸碰至第—焊、線13a或該第一焊線13a /、忒弟二坏線13b接觸產生短路等不良問題。 又氣子產品在積集化的趨勢，古 用功能，㈣隊Μ電子產品之使 承載板之i “ 品之高度，將半導體元件内嵌於 t之技*逐漸受到重視’而嵌埋於電路板之半導體元 件可為主動元件或被動元件。 本逡駚_ Μ Λ 什如弟2圖所不，係為習知將 2。=:，1埋於一電路板中之結構示意圖，於-承載板 一半至少一開口 200,該開口細係用以安裝 且2 卜而該半導體元件21具有-作用面2U， * Λ用面2la具有複數電極墊212，於該承載板2〇上表 以及δ亥半導體元件21之作用面^上形成一介電層 2二並於該介電層22上形成-線路層23,且該線路；23 八有複數導電結構231以連接該半導體元件21之電極整 212,依此增層方式形成多層線路層 以及介電層，俾以構成 一多層電路板。 一於上述衣私中，由於單一承載板20嵌埋單—半導 體=件21之電性功能有限，若要增加該承載板2G之電性 功能則必須增加贫屯道_ _ 曰加及+V體兀件21之數量，如此則必須在該 6 19375 1314031 有載2 2〇上開設複數個開口 200，但該承載板20之面積 展’、’、夬擴大，因而限制了承載板20電性功能的擴充與發 中5日^如何提供一種可將半導體元件嵌埋於電路板 之課:時強化其電性需求及功能’實已成為目前亟欲解決 【發明内容】 > 於以上所述習知技術之缺點，本發明之主要目的係 入〜 > 有+導體兀件之電路板疊接結構，係以壓 二：成多層線路之增層，俾得簡化製程及降低成本。 之電路又—目的係在提供—種嵌埋有半導體元件 仏接結構，以強化整體結構之電性需求及功能。 之電路再™目的係在提供—㈣埋有半導體元件 量生產,、结構，可縮短多層電路板製程時間以利於大 V元:^上述及其他目的’本發明所揭露之嵌埋有半導 體兀件之電路板疊接結構，係有^ 電路板之表面具有線路層，且;路板，各该 於該開口中嵌埋-具有複數電==至:-開口， 路層具有複數導電結構以電性連= = 線 形成於該至少—電路板之電性數導電凸塊’係 電黏著層，係形成於至少二電==面，，及至少-導 表面相對應之導電凸塊盘φ θ使至少二電路板 ^凸塊^性連接墊之間的導電黏著層透 19375 7 !314031 過壓合以形成導電通路，而形成 本發明之另—實施妙 、反間之電性連接。 於該些電路板之電性連接°墊表面:亥電凸魏係形成 相對應之導電凸塊與導 亥至少二電路板表面 以形成導電通路’而形成電路板；之:著層透過璧合 該電路板係為印刷電路板或了 ^連接。 黏者層係由黏著樹脂、硬化劑 ：土板，而該導電 該導電黏著層夾置於兩電路板方性 知，料電黏著層中之黏著_心，熱麼合 至電路板之電性連接墊及導 侍導電粒子移動 中藉由硬化劑固化，使該導電粒子:：’而在冷卻後過程 對應之電性連接塾與導電凸塊1(==在兩電路板相 板之兩導電凸塊（受屡處）之間而形 ）炊或是兩電路 連接兩疊接的電路板。 电k路，俾以電性 再者於該電路板未形成有導電黏 絕緣保護層，且該絕緣保 ：表面形成- 外露出該線路層作為電性連接塾=部=數個開孔，藉以 另或於該電路板未形成有導電^ 線路增層結構，且該線路增層結構中形：：表:形：-構以電性連接至該線路層複數個導電結 有電性連接墊，又㈣線路線路增層結構表面形成 層’且該絕緣保護層表面具有複數 == 路增層結構之電性連接墊。 Μ路出该線 此外’於本發明中係可在該電路板其中一表面之電性 19375 8 1314031 電?塊’而於另-表面僅為電性連接墊 將 第 層 电路板其中—表面之電性至另 表面，凸塊，並於兩電路板二=之 =传以此結構連續堆疊成多層電路板結構。" 構 口此，本發明之❹有半導體元件 係以壓合制妒、仓> ★也，· 吩败宜接結 故几社μ衣轾進仃稷數半導體元件及線路之增声，以 強化^體結構之電性需喪 k 本，並同時簡化製程及降低成
快速製程複數電路板，再利用壓合作業以 以㈣大接結構，藉以縮短多層電路板製程時間 【實施方式】 發明之實施方 示之内容輕易地 以下係藉由特定的具體實施例說明本 式热白此技藝之人士可由本說明書所揭 瞭解本發明之其他優點與功效。 [弟一實施例] 明 > 閱第3a及3b圖，係為本發明之嵌埋有半導體元 2之電路板疊接結構的第—實施例；㈣提供至少二例如 '、、、印刷電路板丨IC封裝基板之電路板30,該電路板3〇表 面具有線路層31’且該電路板3〇具有至少一開口％3，於 。亥開口 303中嵌埋有至少一半導體元件32，該半導體元件 32係可為CPU或記憶體（dram、srAm、SDRAM)等 主動元件，或係如電容（capacit〇rs)、電阻―）或 電感（inductors)等被動元件，該半導體元件32具有複數 電極墊32卜且該線路層31具有複數導電結構3ιι電性連 19375 9 1314031 接該半導體元件32之電極墊32卜又該線路層Μ具有 數電性連接墊312。再者於該至少一電路板3〇之電 >性連^ 墊312表面形成有導電凸塊33，該導電凸塊33係為鋼 (Cu)、銀（Ag)、金（Au)、鎳/金（Ni_Au)及鎳/鉛/金（川邛^ :斤：成群組之一者，如第3八圖所示；至少一導電點著； /係形成於至少兩電路板3〇之間，使兩電路板扣 7對應之導電凸塊33與電性連接塾312之 34藉由壓合以形成導電通路，俾 ：::層 •如第3B圖所示。 败川電性連接， 該導電黏著層34係由黏著樹脂 '硬 3:，之異方性導電膠，當該導電黏著層3=子 C間受熱並壓合時’該導電黏著層34中之辞著 树知軟化，使得導電粒子341移動 中之4者 =12及導電凸塊33表面’而在冷卻後:: 固化，使該導電粒子341聚集 中:由硬化劑 1電性連接墊312鱼導 屯路板30相對應之 所示;另或是兩電 形成有導電凸塊33,使該導電ς1連接墊312表面各 電粒子川聚集於兩㈣叙“:4於壓合過程中導 而形成導電通路，如第3Β，圖 \3之間（受壓處） 的電路板。 、俾以電性連接兩疊接 形成=緣有導電㈣層…面 個開孔露出該線路;緣3=^ 作為電性連接墊312之 19375 10 1314031 部分，於該電性連接執 (圖式t未表示）以虚冰Λ 、面則可再形成其它導電結構 [第二實施例])與外部電子裝置作電性連接。 凊簽閱第4圖，係為本發明之 路板疊接結構的第一盘 人里有半導體元件之電 在於該電路板3〇未 〜引只她例不同處 衣化成有導電黏著層 路增層結構36,該線路增層結構％ 之入表面形成一線 成於該介電層361上之線 有；|電層361、形 361中之導電杜;^ 36ι、 θ ，以及形成於該介電層 路板3〇表面的線路層31，又構363電性連接至該電 有複數電性連接塾364，且於 二 '-構36表面形成 一絕緣保護層35，該絕緣 ‘曰a結構36表面形成 35〇 , ffl ^ H ψ ^ …35表面具有複數個開孔 部分，於該電性連接墊表面:、1性連接整364之 (圖式中未表示）以與外部電子置;=成其它導電結構 ::ri”:r的外表面分別形成線路增二^ 俾以形成夕層電路板的結構。 [弟三實施例] 路J=5圖：！為本發明之嵌埋有半導體元件之電 在“電：板貫施例不意圖’與前述實施例不同處 由導電黏著層持續疊接，俾以構成-多 =路板結構；該電路板3g之以 夕 ==言形成有導電凸塊33,而另一表面僅露出該電 1生 連接塾312’而以一雷腺；in +中， 电路板30之電性連接墊312上的導電 19375 11 1314031 凸塊33疊接另一電路板3〇 路板30、30,之間央詈右一道/生連接墊312，亚於兩電 30,上再間隔一導’電黏著層34;又於該電路板 此類推，俾以連二成多，^ 史貝罐宜成夕層電路板結構。 成：=:該電路板3〇及3〇，，最外表面之線路層^ 成一絕緣保護層35，且續 ^ 。以 _線‘; _未表示）以與㈣==^^其#它導電結細式中 埋有半導二之電路㈣接結 塊，並盘另一心：=，電性連接墊上形成有導電凸 導接，二it 連接墊或導電凸塊相對應電性 路板之預埋有半導體元件，以在至少兩電 Γ:二電黏著層’該導電黏著層係由黏著樹 :著Γ火ΪΓ電粒子所組成之異方性導電朦，當該導電 路板之間受熱並厂堅合時，該導電黏著層 m兩電路板之電性連接墊與導電凸塊之 4 ’或兩电路板之導電凸塊與導電凸塊之間而形成導電通 路，俾以電性連接複數疊接電 的丰導〜杜妖且接的電路板及嵌埋於該電路板中 的+導^件，而可簡化製程及強化整體 及功能、，並可先藉由分別製程複數電路板，再利用壓= 業以快速开> 成電路板疊接έ士構萨 時間以利於大量生產細短多層電路板製程 惟以上所述之具體實施例，僅係用以例釋本發明之特 19375 12 1314031 點及功效，㈣心限定 内 範圍所涵蓋 【圖式簡單說明 本發明上揭之精神與技術料下，任=:二：未脫離 :完成之等效改變及修飾，均仍應為下述;; 圍所涵蓋。 曱明專利 第1圖係美國專利第5,323,〇6〇號 之多晶片半導體封《件剖面示意圖；^導體晶片 圖；第2圖係為習知餘半導體元件之電路板結構示意 第3A圖及第3B圖係本發明之嵌埋有半 路板it，—實施的分解剖視圖及組合剖視:意= 本發明之嵌埋有半導體元件之電路板叠接 、、、《構之另一組合剖視示意圖； =4圖係本發明之嵌埋有半導體元件之電路板疊接結 構的弟二貫施剖視示意圖；以及 構的第三實施剖視示意圖。 【主要元件符號說明 ] 1 半導體封裝件 12a 第一半導體晶片 12b 第二半導體晶片 13a 第一焊線 13b 第二焊線 14 膠層 19375 13 1314031 11 、 30 、 3(Γ、30，， 電路板 16 、 23 、 31 、 362 線路層 12 、 22 、 361 介電層 350 開孔 200 ' 303 開口 231 、 311 、 363
20 21、32 212 ' 321 • 21a 312 、 364 33 341 34 35 36 承載板 半導體元件 電極墊 作用面 導電結構 電性連接墊 導電凸塊 導電粒子 導電黏著層 絕緣保護層 線路增層結構 14 19375

Claims (1)

  1. 2. 3. 4. 5. 1314031 十、申請專利範圍： 一種嵌埋有半導體元件之電 至少二電路板，各該電路板::結構，係包括: 且該電路板具有至少— 表面具有線路層， 複數電極墊之半導體元二，，f該開口中嵌埋一具有 結構以電性連接該半導體元具有複數導電 具有複數電性連接墊； 墊，又该線路層 複數導電凸塊，係形成於玆、一 連接墊表面；以及 ' X v 一電路板之電性 至少一導電黏著層，係 間，使至少二電路板表面相對庫之導板之 :妾墊:間的導電黏著層得以透過Μ合以形成導^連 路，俾形成電路㈣七成導甩通 如申請專利範圍第1項之嵌=半導體一 疊接結構，其中，該半導體元::為 === 元件其中一者。 々王勡兀件及被動 ==專利_第丨項之嵌埋有半導 基板其中之—者。4路板㈣印刷電路板及1C封裝 範Γ1項之嵌埋有半導體元件之電路板 導：絕緣保護層，係形成於該電路板 右㈣ Γ黏著層之表面，且該絕緣保護層表面具 汗 以路出5亥線路層之電性連接墊。 如申請專利範圍第1項之嵌埋有半導體元件之電路板 19375 15 1314031 愛接結構，復包括有線路 板未形成有導電黏著声之著二4係、形成於該電路 形成有複數個導電結;:::連結構中 =增層結構表面形成有電性逹接墊路層’並於 申明專利範15第5項之嵌埋有半導 疊接結構，德句赵古妨 _體疋件之電路板 二;=，且該絕緣保護層表面具有開孔，以露出 °亥線路增層結叙f性連接墊。 如申請專利範圍第5項 疊接沾椹# , 入里有+導體7C件之電路板 成其中，該線路增層結構包括有介電層、形 導電結構。線路層，以及形成於該介電層中之 ，申請專利範圍第i項之嵌 疊接結構，Α中，彳鐙兀什之电路板 南丨旨 八 ^ ¥電黏著層係由黏著樹脂、硬化 9. ^泠電粒子組成之異方性導電膠。 如申晴專利範圍第丨 疊接結構，其中，牛之電路板 及鎳/鉛/金所組成群組之一。 鎳 種甘入埋有半導體兀件之電路板疊接結構，係包括： 且電路板，各該電路板之表面具有線路層， 複畫具有至少—開口 ’於該開口中鼓埋—具有 “墊之半導體元件’而該線路 結構以電性遠接兮主道挪—灿 ^ …：件之電極墊，又該線路層 〃、有複數電性連接塾； 19375 16 1314031 1 塾表:數凸塊，係形成於該些電路板之電性連接 =^ ♦電黏著層’係形成於至少二電路板之 間，使該至少-φt丄 凸塊之門沾、首 面相對應之導電凸塊與導電 路，俾^成2黏著層得以透過壓合以形成導電通 v成電路板間之電性連接。 U.如申請專利範圍第10項之嵌埋有半導，开杜+ + 疊接結構，A中，W 有丰導體70件之電路板 元件其中—者料㈣元件係為主動元件及被動 丨“以二圍第1。項之嵌埋有半導體元件之電路板 基板該電路板係為印刷電路板及Ic封裝 13.==利=二項，嵌埋有半導體元件之電路板 未形成有導電:著乂::護層，係形成於該電路板 有開別” 表面，且該絕緣保護層表面具 14 A 以路出該線路層之電性連接墊。 項之嵌埋有半導體元件之電路板 板未形成有導電:著::=、结構，係形成於該電路 形成有複數個導電且該線路增層結構中 該&π+、，s ，電、、、°構以電性連接至該線路層，並;^ 15 ，路增層結構表面形成有電性連接墊。 .σ申凊專利範圍第14項之嵌 疊接結構，復包括導體70件之電路板 層社;、G、、/、6蒦層，係形成於該線路增 構表面，且該絕緣保護層表面具有開孔，以露出 19375 17 1314031 該線路增層結構之電性連接墊。 16·如申請專利範圍第14項之嵌 疊接結構，1中m 牛蜍體兀件之電路板 成於該介電層:之i:T層結構包括有介電層、形 導電結構。《線路層’以及形成於該介電層中之 17. t申請專利範圍第10項之嵌埋有半導體元侔 豐接結構，其中，該導電”層係由=之電路板 劑及導電粒子組成之異方性導電谬。树脂、硬化 18. 如申請專利範圍帛10項之嵌埋有二 疊接結構，其中，該導電凸塊件八之電路板 及鎳/錯/金所組成群組之一。 銀、正、鎳/金 19375 18
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