TWI313036B - Multi-anneal process - Google Patents

Description

1313036 _Case No. 92113648_年月曰曰 Revision_5. Description of the Invention (1) Technical Field of the Invention The present invention relates to a Mult i-anneal process, and more particularly to a semiconductor suitable for use in a semiconductor Multiple annealing process for copper processes. [Prior Art] Under the circumstances that traditional aluminum metal wires cannot break through the bottleneck, after years of research and development, copper wires have become the mainstream of semiconductor materials. Since copper has a lower resistance than the previous one, it can carry a large current on a small area, allowing manufacturers to produce chips with faster speeds, more dense circuits, and improved performance by about 30% to 40%. . In addition, since the electro-migration ability of copper is better than that of I, it can reduce the electromigration effect, thereby improving the reliability of the wafer. Please refer to the flow chart of the conventional copper process with a single annealing step as shown in FIG. First, a substrate is provided in which the substrate has been formed into a portion of a semiconductor component in a prior art process. Next, as shown in step 10, a copper film is formed on the substrate, wherein the copper film can be a via (Via) and a metal layer (or a contact layer and a metal layer) in the dual damascene process, and step 1 0 can be achieved, for example, by an electrochemical clock (ECC) method. Since the copper film is still in an unstable state after the step of forming the copper film described above, it is necessary to apply a heat treatment process to the copper film, whereby the crystal grain growth of the copper film tends to be stable. Therefore, the substrate having the copper film is subjected to an annealing step as shown in step 20, wherein the annealing step is generally performed in the same reaction chamber as described above for electrochemical plating in the presence of (I η - situ ) get on. Then, as shown in step 40, the surface of the copper film is subjected to chemical mechanical polishing (CMP) to thereby make the copper film

Page 6 1313036 Case No. 92113648_月日_5, invention description (2) Before the surface reaches the required flatness, the copper process with step 20 in the above figure 1 has become the standard process. However, the copper process as shown in Fig. 1 can provide the copper film with the desired resistance to electron migration. However, as for the stress of the copper film, the phenomenon of "Stress M] l grat i on is shown in Fig. 1. The copper process shown does not smoothly suppress the stress of the copper film* Φ migration phenomenon 5, which leads to a decrease in the resistance of the dielectric layer of the stress migration test and a decrease in the yield. Therefore, it is necessary to find a solution. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multiple annealing process that mitigates the stress»St migration phenomenon. Another aspect of the present invention is to provide a multiple annealing process to reduce stress migration. The rate of increase of resistance 〇 another one of the present invention provides a multiple annealing process by which the yield can be improved and stabilized. The above-mentioned g of the present invention is proposed as a multiple annealing process, which is a preferred embodiment of the present invention. In this example, the multiple annealing process includes at least the following steps. First, a substrate is provided, and then a copper film is formed to cover the substrate, and the substrate is subjected to a plurality of annealing steps. In addition, the plurality of annealing steps include at least one of the first annealing steps and the first step. An annealing step, wherein the temperature and time of the first annealing step are 50 ° C to 400 ° C and 10 seconds to 1 000 ° 5 respectively, and the temperature and time of the second annealing step are 1 ( ) ( TC to 50 (TC and 1 minute to 10 hours, the temperature and time of the other first annealing step and the second annealing step may be as described above. In a preferred embodiment of the invention, the temperature of the first annealing step may be Less than the temperature of the second annealing step; and the time of the first annealing step may be less than the time of the second annealing step

1313036 Case No. 92113648 月 Amendment V. Inventive Note (3), the first annealing step and the second annealing step further include cooling the substrate to room temperature. Therefore, the application of the present invention can alleviate the phenomenon of stress migration. Furthermore, the application of the present invention can reduce the rate of increase in the resistance of the stress migration test interposer. Furthermore, the application of the present invention can improve the yield and be relatively stable. [Embodiment]

This invention relates to a multiple annealing process suitable for use in a semiconductor copper process. Please refer to FIG. 2 for a flow chart of a copper process having multiple annealing steps in accordance with a preferred embodiment of the present invention. First, a substrate is provided in which the substrate has been partially formed into a semiconductor device in a prior art process. Next, as shown in step 110, a copper film is formed on the substrate, wherein the copper film can be a dielectric layer and a metal layer (or a contact layer and a metal layer) in the dual damascene process, and the step 1 1 0 can For example, electrochemical plating is achieved. Next, as shown in step 120, the substrate having the copper film is subjected to a first annealing step, wherein the first annealing step is generally performed in the same reaction chamber as described above for performing electrochemical plating. As for the temperature and time required for performing the first annealing step of this step 120, for example, 50 ° C to 400 ° C and 10 0 to 1 000 seconds, respectively. Then, the temperature of the above substrate was lowered to room temperature. The process of lowering the temperature of the substrate to room temperature can be continued in the presence of the substrate or by moving the substrate out of the reaction chamber for performing the first annealing step of step 120. Next, as shown in step 130, the substrate is subjected to a second annealing step, wherein the temperature and time required for performing the second annealing step of the step 130 are, for example, 1 0 0 ° C to 5 0 0 °, respectively. C and 1 minute to 10 hours. As for this second annealing

Page 8 1313036 _ Case No. 92Π3648_年月曰 修正 Amendment _ V. Invention Description (4) The method used in the step can be, for example, a thermal pad (Η 〇 t P 1 a t e ). In addition, the temperature and time of the first annealing step and the second annealing step may be as described above. In a preferred embodiment of the invention, the temperature of the first annealing step may be lower than the temperature of the second annealing step; and the first annealing The time of the step may be less than the time of the second annealing step. The second annealing step of the above step 130 is a feature of the present invention. By the second annealing step of the step 130, the phenomenon of stress migration in the copper film can be alleviated, thereby reducing the increase rate of the stress migration test interposer resistance, and thereby improving the yield. However, it is not limited in the present invention to use only two annealing steps. It is within the scope of the present invention to perform at least two annealing processes after forming a copper film on the substrate. That is, the present invention can be as shown in FIG. 2, after adding another annealing process after the standard single annealing process, or adding at least two annealing processes after the standard single annealing process, all of which are claimed in the present invention. Within the scope of protection. Then, as shown in step 140, the surface of the copper film is subjected to chemical mechanical polishing so that the surface of the copper film achieves the desired flatness. Please refer to the relationship between the dielectric resistance offset and the probability of occurrence of the multiple annealing process of the present invention, the conventional standard single annealing process, and the single annealing process for increasing the thermal budget, as shown in FIG. As described above, with the multiple annealing process of the present invention, the stress migration phenomenon in the copper film can be effectively suppressed, thereby reducing the increase in the dielectric resistance caused by the long-term stress migration. This effect of the present invention is apparent from Fig. 3. The legend A in Fig. 3 represents the corresponding data of the multiple annealing process of the present invention; the legend B represents the corresponding data of the conventional standard single annealing process; and the legend C represents the corresponding data of the single annealing process which increases the thermal budget, wherein the legend The corresponding increase of C

1313036 _ Case No. 92113648_年月曰 Amendment _ V. Description of the invention (5) The total annealing energy of the single annealing process of the thermal budget is approximately equal to the total annealing energy of the multiple annealing process of the present invention corresponding to the legend A. As for the diagonal coordinate in Figure 3, the dielectric resistance offset (in %), and the ordinate is the probability of occurrence of a certain dielectric resistance offset (in %). In addition, the data in Figure 3 was obtained for a standard stress-migration test of 1 〇 〇 〇 for the Ke 1 v i η single-layer test structure commonly used in the semiconductor industry. It can be clearly seen from Fig. 3 that the multiple annealing process represented by the legend 具有 has the best test results, and for the probability of occurrence of about 100%, the dielectric resistance of the multiple annealing process represented by the legend A is biased. The shift ratio is reduced by about 10% from the dielectric resistance offset of the other two annealing processes represented by Legend B and Legend C. Please refer to the multi-anneal process of the present invention illustrated in FIG. 4 and the yield comparison chart of the conventional standard single annealing process. The yield data of the multiple annealing process of the present invention and the conventional standard single annealing process are shown in Fig. 4, respectively. As is apparent from Fig. 4, the conventional standard single annealing process has a relatively large yield distribution, and the multiple annealing process of the present invention has a relatively stable yield distribution. 5 %。 The average yield of the standard single-annealing process in Figure 4 is about 49. 9%, and the average yield of the multiple annealing process of the present invention is about 61.5 %. That is, the multiple annealing process of the present invention can increase the yield by at least about 10 °/ over the conventional standard single annealing process. . Therefore, the present invention does provide a relatively stable and high yield. It will be apparent from the above-described preferred embodiments of the present invention that the application of the present invention can alleviate the phenomenon of stress migration. Furthermore, it is apparent from the above-described preferred embodiments of the present invention that the application of the present invention can reduce the rate of increase in the resistance of the stress migration test interposer. Furthermore, it can be seen from the above preferred embodiments of the present invention that the application of the present invention can be utilized

Page 10 1313036 _ Case No. 92113648_年月曰 修正 Amendment _ V. Invention Description (6) Improve the yield and be more stable. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 1313036 Case No. 92113648 月 Amendment Simple description of the drawing Fig. 1 is a flow chart showing a conventional copper process with a single annealing step. 2 is a flow chart showing a copper process having multiple annealing steps in accordance with a preferred embodiment of the present invention. Fig. 3 is a graph showing the relationship between the amount of interlayer resistance displacement and the probability of occurrence of the multiple annealing process of the present invention, the conventional standard single annealing process, and the single annealing process for increasing the thermal budget. Figure 4 is a graph showing the yield comparison of the multiple annealing process of the present invention and the conventional standard single annealing process.

[Simplified Description of Component Symbols] 10: Forming a Copper Film on a Substrate 20: Performing an Annealing Step 40: Performing Chemical Mechanical Polishing 110: Forming a Copper Film on a Substrate: Performing a First Annealing Step 1 3 0: Performing Second annealing step 140: performing chemical mechanical polishing A: multiple annealing process

B: Standard single annealing process C: Single annealing process to increase thermal budget

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Claims (1)

Π Wt 修修王戍E/Supplement_Case No. 92113648_年月日日 Revision_6. Patent Application Scope' 1. A multi-anneal process, including at least: providing a substrate; forming a copper The film covers the substrate; and the substrate is subjected to a plurality of annealing steps, the annealing step comprising at least one of a first annealing step, a cooling step and a second annealing step, wherein the cooling step is The substrate is cooled to a room temperature, the temperature of the first annealing step is 50 ° C to 400 ° C, and the time of the first annealing step is 10 seconds to 1000 seconds, and the second annealing step is performed. The temperature is from 10 ° C to 500 ° C, and the time of the second annealing step is from 1 minute to 10 hours. 2. The multiple annealing process of claim 1, wherein the step of forming the copper film uses an electrochemical bond (ECP). 3. The multiple annealing process of claim 1, wherein the second annealing step uses a hot plate. 4. The multiple annealing process of claim 1, wherein the temperature of the first annealing step is less than the temperature of the second annealing step. 5. The multiple annealing process of claim 1, wherein the time of the first annealing step is less than the time of the second annealing step. Page 13 1313036 _ Case No. 92113648 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Chemical Mechanical Polishing (CMP) step. 7. A multiple annealing process comprising, at least: providing a substrate; forming a copper film over the substrate; performing a first annealing step on the substrate; performing a cooling step on the substrate, the cooling step Cooling the substrate to a room temperature; and performing a second annealing step on the substrate; wherein the temperature of the first annealing step is less than the temperature of the second annealing step, and the time of the first annealing step is less than the second The time of the annealing step. 8. The multiple annealing process of claim 7, wherein the step of forming the copper film is by electrochemical plating. 9. The multiple annealing process of claim 7, wherein the temperature of the first annealing step is from 50 ° C to 400 ° C. 10. The multiple annealing process of claim 7, wherein the first annealing step is from 10 seconds to 1 000 seconds. 11. The multiple annealing process as described in claim 7 of the patent application, wherein Page 14 1313036 _ Case No. 92Π3648_年月日日 Revision _ 6. Patent application scope, the temperature of the second annealing step is 1 0 0 °C to 500 °C. 12. The multiple annealing process of claim 7, wherein the second annealing step is from 1 minute to 10 hours. 13. The multiple annealing process of claim 7, wherein the second annealing step uses a thermal pad. 14. The multiple annealing process of claim 7, wherein the second annealing step further comprises subjecting the substrate to a chemical mechanical polishing step. Page 15 1313036 ________ Case No. 92113648_年月曰 Article 正 _ IV. Abstract of Chinese Invention (Invention Name: Multiple Annealing Process) A multi-anneal process. The multiple annealing process of the present invention includes at least the following steps. First, a substrate is provided. Next, a copper film covering substrate is formed. The substrate is then subjected to several annealing steps. In addition, the plurality of annealing steps include at least one of the first annealing step and the second annealing step, wherein the temperature and time of the first annealing step are 50 ° C to 400 ° C and 1 0 respectively. The second to 1000 seconds, and the temperature and time of the second annealing step are from 1 0 0 ° C to 500 ° C and 1 minute to 10 hours, respectively. V. (1) The representative figure of this case is: _____ diagram (2), the representative symbol of the representative figure of this case is a simple description: 110: Forming a copper film 120 on the substrate: performing the first annealing step 130: Second annealing step 140: performing chemical mechanical polishing. V. English abstract (invention name: MULTI-ANNEAL PROCESS) The present invention includes: providing a substrate; forming a copper film on the substrate; and proceeding with a plurality of anneal steps to the substrate. further, the plurality of anneal steps comprises a first anneal step And a second anneal step proceeded sequentially, the temperature and time of the first anneal step Page 2 1313036 _ Case No. 92113648_年月日日_魅 Six, designated representative map Page 4