TW502391B - Fabrication method for doped copper interconnect - Google Patents

Abstract

A fabrication method for doped copper interconnect is provided to eliminate additionally formed copper protection layer or etch stop layer and diffusion barrier layer in copper interconnect fabricating process. Interconnect is formed by filling grooves or via holes or dual damascene structure with copper metal doped by at least one of the following elements: magnesium, silver, titanium, zirconium, tin, zinc, or carbon. Annealing the copper metal for diffusing the doping element into the surface of copper metal and to form an oxide layer that serves as copper protection layer, etch the stop layer and diffusion barrier layer. Thus, copper metal oxidation and photoresist poisoning are prevented and process is simplified.

Description

502391

Field of the Invention: The present invention relates to a method for manufacturing interconnects, particularly a method for manufacturing copper interconnects with doping to prevent steel oxidation, poisoning, and increase adhesion between dielectric layers. And delay effect (RC delay effect). Relevant technical description: In very large accumulation circuits (ULSI), metallization is an important step, in which the interconnects play the role of electrically connecting various components in the circuit, so it deeply affects the electrical characteristics of the components and Function of components. In today's interconnecting process, copper metal has become a material of great interest due to its low resistivity and resistance to electron migration (EM), which is suitable for deep submicron integrated circuits. However, 'copper metal is very easy to oxidize and has a high diffusion coefficient. After contacting with silicon or silicon dioxide, it will quickly diffuse into the substrate and cause adverse effects on the electrical properties of the device. Therefore, in the conventional copper interconnect manufacturing method, a diffusion barrier layer and a protective layer are formed before and after the interconnect is formed. In order to further understand the background of the present invention, a cross-sectional schematic diagram of a process for forming a copper interconnect by a conventional technique is described below with reference to FIGS. First, referring to FIG. 1a, a first dielectric layer 102 is formed on a semiconductor substrate 100. Then, a trench 103 is formed on the first dielectric layer 102 by a lithography etching technique. Subsequently, a diffusion barrier layer 104 such as titanium nitride (TiN) or tantalum nitride (TaN) is formed on the inner wall of the trench 103.

502391 V. Description of the invention (2) Next, please refer to FIG. 1b, and fill copper 106 in the trench 103 having the barrier layer 104 formed thereon, and above the trench 103 and the first reference A protective layer 108, such as silicon nitride (SiN) or silicon carbide (SiC) ', is formed on the electrical layer 102 to prevent copper from oxidizing and at the same time as an etch stop layer in subsequent processes. Finally, please refer to FIG. 1c, and a second dielectric layer 110 is formed on the protective layer 108 for subsequent processes. Since the first and second dielectric layers and U 0 are separated by the protective layer 108, the dielectric constant of the entire device is increased, that is, increasing the capacitance value of the device causes the time delay effect to rise and the dielectric layers 102 and 110 to increase. The adhesion between them is poor, and leakage current is easy to occur. Furthermore, in the subsequent process, the protective layer 108 may easily contaminate the second dielectric layer 110 and indirectly cause photoresistance poisoning. In addition, in order to solve the problem caused by the protective layer 108, Taiwan Patent No. 426964 discloses a method for manufacturing a copper alloy interconnect, by forming adjacent copper alloy layers on the upper and lower surfaces of pure copper, and then Annealing is performed to form copper alloy interconnects, so there is no need to use a protective layer to avoid problems caused by them. However, the manufacturing method still needs to form a diffusion barrier layer and an adjacent copper alloy layer, and the manufacturing process is more complicated. In view of this, the present invention provides a method for manufacturing a copper interconnect with doping, 'using copper metal with a doping element as the interconnect material, and applying an annealing treatment to diffuse the doped element to the copper. An oxide layer having the functions of a protective layer, an epitaxial stop layer and a diffusion barrier layer is formed on the metal surface. It can effectively simplify the process, reduce the time delay effect, and prevent photoresistance and component degradation. Summary of invention:

502391 V. Description of the invention (3) The purpose of the present invention is to provide a doped copper to avoid photoresist poisoning and reduce the capacitance value of the device, so as to reduce the ′ ′ ίίί side. The objective of the interfacial delay effect method is to provide a method for manufacturing steel interconnects with doping to simplify the manufacturing process and avoid the damage of the deep diffusion characteristics of copper atoms. Electrically increasing k to 70 pieces of electrical fabrication; ... The present invention provides a step of doping steel interconnects: forming on the semiconductor substrate-"-,-" the electrical layer has a trench or dielectric Layer hole or dual damascene structure ^ on the first dielectric layer and inside the trench or via hole or dual damascene structure & insert copper metal with doping elements as interconnects; perform an annealing treatment on the copper metal To form an oxide layer on the surface of the copper metal; and to remove the copper metal formed with the oxide layer by etching to expose the surface of the first dielectric layer, thereby leaving the copper metal in the trench and forming the above on the surface of the copper metal at the same time An oxide layer. After exposing the surface of the first dielectric layer, the method further includes forming a second dielectric layer on the top surface of the copper metal on which the oxide layer is formed on the first dielectric layer and in the trench for subsequent The manufacturing process. The doping element is selected from at least one of magnesium, silver, titanium, hafnium, tin, carbon, and carbon, and the oxide layer is formed by the reaction of the doping element with oxygen. In addition, the annealing treatment is performed under nitrogen. Under forming gas environment with lice gas The temperature and time are in the range of 150 to 450 ° C and the range of 30 to 120 minutes, respectively.

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0503-6685TWF; TSMa〇〇i.〇541; spin.ptd p. 6 ^ 02391

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes specific embodiments in combination with the accompanying drawings in detail as follows: Figures 1a to 1c show the conventional knowledge. Schematic diagram of the process surface for forming copper interconnects by technology; ° Figures 2a to 2d are schematic cross-sectional views of the process of doped steel wiring according to an embodiment of the present invention; Graph of the change of sheet resistance Rs after annealing of magnesium and copper. [Symbol description] Instrument 100, 200 ~ semiconductor substrate; 102, 202 ~ first dielectric layer; 103, 203 ~ trench; 104 ~ diffusion barrier layer; 106 ~ copper metal; 108 ~ etch stop layer 110, 206 ~ second dielectric layer; 204 ~ doped copper metal; 204a ~ oxide layer. Detailed description of the preferred embodiment: The manufacturing method of the doped interconnects according to the embodiments of the present invention will be described below with reference to Figs. 2a to 2d.

502391

First, referring to FIG. 2a, a semiconductor substrate 200, such as a silicon wafer, is provided. A plurality of semiconductor elements are formed on the substrate 200. To simplify the illustration, only a flat substrate is shown here. Next, a first dielectric layer 202 is formed on the semiconductor substrate 200, such as a silicon dioxide layer or a low dielectric constant material layer. Subsequently, a trench 203 is defined on the first dielectric layer 202 and the surface of the substrate 200 is exposed by the conventional lithography technique. " Next FIG. 2b 'uses physical vapor deposition (PVD) to form a copper metal 204 with doping elements on the first dielectric layer 202 and in the trench 203 to As an interconnect. In this embodiment, the target used for PVD is a copper alloy target, that is, the copper target is doped with other elements, such as selected from magnesium (Mg), silver (Ag), and titanium (Ti ), Hammer (Zr), tin (Sn), zinc (zn), carbon (C) and the like. In this embodiment, the preferred doping element is magnesium. In addition, a copper plating method may be used instead of the PVD method, that is, the doped element is placed in a plating solution for electroplating. After the doped copper metal 204 is formed, an annealing treatment is performed on the copper metal 204 under an environment of nitrogen and hydrogen ^ forming gas and a temperature in the range of 150 to 45 °. Among them, the duration is in the range of 30 to 120 minutes. 0

Next, please refer to Figure 2c. After the copper metal 204 has undergone the annealing process, the doped elements inside it will diffuse to the surface and react with the surrounding oxygen to form an oxide layer 204a. The copper metal 2 There are also copper alloy grains (not shown) inside the 〇4. As mentioned earlier, since pure copper is very easy to oxidize and easily diffuse into the silicon dioxide layer or stone layer,

502391

A protective layer is formed over the copper layer in the connection system, and at the same time, it is used as an etching layer / cutting layer to form an expansion layer. In reality, 'because of the formation of the oxide layer 204a', it can replace the above protective layer and diffusion resistance. Barrier layer, @this has the original efficacy of these two layers and simplifies the manufacturing process ... b, steel alloys have the function of resisting electron migration (EM).

Next, referring to FIG. 2D, the chemical metal polishing (CMp) method is used to remove the copper metal 204 having the oxide layer 20 4a formed thereon until the surface of the first dielectric layer 202 is exposed, so that the trench is formed in the trench. Copper metal 204 is left in 203, and an oxide layer 204a is formed on the surface of the copper metal. At this time, the inventor found that the oxide layer 20 ″ also has the function of a stop layer without affecting the progress of the CMP process. Therefore, according to the manufacturing method of the copper interconnects of the present invention, there is no need to form an additional etching stop layer. The annealing process can also be performed after chemical mechanical polishing, as shown in Figure 2c, to form an oxidation protection layer 204a. Compared with the conventional technology, it not only simplifies the manufacturing process, but also prevents The etching stop layer causes photoresist poisoning in subsequent processes and increases the capacitance value of the device to increase the time delay effect. Finally, a copper metal 204 having an oxide layer 20 4a is formed on the surface of the exposed first dielectric layer 202 and in the trench 203. A second dielectric layer 206 is formed on the upper surface for subsequent processes. This oxide layer 204a can prevent chemical reactions, such as oxidation, on copper when depositing the upper borrow layer material. In addition, because the second dielectric layer 206 It is directly formed on the first dielectric layer 202, which is different from the etching stopper layer in the conventional technology. Therefore, it has better adhesion and can improve the generation of leakage current.

0503-6685TW; TSMC2001-0541; Spin.ptd Page 9 502391 V. Description of the invention (7) Furthermore, compared to the line, the present invention does not require an amount and can effectively simplify the manufacturing process. In addition, please refer to copper metal after annealing. It can be seen that the use of doped sheet resistors will be close to pure response. Although the above embodiments can be understood in the formation of a dual damascene manufacturing method. Although the present invention has limited the present invention, within any god and scope, when the attached application is attached, the application of another known technology using copper alloy as the internal A diffusion barrier layer and an adjacent copper alloy layer are formed outside. FIG. 3 is a graph showing the relationship between the sheet resistance and the resistance after the treatment of pure copper, doped hammer, and magnesium. After the annealing process, the steel will not cause a bad effect on the electrical properties of the device = the dielectric layer with grooves is used as an example, but the layer = (via ho 1 e) or a dual damascene structure) The electrical layer can also be disclosed as above using the embodiment of the interconnection system of the present invention, but it is not intended to change the artist's skills without departing from the refined decoration of the present invention. Therefore, the scope of protection of the present invention is defined as $ . Due to

Claims (1)

502391 VI. Application for Patent Scope 1. A method for manufacturing doped copper interconnects, including the following steps: forming a first dielectric layer on a semiconductor substrate, wherein the upper coating layer and the / 1 electrical layer have grooves; Trench or interlayer hole or dual damascene structure; firstly filling copper metal with doping element on the first dielectric layer and the trench or the interlayer hole J damascene structure as described in the above Subjecting the copper metal to an annealing treatment on the surface of the copper metal to form an oxide layer; and The neodymium etch removes the steel metal on which the oxide layer is formed to expose the surface of the first dielectric layer, thereby leaving the copper metal in the trench, and simultaneously forming the oxide layer on the surface of the copper metal. 2. The manufacturing method of doped copper interconnects as described in item 1 of the scope of the patent application, wherein after the surface of the first dielectric layer is exposed, the method further includes the first dielectric layer and the trench. A second dielectric layer is formed on the upper surface of the steel metal in which the oxide layer is formed to perform subsequent processes. 3. The manufacturing method of doped copper interconnects as described in item 1 of the scope of the patent application, wherein said doping element is selected from at least one of magnesium, silver, titanium, hafnium, tin, zinc, and carbon. 4. The manufacturing method of doped copper interconnects as described in item 1 of the scope of patent application, wherein the formation of the above copper metal is one of physical vapor deposition method and bond copper method. 5. The manufacturing method of doped copper interconnects as described in item 1 of the scope of the patent application, wherein the annealing temperature is in the range of 150 to 450 ° C. 0 0503-6685BfF; TSMC2001-0541; spin.ptd Page 11 VI. Patent Application Range 6 · The manufacturing method of doped copper interconnects as described in item 1 of the patent application range, where the annealing time is as described above Fan Park in 30 to 120 minutes. • The manufacturing method of doped steel interconnects as described in item 1 of the scope of the patent application, wherein the annealing treatment is performed under a forming atmosphere of nitrogen and hydrogen. Clothing 8. The method for manufacturing a doped steel interconnect as described in item 1 of the scope of patent application, wherein the above-mentioned oxide layer is used as a diffusion barrier layer. 9. The manufacturing method of doped copper interconnects as described in item 1 of the scope of the patent application, wherein the oxide layer is used as an etching stop layer. IO · The method for manufacturing steel interconnects with doping as described in item 2 of the scope of the patent application, wherein the above-mentioned oxide layer is a reaction form of the above-mentioned doping element and oxygen1. A method for manufacturing a hybrid copper interconnect Including the step of forming a first dielectric layer on a substrate, wherein the first dielectric reed has a trench or a via hole or a dual damascene structure; θ is one of a physical vapor deposition method and a copper electroplating method In the above and the above-mentioned trenches or the above-mentioned interlayer holes or the above-mentioned double damascene structure, copper elements are used as interconnects, wherein the dopant is selected from magnesium, silver, titanium, hafnium, tin, and silicon. At least one pair of copper and carbon metal is annealed to form an oxide layer on the surface; 4 The surface metal is removed at a later time to expose the copper metal formed with the oxide layer to expose the above 0503-6685TW; l.〇541; spin.ptd Page 12 502391 VI. Patent application scope The surface of the first dielectric layer, thereby leaving the copper and gold in the trench and forming the oxide layer on the surface of the copper metal; On the first dielectric layer Σ within the groove to a rear surface of the second dielectric layer is formed on said copper metal of the oxygen has to be: Cheng. ≪ I 12. The manufacturing method of doped copper interconnects as described in item 丨 丨 of the patent application scope, wherein the annealing temperature is in the range of i 5 0 to 4 5 0. & 13. The manufacturing method of doped copper interconnects as described in item Π of the patent application range, wherein the annealing time is in the range of 30 to 120 minutes. 14. The method for manufacturing doped copper interconnects as described in item U of the scope of the patent application, wherein the annealing treatment is performed in a nitrogen and nitrogen environment. 15. The manufacturing method of doped copper interconnects as described in item u of the patent application, wherein the above-mentioned oxide layer is used as a diffusion barrier layer. 16. The manufacturing method of doped copper interconnects as described in item 丨 丨 of the scope of the patent application, wherein the above-mentioned oxide layer is used as an epitaxial stop layer. »17. · The manufacturing method of doped copper interconnects as described in Item 丨 丨 of the declared patent scope, wherein the above-mentioned oxide layer is formed by the reaction of the above-mentioned impurity element and oxygen to form 0.