CN1243377C - Method for making mixed copper internal connection stracture - Google Patents
Method for making mixed copper internal connection stracture Download PDFInfo
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- CN1243377C CN1243377C CN 02105018 CN02105018A CN1243377C CN 1243377 C CN1243377 C CN 1243377C CN 02105018 CN02105018 CN 02105018 CN 02105018 A CN02105018 A CN 02105018A CN 1243377 C CN1243377 C CN 1243377C
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Abstract
The present invention relates to a method for manufacturing a doped copper interconnection structure. The present invention is used for omitting a copper protective layer or an etch stop layer or a diffusion barrier layer additionally formed in the manufacture process of the copper interconnection structure. First, metallic copper doped with at least one kind of elements of magnesium, silver, titanium, zirconium, stannum, zinc and carbon is filled into a groove or a dielectric hole or a double-embedded structure to be used as the interconnection structure; subsequently, the metallic copper carries out anneal treatment, and the doped element is diffused to the surface of the metallic copper to form an oxide layer used as the copper protective layer, the etch stop layer and the diffusion barrier layer. The present invention prevents the metallic copper from being oxygenized, prevents a light resistor from being poisoned, and simplifies the steps of the manufacture process.
Description
Technical field
The present invention relates to a kind of manufacture method of inline structure, particularly relate to a kind of manufacture method of the inline structure of copper of tool doping, be used to prevent that copper oxidation, photoresistance from poisoning, increasing the adhesive force (adhesion) between the dielectric layer and reducing time delay effect (RC delay effect).
Background technology
In very lagre scale integrated circuit (VLSIC) (ULSI), metallization (metallization) is an important step, wherein inline structure (interconnect) is played the part of the role who electrically connects each assembly in the circuit, so it influences the electrical characteristics of assembly and the performance of assembly function deeply.In the inline now structure fabrication process, because metallic copper has low-resistivity, (electronmigration, EM) height are applicable to the integrated circuit of deep-sub-micrometer, so become the inline structural material of attracting attention in anti-electron transfer.
Yet metallic copper is very easy to oxidation and diffusion coefficient height, and understands rapid diffusion after silicon or silicon dioxide contacts and enters base material and cause the electrical harmful effect of assembly.Therefore in the manufacture method of the inline structure of copper of known technology, can form diffusion shielding layer and protective layer respectively forming before and after the inline structure.Be further to understand background of the present invention, below with reference to the manufacturing process generalized section of Fig. 1 a to the inline structure of 1c explanation known technology formation copper.
At first, please refer to Fig. 1 a, in semiconductor substrate 100, form one first dielectric layer 102.Then, utilize photolithography techniques on first dielectric layer 102, to form a groove 103.Subsequently, form a diffusion shielding layer 104, for example titanium nitride (TiN) or tantalum nitride (TaN) at groove 103 inwalls.
Next; please refer to Fig. 1 b; in the groove 103 that is formed with screen 104, insert metallic copper 106 and forming a protective layer 108 above the groove 103 and on first dielectric layer 102; for example silicon nitride (SiN) or carborundum (SiC) are to prevent the copper oxidation and simultaneously as the etch stop layer in the follow-up manufacturing process.
At last, please refer to Fig. 1 c, on protective layer 108, form one second dielectric layer 110 to carry out follow-up manufacturing process.Since between first and second dielectric layer 102 and 110 across protective layer 108; therefore can make the dielectric constant of assembly integral body increase; the capacitance that also promptly increases assembly causes the tack between the rising of time delay effect and dielectric layer 102 and 110 relatively poor, and leakage current generating is easily arranged.Moreover in follow-up manufacturing process, this protective layer 108 easily might pollute second dielectric layer 110 and then cause photoresistance to poison indirectly.
In addition; for solving the problem that protective layer 108 is caused; the Announcement Number of Taiwan patent discloses the inline structure making process of an Albatra metal-No. 426964; utilization forms the copper alloy layer of adjacency on the upper and lower surface of fine copper; impose annealing in process again; with the inline structure of formation copper alloy, thereby need not to use the problem of protective layer to avoid it to cause.Yet, still need form the copper alloy layer of diffusion shielding layer and adjacency in its manufacture method, manufacturing process is comparatively complicated.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of the inline structure of copper of tool doping, to avoid photoresistance to poison and to reduce the assembly capacitance and then the time delay effect is reduced.
Another purpose of the present invention is to provide the manufacture method of the inline structure of copper that a kind of tool mixes, to simplify manufacturing process and to avoid copper atom to diffuse to the infringement that dielectric layer causes the electrical component characteristic.
The object of the present invention is achieved like this:
The invention provides a kind of manufacture method of the inline structure of copper of tool doping; with the metallic copper of tool doped chemical as inline structural material; and apply an annealing in process again form so that doping elements diffuses to copper surface have protective layer, the oxide layer of etch stop layer and diffusion shielding layer effect.Can effectively simplify manufacturing process, reduce the time delay effect and prevent that photoresistance from poisoning and component characteristic descends.
The manufacture method of the inline structure of copper that a kind of tool mixes comprises the following steps: to form one first dielectric layer in the semiconductor substrate, and wherein first dielectric layer has groove or interlayer hole or dual-damascene structure; On first dielectric layer and in groove or interlayer hole or the dual-damascene structure, insert metallic copper, with as inline structure with doped chemical; Metallic copper is implemented an annealing in process, to form an oxide layer at copper surface; And the etching removal is formed with the metallic copper of oxide layer to expose the first dielectric layer surface, the next metallic copper that stays, and while described oxide layer of formation on described copper surface in groove.
Moreover, after exposing the first dielectric layer surface, also be included on first dielectric layer and groove in be formed with oxide layer the metallic copper upper surface form one second dielectric layer, to carry out follow-up manufacturing process.Wherein, doped chemical is selected from least a in magnesium, silver, titanium, zirconium, tin, zinc, the carbon, and oxide layer is described doped chemical and formation that oxygen reacts.In addition, described annealing in process ties up under shaping gas (forming gas) environment of nitrogen and hydrogen carries out, and temperature and time is respectively in 150 to 450 ℃ scope and 30 to 120 minutes scope.
Description of drawings
Fig. 1 a is the generalized section of the inline structural approach of known technology copper to 1c;
Fig. 2 a is the generalized section of the inline structure of copper that tool mixes according to the present invention to 2d;
Fig. 3 be the copper of fine copper and doping zirconium, magnesium after annealing in process, the variation relation figure of sheet resistor Rs.
Embodiment
For purpose of the present invention, feature and advantage can be become apparent,, and in conjunction with the accompanying drawings, be described in detail below especially exemplified by preferred embodiment:
Below in conjunction with the manufacture method of Fig. 2 a to the inline structure of copper of the tool doping of the 2d explanation embodiment of the invention.
At first, please refer to Fig. 2 a, semiconductor substrate 200 is provided, for example a Silicon Wafer is formed with the several semiconductor assembly in substrate 200, for simplifying, only draws a smooth substrate herein.Then, on the semiconductor-based end 200, form one first dielectric layer 202, for example silicon dioxide layer or low dielectric constant material layer.Subsequently, utilize known photolithography techniques on first dielectric layer 202, to define a groove 203 and expose substrate 200 surfaces.
Next, Fig. 2 b, utilize physical vaporous deposition (physical vapor deposition, PVD), on first dielectric layer 202 and the metallic copper 204 that formation has doped chemical in the groove 203, with as inline structure.In the present embodiment, the employed target of PVD (target) is a copper alloy target, promptly is doped with other element in the copper target, for example is selected from magnesium (Mg), silver (Ag), titanium (Ti), zirconium (Zr), tin (Sn), zinc (Zn), the carbon (C) etc. at least a.In the present embodiment, preferable doped chemical is a magnesium.In addition, also can use plating (plating) copper method to replace described PVD method, be about to doping elements and insert in the electroplate liquid to electroplate.After forming the metallic copper 204 that tool mixes, then the environment of the shaping gas (forming gas) of nitrogen and hydrogen down and temperature 150 to 450 ℃ scope to metallic copper 204 enforcements one annealing in process.Wherein, the processing time was 30 to 120 minutes scope.
Next, please refer to Fig. 2 c, metallic copper 204 after the annealed treatment step, its inner institute doping elements except meeting diffuse to the surface and with arround the oxygen reaction and form the oxide layer 204a, metallic copper 204 inside also have copper alloy crystal grain (grain) to produce (not illustrating).As previously mentioned; because fine copper is very easy to oxidation, and easily diffuses to silicon dioxide layer or silicon layer, therefore can above the copper layer in the inline structure fabrication process, form protective layer; and simultaneously as etch stop layer, and the place formation diffusion shielding layer that is contacting with silicon dioxide layer or silicon layer.Yet in the present embodiment, owing to form the cause of oxide layer 204a, it can replace described protective layer and diffusion shielding layer, therefore has this two-layer original effect and has simplified manufacturing process.In addition, copper alloy crystal grain has the effect of anti-electron transfer (EM) simultaneously.
Next, please refer to Fig. 2 d, utilize chemical mechanical milling method (chemical mechanicpolishing, CMP) remove be formed with oxide layer 204a metallic copper 204 until exposing first dielectric layer, 202 surfaces, in groove 203, stay metallic copper 204, and on described copper surface, form oxide layer 204a simultaneously.At this moment, oxide layer 204a also has the effect of etch stop layer and does not have influence on the carrying out of CMP manufacturing process, therefore according to the manufacture method of the inline structure of copper of the present invention, need not additionally to form etch stop layer.The step of annealing in process also can be after cmp, and its inner institute doping elements shown in Fig. 2 c, forms oxide protective layer 204a.Than known technology, not only simplified manufacturing process, can prevent that simultaneously etch stop layer from causing photoresistance to poison and the capacitance that increases assembly makes the rising of time delay effect in follow-up manufacturing process.At last, metallic copper 204 upper surfaces that are formed with oxide layer 204a on first dielectric layer, 202 surfaces of exposing and in the groove 203 form second dielectric layer 206, to carry out follow-up manufacturing process.This oxide layer 204a can prevent when deposition upper strata mat electricity layer material the chemical reaction to copper, for example oxidation.In addition, because second dielectric layer 206 directly is formed on first dielectric layer 202, be different from the known technology across etch stop layer, so tack (adhesion) is preferable, can improve the generation of leakage current simultaneously.
Moreover as inline structure, the present invention need not additionally to form the copper alloy layer of diffusion shielding layer and adjacency, can effectively simplify manufacturing process than the use copper alloy of another known technology.
In addition, please refer to Fig. 3, its metallic copper that shows fine copper and doping zirconium, magnesium after annealed processing, the variation relation figure of sheet resistor Rs.As seen from the figure, make copper that apparatus mixes as inline structure, after annealed processing, sheet resistor can approach fine copper, therefore can be to assembly electrically cause harmful effect.
Though described embodiment to be making example forming fluted dielectric layer, yet can to recognize at the dielectric layer that is formed with interlayer hole (via hole) or dual-damascene structure (dual damascene) and also can use inline structure making process of the present invention.
Though the present invention with preferred embodiment openly as above; so it is not to be used to limit the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is as the criterion with claim.
Claims (9)
1. the manufacture method of the inline structure of copper of a tool doping comprises the following steps:
Form one first dielectric layer in the semiconductor substrate, wherein said first dielectric layer has groove, interlayer hole or dual-damascene structure;
Insert the metallic copper with doped chemical on described first dielectric layer and in described groove, described interlayer hole or the described dual-damascene structure, with as inline structure, wherein, described doped chemical is selected in magnesium, silver, tin, zinc, carbon at least a;
Described metallic copper is implemented an annealing in process, to form an oxide layer at described copper surface; And
The etching removal is formed with the metallic copper of described oxide layer to exposing the described first dielectric layer surface, stays described metallic copper in described groove, and forms oxide layer simultaneously on described copper surface.
2. the manufacture method of the inline structure of copper that tool as claimed in claim 1 mixes, it is characterized in that, after exposing the described first dielectric layer surface, the described metallic copper upper surface that also is included on described first dielectric layer and is formed with oxide layer in described groove forms one second dielectric layer, to carry out follow-up manufacturing process.
3. the manufacture method of the inline structure of copper that tool as claimed in claim 1 mixes is characterized in that, forms described metallic copper and be to utilize a kind of in physical vaporous deposition, the electrocoppering.
4. the manufacture method of the inline structure of copper that tool as claimed in claim 1 mixes is characterized in that, the temperature of described annealing in process is 150 to 450 ℃ scope.
5. the manufacture method of the inline structure of copper that tool as claimed in claim 1 mixes is characterized in that, the carrying out time of described annealing in process was 30 to 120 minutes scope.
6. the manufacture method of the inline structure of copper that tool as claimed in claim 1 mixes is characterized in that described annealing in process is carried out under the shaping gas environment of nitrogen and hydrogen.
7. the manufacture method of the inline structure of copper that tool as claimed in claim 1 mixes is characterized in that wherein oxide layer is as diffusion shielding layer.
8. the manufacture method of the inline structure of copper that tool as claimed in claim 1 mixes is characterized in that wherein oxide layer is as etch stop layer.
9. the manufacture method of the inline structure of copper that tool as claimed in claim 2 mixes is characterized in that wherein oxide layer is described doped chemical and formation that oxygen reacts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105018 CN1243377C (en) | 2002-02-10 | 2002-02-10 | Method for making mixed copper internal connection stracture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105018 CN1243377C (en) | 2002-02-10 | 2002-02-10 | Method for making mixed copper internal connection stracture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1438691A CN1438691A (en) | 2003-08-27 |
| CN1243377C true CN1243377C (en) | 2006-02-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02105018 Expired - Lifetime CN1243377C (en) | 2002-02-10 | 2002-02-10 | Method for making mixed copper internal connection stracture |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7956465B2 (en) | 2006-05-08 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing resistivity in interconnect structures of integrated circuits |
| US7919862B2 (en) | 2006-05-08 | 2011-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing resistivity in interconnect structures of integrated circuits |
| US8242016B2 (en) | 2007-05-14 | 2012-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach for reducing copper line resistivity |
| CN105006440B (en) * | 2015-06-24 | 2018-01-09 | 武汉新芯集成电路制造有限公司 | A kind of hybrid bonded method of vacuum bonding air pressurization |
| US9595510B1 (en) | 2015-10-13 | 2017-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and formation method for chip package |
| CN109686711A (en) * | 2018-12-26 | 2019-04-26 | 上海集成电路研发中心有限公司 | A method of it realizes hybrid bonded |
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- 2002-02-10 CN CN 02105018 patent/CN1243377C/en not_active Expired - Lifetime
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