CN1466187A - Barrier layer free inner wiring technology and structure with multi-layer seed layers - Google Patents
Barrier layer free inner wiring technology and structure with multi-layer seed layers Download PDFInfo
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- CN1466187A CN1466187A CNA021228868A CN02122886A CN1466187A CN 1466187 A CN1466187 A CN 1466187A CN A021228868 A CNA021228868 A CN A021228868A CN 02122886 A CN02122886 A CN 02122886A CN 1466187 A CN1466187 A CN 1466187A
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Abstract
An interconnect technology and structure with multiple seed layers and non-barrier layer characterizes in having multiple seed layers with interstacked alloy seed layer and pure metal seed layer. The technique utilizes annealing to form the interconnect line structure with non-barrier layer and multiple seed layers avoiding the barrier layer and reducing contact resistance and sheet resistance.
Description
Technical field
The present invention is relevant for metal interconnecting (Interconnect) technology and structure in a kind of semiconductor technology, particularly relevant for a kind of barrier layer free (Barrier Layer) and have interconnecting process and the structure of multilayer Seed Layer (Seed Layer).
Background technology
Recent decades in past, metallic aluminium is used to be used as the conductor material of wafer inside always.Along with dwindling of live width, the speed of element computing just can be subjected to resistance value and capacitance the multiply each other increase that postpones and significant decline.For in the face of more intensive circuit design, industry must select one to have more low-resistance metal material and replace aluminium.
Because copper has low-resistance characteristic, therefore be that the element of lead can bear more intensive circuit arrangement with copper, so can significantly reduce the number of required metal level, and then reduce production costs and improve the arithmetic speed of computer.In addition, copper also has higher electromigration (Electromigration; EM) therefore resistance is that the element of lead has higher life-span and stability with copper.
Copper can't carry out lead cloth with traditional dry-etching technology plants, and therefore the most of wire producing technology of a new generation that adopts of industrial quarters is inlayed the filling that (damascene) method is made copper conductor at present.Please refer to the section of structure of dual damascene technique in the known process for copper of Fig. 1.As shown in Figure 1, at first provide base material 10 and be positioned at etch stop 20 on the base material 10.As for, 30 of dielectric layers are to be positioned on the etch stop 20, and etch stop 40 is positioned on the dielectric layer 30.Wherein, dielectric layer 50 is positioned on the etch stop 40, and definition has interlayer hole 32 to expose the base material 10 of part approximately with groove 52 in dielectric layer 30 and the dielectric layer 50.As for, 60 of barrier layers be conformally cover dielectric layer 50, dielectric layer 30, with the part base material 10 that exposes approximately.In addition, still there is a Seed Layer 70 to be positioned on the barrier layer 60.Comprise more that in known bimetal mosaic structure metal level 80 fills up interlayer hole 32 and groove 52 etc., wherein metal level 80 becomes with copper.
Above-mentioned copper material in order to formation metal level 80 very easily produces diffusion phenomena under the environment of high temperature.Therefore, known copper enchasing technology comprises the step of deposit barrier layers 60, and so as to stoping the generation of copper diffusion, wherein the material of this barrier layer 60 for example is a tantalum nitride (TaN).Yet, with copper by contrast, tantalum nitride has higher resistivity, so the contact resistance of the metal level in interlayer hole and the groove 80 (Contact Resistance; RC) with sheet resistor (SheetResistance; RS) can improve thereupon.So be necessary to seek solution.
Summary of the invention
In the foregoing invention background, in order in comparison, have higher resistivity, and then the contact resistance of the metal level in interlayer hole and the groove and sheet resistor are improved thereupon in the known copper enchasing technology as the tantalum nitride of barrier layer material and copper.Therefore purpose of the present invention can be so as to saving the step of known formation barrier layer for a kind of barrier layer free being provided and having the interconnecting process and the structure of multilayer Seed Layer.
Another object of the present invention can be directly to contact with metal interlevel because of metal level so as to reducing contact resistance and sheet resistor for a kind of barrier layer free being provided and having the interconnecting process and the structure of multilayer Seed Layer.
Another purpose of the present invention can be so as to avoiding the metal level oxidation for a kind of barrier layer free being provided and having the interconnecting process and the structure of multilayer Seed Layer.
According to above-mentioned purpose of the present invention, therefore the invention provides a kind of barrier layer free and have the technology of the intraconnections of multilayer Seed Layer, comprise the following steps: at least that at first base material is provided, and this base material has preset structure, and has opening on this preset structure; Then, form a plurality of Seed Layer covering substrates of storehouse; Then, forming metal level covers Seed Layer and fills up opening; Then, carry out thermal annealing (Annealing) step; Then, planarization metal layer makes the base material that exposes part approximately.
According to above-mentioned purpose of the present invention, so the present invention provides a kind of barrier layer free in addition and has the structure of the intraconnections of multilayer Seed Layer, comprises at least: base material, and this base material has preset structure, and has opening on this preset structure; A plurality of Seed Layer, storehouse also is covered on the part base material in the opening; And the metal level with a plurality of dopant ions, this metal level fills up opening, and this metal level and Seed Layer have about equal height.Wherein, dopant ion is selected from a group that is made up of chromium, palladium, tin, titanium, zirconium, magnesium, aluminium and cobalt.
Description of drawings
Fig. 1 is the section of structure of dual damascene technique in the known process for copper;
Fig. 2 A to Fig. 2 F is the barrier layer free of a preferred embodiment of the present invention and the section of structure with interconnecting process of two-layer Seed Layer; And
Fig. 3 A to Fig. 3 G is the barrier layer free of a preferred embodiment of the present invention and the section of structure with interconnecting process of three layers of Seed Layer.
10: base material 20: etch stop
30: dielectric layer 40: etch stop
32: interlayer hole 50: dielectric layer
52: groove 60: barrier layer
70: Seed Layer 80: metal level
110: base material 125: etch stop
135: dielectric layer 148: etch stop
158: dielectric layer 165: interlayer hole
170: groove 180: Seed Layer
190: Seed Layer 200: metal level
205: metal level 210: metal level
310: base material 325: etch stop
335: dielectric layer 348: etch stop
358: dielectric layer 365: interlayer hole
370: groove 380: Seed Layer
390: Seed Layer 392: Seed Layer
400: metal level 405: metal level
410: metal level
Embodiment
The present invention includes two-layer or two-layer above multilayer Seed Layer.Please refer to the barrier layer free of the preferred embodiment of the present invention shown in Fig. 2 A to Fig. 2 F and have the section of structure of the interconnecting process of two-layer Seed Layer.At first, for example metal level that provides base material 110 and this base material 110 to comprise to form in previous technology as Fig. 2 A or dielectric layer (not illustrating) etc.In addition, base material 110 has more etch stop 125, dielectric layer 135, etch stop 148, dielectric layer 158, interlayer hole 165 and the groove 170 etc. that formed in previous technology.Etch stop 125 is positioned on the base material 110 partly.As for, 135 of dielectric layers are to be positioned on the etch stop 125, and etch stop 148 is positioned on the dielectric layer 135.Wherein, dielectric layer 158 is positioned on the etch stop 148, and definition has interlayer hole 165 to expose the base material 110 of part approximately with groove 170 in dielectric layer 135 and the dielectric layer 158.Then, shown in Fig. 2 B, form part dielectric layer 135 and part base material 110 that Seed Layer 180 conformally covers dielectric layer 158, exposes approximately.Then, shown in Fig. 2 C, form Seed Layer 190 and conformally cover Seed Layer 180.
Above-mentioned Seed Layer 180 and Seed Layer 190 for example can electrochemistry galvanoplastic (Electrochemical Plating; ECP) form, and the purposes of Seed Layer 180 and Seed Layer 190 is used so as to conduction when being follow-up electroplated metal layer.Known Seed Layer only is one deck, and material can be simple metal or alloy.Comprise two-layer material different Seed Layer 180 and Seed Layer 190 herein in the preferred embodiment of the present invention, so as to saving barrier layer, and can overcome known because of using barrier layer to make contact resistance and the too high problem of sheet resistor.As for, Seed Layer 180 has two kinds of combinations with the material of Seed Layer 190.If the material of Seed Layer 180 is an alloy, then the material of Seed Layer 190 is a simple metal.Otherwise if the material of Seed Layer 180 is a simple metal, then the material of Seed Layer 190 is an alloy.Above-mentioned simple metal for example can be copper, and alloy for example can be the alloy of copper layer and other metal, wherein this other metal for example can be chromium (Cr), palladium (Pd), tin (Sn), titanium (Ti), zirconium (Zr), magnesium (Mg), aluminium (Al) or cobalt (Co) etc., and be in the method adding copper layer with mix (Doping), so other metal can be described as admixture (Dopant).In addition, Seed Layer 180 can be about 0.1 to about 10 with the thickness ratio of Seed Layer 190.
Then, shown in Fig. 2 D, form metal level 200, so as to covering Seed Layer 190 and filling up interlayer hole 165 and groove 170 among Fig. 2 C.This step that forms metal level 200 for example can the electrochemistry galvanoplastic be reached.As for, the material of metal level 200 for example can be copper.
Then, carry out thermal anneal step.When this thermal anneal step was finished, the admixture in Seed Layer 180 or the Seed Layer 190 (being metals such as chromium, palladium, tin, titanium, zirconium, magnesium, aluminium or cobalt) can diffuse in the metal level 200 and become as the metal level among Fig. 2 E 205.This metal level 205 with admixture has the function that stops copper to spread under hot environment, thereby in previous technology of the present invention, can not need use barrier layer, further reaching and avoid contact resistance and the too high effect of sheet resistor, is directly to contact event because of metal level and metal interlevel.In addition, the metal level 205 with admixture has more the effect of avoiding oxidation.As for, the temperature of this thermal anneal step can be about 100 ℃ to about 500 ℃.
Then, for example with chemical mechanical milling method (Chemical Mechanical Polishing; CMP) planarization metal layer 205, also expose dielectric layer 158 approximately so as to the metal level 210 that forms as Fig. 2 F.This metal level 210 is and utilizes the formed metal interconnecting of the present invention.
Another preferred embodiment of the present invention can be with reference to figure 3A to Fig. 3 G.Fig. 3 A to Fig. 3 G is the barrier layer free of a preferred embodiment of the present invention and the section of structure with interconnecting process of three layers of Seed Layer.At first, for example metal level that provides base material 310 and this base material 310 to comprise to form in previous technology as Fig. 3 A or dielectric layer (not illustrating) etc.In addition, base material 310 has more etch stop 325, dielectric layer 335, etch stop 348, dielectric layer 358, interlayer hole 365 and the groove 370 etc. that formed in previous technology.Etch stop 325 is positioned on the base material 310 partly.As for, 335 of dielectric layers are to be positioned on the etch stop 325, and etch stop 348 is positioned on the dielectric layer 335.Wherein, dielectric layer 358 is positioned on the etch stop 348, and definition has interlayer hole 365 to expose the base material 310 of part approximately with groove 370 in dielectric layer 335 and the dielectric layer 358.Then, shown in Fig. 3 B, form part dielectric layer 335 and part base material 310 that Seed Layer 380 conformally covers dielectric layer 358, exposes approximately.Then, shown in Fig. 3 C, form Seed Layer 390 and conformally cover Seed Layer 380.Then, shown in Fig. 3 D, form Seed Layer 392 and conformally cover Seed Layer 390.
Above-mentioned Seed Layer 380, Seed Layer 390 and Seed Layer 392 for example can the electrochemistry galvanoplastic form, and the purposes of Seed Layer 380, Seed Layer 390 and Seed Layer 392 is used so as to conduction when being follow-up electroplated metal layer.Comprise the different Seed Layer of three-layer-material 380, Seed Layer 390 and Seed Layer 392 in this another preferred embodiment of the present invention, so as to saving barrier layer, and can overcome known because of using barrier layer to make contact resistance and the too high problem of sheet resistor.As for, the material of Seed Layer 380, Seed Layer 390 and Seed Layer 392 has two kinds of combinations.If the material of Seed Layer 380 is an alloy, then the material of Seed Layer 390 is a simple metal, and the material of Seed Layer 392 is an alloy.Otherwise if the material of Seed Layer 380 is a simple metal, then the material of Seed Layer 390 is an alloy, and the material of Seed Layer 392 is a simple metal.Above-mentioned simple metal for example can be copper, and alloy for example can be the alloy of copper and other metal, wherein this other metal for example can be chromium, palladium, tin, titanium, zirconium, magnesium, aluminium or cobalt etc., and is to add in the copper, so other metal can be described as admixture with the method for mixing.In addition, Seed Layer 380 can be about 0.1 to about 10 with the thickness ratio of Seed Layer 390.And the thickness of Seed Layer 390 and Seed Layer 392 is than also can be about 0.1 to about 10.
Then, shown in Fig. 3 E, form metal level 400, so as to covering Seed Layer 392 and filling up interlayer hole 365 and groove 370 among Fig. 3 D.This step that forms metal level 400 for example can the electrochemistry galvanoplastic be reached.As for, the material of metal level 400 for example can be copper.
Then, carry out thermal anneal step.When this thermal anneal step was finished, the admixture in Seed Layer 380, Seed Layer 390 or the Seed Layer 392 (being metals such as chromium, palladium, tin, titanium, zirconium, magnesium, aluminium or cobalt) can diffuse in the metal level 400 and become as the metal level among Fig. 3 F 405.This metal level 405 with admixture has the function that stops copper to spread under hot environment, thereby in previous technology of the present invention, can not need use barrier layer, further reaching and avoid contact resistance and the too high effect of sheet resistor, is directly to contact event because of metal level and metal interlevel.In addition, the metal level 405 with admixture has more the effect of avoiding oxidation.As for, the temperature of this thermal anneal step can be about 100 ℃ to about 500 ℃.
Then, for example with chemical mechanical milling method planarization metal layer 405, also expose dielectric layer 358 approximately so as to the metal level 410 that forms as Fig. 3 G.This metal level 410 is and utilizes the formed metal interconnecting of the present invention.
Seed Layer among the present invention be two-layer or two-layer more than, and be not limited among above-mentioned two embodiment two-layer with three layers.The number of plies that spirit of the present invention is Seed Layer no matter why, these Seed Layer are by an alloy Seed Layer and simple metal Seed Layer storehouse alternately or in regular turn, and orlop (being the Seed Layer 380 among Seed Layer 180 and Fig. 3 B to Fig. 3 G among Fig. 2 B to Fig. 2 F) can be alloy Seed Layer or simple metal Seed Layer.Just, with four layers be example, if orlop is the alloy Seed Layer, then the second layer to the from lower to upper is simple metal Seed Layer, alloy Seed Layer and simple metal Seed Layer for four layers in regular turn; Otherwise if orlop is the simple metal Seed Layer, then the second layer to the from lower to upper is alloy Seed Layer, simple metal Seed Layer and alloy Seed Layer for four layers in regular turn.As for more than five layers or five layers, can in like manner analogize.
Comprehensively above-mentioned, an advantage of the present invention can be so as to saving the step of known formation barrier layer for a kind of barrier layer free being provided and having the interconnecting process and the structure of multilayer Seed Layer.
Another advantage of the present invention can be directly to contact with metal interlevel because of metal level so as to reducing contact resistance and sheet resistor for a kind of barrier layer free being provided and having the interconnecting process and the structure of multilayer Seed Layer.
Another advantage of the present invention can be so as to avoiding the metal level oxidation for a kind of barrier layer free being provided and having the interconnecting process and the structure of multilayer Seed Layer.
Claims (10)
1. a barrier layer free (Barrier layer) and have the technology of the intraconnections (Interconnect) of multilayer Seed Layer (Seed Layer) is characterized in that this technology comprises at least:
One base material is provided, and this base material has a preset structure, and has an opening on this preset structure;
The a plurality of Seed Layer that form storehouse cover this base material;
Forming a metal level covers those Seed Layer and fills up this opening;
Carry out a thermal annealing (Annealing) step; And
This metal level of planarization makes this preset structure that exposes part approximately.
2. barrier layer free as claimed in claim 1 and have the technology of the intraconnections of multilayer Seed Layer is characterized in that, those Seed Layer comprise that at least one alloy Seed Layer and at least one simple metal Seed Layer are by the up mutual storehouse in a surface of this base material.
3. barrier layer free as claimed in claim 2 and have the technology of the intraconnections of multilayer Seed Layer, it is characterized in that, the material of this at least one alloy Seed Layer comprises a copper and a metallics, and this metallics is selected from a group that is made up of chromium, palladium, tin, titanium, zirconium, magnesium, aluminium and cobalt.
4. barrier layer free as claimed in claim 2 and have the technology of the intraconnections of multilayer Seed Layer is characterized in that, the thickness of this at least one alloy Seed Layer and this at least one simple metal Seed Layer is than being about 0.1 to about 10.
5. barrier layer free as claimed in claim 1 and have the technology of the intraconnections of multilayer Seed Layer is characterized in that the temperature of this thermal anneal step is about 100 ℃ to about 500 ℃.
6. barrier layer free as claimed in claim 1 and have the technology of the intraconnections of multilayer Seed Layer is characterized in that, the step of this this metal level of planarization is used cmp (Chemical Mechanical Polishing; CMP) method.
7. a barrier layer free and have the structure of the intraconnections of multilayer Seed Layer is characterized in that this structure comprises at least:
One base material, this base material has a preset structure, and has an opening on this preset structure;
A plurality of Seed Layer, storehouse also is covered on this base material of part in this opening; And
Have a metal level of a plurality of dopant ions, this metal level fills up this opening, and this metal level and those Seed Layer have about equal height.
8. barrier layer free as claimed in claim 7 and have the structure of the intraconnections of multilayer Seed Layer is characterized in that, those Seed Layer comprise that at least one alloy Seed Layer and at least one simple metal Seed Layer are by the up mutual storehouse in a surface of this base material.
9. barrier layer free as claimed in claim 8 and have the structure of the intraconnections of multilayer Seed Layer, it is characterized in that, the material of this at least one alloy Seed Layer comprises a copper and a metallics, and this metallics is selected from a group that is made up of chromium, palladium, tin, titanium, zirconium, magnesium, aluminium and cobalt.
10. barrier layer free as claimed in claim 7 and have the structure of the intraconnections of multilayer Seed Layer is characterized in that those dopant ions are selected from a group that is made up of chromium, palladium, tin, titanium, zirconium, magnesium, aluminium and cobalt.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021228868A CN1327506C (en) | 2002-06-17 | 2002-06-17 | Barrier layer free inner wiring technology and structure with multi-layer seed layers |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021228868A CN1327506C (en) | 2002-06-17 | 2002-06-17 | Barrier layer free inner wiring technology and structure with multi-layer seed layers |
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| CN1466187A true CN1466187A (en) | 2004-01-07 |
| CN1327506C CN1327506C (en) | 2007-07-18 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101689490B (en) * | 2007-06-28 | 2011-12-21 | 东京毅力科创株式会社 | Filming method, and treating system |
| CN102543778A (en) * | 2010-12-16 | 2012-07-04 | 索泰克公司 | Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods |
| US8778773B2 (en) | 2010-12-16 | 2014-07-15 | Soitec | Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods |
| CN107170705A (en) * | 2016-03-08 | 2017-09-15 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143650A (en) * | 1999-01-13 | 2000-11-07 | Advanced Micro Devices, Inc. | Semiconductor interconnect interface processing by pulse laser anneal |
-
2002
- 2002-06-17 CN CNB021228868A patent/CN1327506C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101689490B (en) * | 2007-06-28 | 2011-12-21 | 东京毅力科创株式会社 | Filming method, and treating system |
| CN102543778A (en) * | 2010-12-16 | 2012-07-04 | 索泰克公司 | Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods |
| US8778773B2 (en) | 2010-12-16 | 2014-07-15 | Soitec | Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods |
| CN102543778B (en) * | 2010-12-16 | 2015-08-26 | 索泰克公司 | Semiconductor structure Direct Bonding method together and the semiconductor structure of bonding |
| CN107170705A (en) * | 2016-03-08 | 2017-09-15 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
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| Publication number | Publication date |
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| CN1327506C (en) | 2007-07-18 |
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