CN2770096Y - Semiconductor substrate structure - Google Patents

Semiconductor substrate structure Download PDF

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Publication number
CN2770096Y
CN2770096Y CNU2004200590373U CN200420059037U CN2770096Y CN 2770096 Y CN2770096 Y CN 2770096Y CN U2004200590373 U CNU2004200590373 U CN U2004200590373U CN 200420059037 U CN200420059037 U CN 200420059037U CN 2770096 Y CN2770096 Y CN 2770096Y
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China
Prior art keywords
metallic film
copper
semiconductor
equipment structure
based equipment
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Expired - Lifetime
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CNU2004200590373U
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Chinese (zh)
Inventor
万文恺
林义雄
雷明达
彭宝庆
林正忠
林佳惠
刘埃森
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemically Coating (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor substrate structure includes a substrate provided with a conductive area and a nonconductive area, wherein the conductive area consists of copper conducting wires and is formed by electroplating process. An alloy layer is formed in these conductive areas and is formed by a cobalt metallic film and a copper metallic film through the process of heat treatment.

Description

Semiconductor-based equipment structure
Technical field
The utility model relates to a kind of semiconductor-based equipment structure, particularly a kind of semiconductor-based equipment structure with surface treated copper conductor.
Background technology
Along with the microminiaturization trend of the live width size of integrated circuit, particularly 0.25 micron, and even below 0.13 micron, (ResistanceCapacitance Delay Time resistance capacitance time of delay that the arithmetic speed of assembly obviously is subjected to plain conductor and is caused; RC Delay Time) influence is so that reduce its arithmetic speed.Therefore, in the face of the higher circuit design of present integration (Integration), has more low-resistance metal material except adopting, for example resistance value is about the copper (Cu) of 1.67 microhm-centimetres, replace the aluminium that traditional resistance value that is adopted is about 2.66 microhm-centimetres, the dielectric material of low-k of also must arranging in pairs or groups comes construction multiple layer metal lead, to improve the phenomenon that RC postpones.
Because copper has low-resistance characteristic, so be that the assembly of lead can bear more intensive circuit arrangement with copper.So the use of copper plain conductor not only can significantly reduce the number of metal level, reduce production costs, but the arithmetic speed of lifting subassembly also.Copper has the ability of higher anti-electron transfer (Electro-migration), therefore, is that the assembly of lead also has longer life-span and preferable advantages such as stability with copper.
But, because the copper metal can't use traditional dry-etching technology, to plant to carry out lead cloth, therefore most of employing is inlayed (Damascene) process technique and is carried out the making of copper conductor.What more often be used in copper wiring at present is a kind of technology that can form interlayer hole connector and plain conductor simultaneously, is called dual-metal inserting (Dual Damascene) processing procedure.
But some chemical property of copper metal have limited the development of copper wiring on integrated circuit also.For instance, copper atom has diffusivity fast, so under the acceleration of electric field, copper atom can penetrate dielectric layer and diffusion fast, in case especially copper atom diffuses in the silicon substrate, will cause the performance degradation and the inefficacy of assembly.Therefore, before copper metal layer forms, need to form earlier to prevent the barrier layer (Barrier Layer) that copper contacts with oxide layer or silicon layer, to avoid producing the problem of copper diffusion.Another effect of barrier layer then is the adhesive force that is used for promoting metal and other material.General barrier layer materials can be divided into metallic barrier material and dielectric barrier layer material etc., and common barrier layer materials for example has tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN) or the like.
In the copper conductor processing procedure of double-metal inlaid structure, because the upper surface of copper conductor does not have barrier layer.Therefore, on the interface of copper metal and dielectric etch stop layer, not only the copper metal easily forms porous cupric oxide, and easily causes copper atom diffusion fast.Not only cause the problem of the serious reliability of integrated circuit, more reduced conductive stability, and influence the quality of integrated circuit package.
Therefore, how can effectively prevent the diffusion and the oxidation of copper atom, depend on the diffusion energy (Diffusion Energy) that improves the copper conductor surface, not only can reduce the problem of copper surface oxidation and copper atom diffusion, also can improve the stability of integrated circuit.And can further improve the production reliability of integrated circuit, be the user and the ardent hope of producer of integrated circuit.
Summary of the invention
In above-mentioned utility model background, because the upper surface of the copper conductor of dual-metal inserting processing procedure is not because of having covering barrier layer thereon, so that cause the problem of the serious reliability of integrated circuit, not only reduce electric conductivity, more influenced the quality of integrated circuit package.
One of the purpose of this utility model is to provide a kind of semiconductor-based equipment structure with surface treated copper conductor, and this copper conductor surface does not form cupric oxide, can not cause the problem of copper atom diffusion.
According to above-described purpose, the utility model provides a kind of method that forms semiconductor-based equipment structure.The method comprises the following step, at first provides a base material to have several conductive regions and several non-conductive zones.Follow covering metal film in the surface of conductive region, then the surface of cleaned base material.The method also comprises heat-treats metallic film, makes the metal material of metallic film and conductive region form alloy-layer.
Wherein above-mentioned covering metal film utilize the processing procedure of electroless plated metal film to carry out, and conductive region is made of in the surface of conductive region copper conductor.The processing procedure of electroless plated metal film immerses base material in one chemical solution of being scheduled to, to form metallic film on presumptive area.Generally speaking, this processing procedure can use as electroless nickel plating (Niickel; Ni), electroless plating palladium (Palladium; Pd) or electroless plating cobalt (Cobalt; Co) etc. mode is carried out.
This electroless plating processing procedure is appropriate to use especially on the copper conductor of semiconductor substrate, and it can form metallic film naturally on the copper conductor surface, effectively isolates the interface of copper conductor and dielectric etch stop layer.Effectively improve the diffusion into the surface energy of copper conductor, reduce the probability of copper conductor surface oxidation, make the reliability thereby the raising of integrated circuit.And copper conductor after the heat treatment and thin nickel metal film form the monel layer.So the electroless plating processing procedure of copper conductor of the present utility model can effectively improve the anti-electron transfer of copper conductor, stress migration (StressMigration; SM) with according to the time dielectric collapse (Time Dependent Dielectric Breakdown; Characteristic such as TDDB).
Description of drawings
Fig. 1 is the structural representation of the copper conductor cross section of the utility model semiconductor substrate;
Fig. 2 is a flow process schematic diagram, and the electroless process of copper conductor of the present utility model is described.
Embodiment
The utility model provides a kind of surface-treated method of copper conductor, improves the diffusion into the surface energy of copper conductor, to improve the problem of copper conductor surface oxidation, not only improves the stability of the operation of integrated circuit, more can further improve the reliability of integrated circuit (IC) products.Below will clearly demonstrate spirit of the present utility model with icon and detailed description, as the person skilled in the art after understanding preferred embodiment of the present utility model, when can be by the technology of the utility model institute teaching, change and modification, it does not break away from spirit of the present utility model and scope.
Consulting Fig. 2, is a flow process schematic diagram, to be used for illustrating the electroless process of copper conductor of the present utility model as shown in FIG..Step 110 at first provides a base material, has conductive region and non-conductive zone on this base material, and as shown in Figure 1, for example conductive region 10 is the upper surface of copper conductor 1, but not 12 of conductive regions are the dielectric material around the copper conductor etc.
Step 120 is the conductive region on this base material optionally, forms metallic film.For example use electroless method on this conductive region, to form metallic film.Electroless method is that base material is immersed in the predetermined chemical solution, to carry out chemical reaction, makes nature form metallic film on conductive region.For example, at the upper surface of above-mentioned copper conductor,, form nickel (Nickel with electroless method; Ni) metallic film 14, and its thickness is about 200 dusts (Angstrom) to 1000 dusts, and preferable is 500 dusts.One example data below is provided, as the data in the table one, use electroless nickel plating on copper conductor with explanation, and then form the detailed data data of thin nickel metal film, this example data only is used for execution mode of the present utility model is described, but not is used for limiting scope of the present utility model.
Table one: the chemical composition reference data of chemical solution that is used in the electroless nickel plating of copper conductor
Nickelous sulfate (NiSO4.6H2O) 20 grams per liters
Coloured glaze Meticortene Solu-Delta-cortef (Sodium Succinate) 6 grams per liters
Sodium hypophosphite (NaH2PO2.H2O) 27 grams per liters
When the chemical solution in the use table one carried out the electroless nickel plating of copper conductor, at first the pH value with chemical solution was adjusted to 4, and to keep working temperature in processing procedure be 88 ± 1 ℃.
Owing to electroless method can form the electroless plated metal film at conductive region by nature, and can't form this metallic film, so very be appropriate on semiconductor substrate, process with partially conductive zone and the non-conductive zone of part in non-conductor area.The utility model does not limit and is used in electroless nickel plating, can use cobalt (Cobalt yet; Or palladium (Palladium Co); Pd) the electroless plating processing procedure of metal, perhaps other forms metallic film in the processing procedure of the conductive region of above-mentioned base material, and it does not all break away from scope of the present utility model.
Step 130 after the metallic film of finishing conductive region adheres to, is cleaned substrate surface.Step 140, then again this base material is heat-treated, further make the metal surface of this metallic film and conductive region form alloy-layer, for example with nickel metal and copper metal with about 400 degrees centigrade of heating after 30 minutes to 60 minutes, to form a monel layer 16, monel then has superior corrosion resistance and thermal endurance.
Because copper atom is easy to diffusion and is easy to oxidation, so that cause the reduction of the production reliability of integrated circuit, the utility model effectively utilizes electroless nickel plating or other metal of electroless plating, improves the diffusion into the surface energy of copper conductor, with effective isolation copper conductor and dielectric etch stop layer.Not only make the reliability thereby the raising of integrated circuit, and further heat-treat, make copper conductor surface and thin nickel metal film form the monel layer.The utility model effectively improves the characteristic on copper conductor surface, makes anti-electron transfer, stress migration with according to the time characteristic such as dielectric collapse all obtain effective improvement.

Claims (8)

1. semiconductor-based equipment structure is characterized in that it comprises at least:
One base material has several conductive regions and several non-conductive zones on this base material, and these conductive regions comprise one first metallic film, and wherein this first metallic film is formed by electroplating process; And
One alloy-layer is formed at these conductive regions, and wherein this alloy-layer is formed by one second metallic film and this first metallic film, and this second metallic film uses and the different materials of this first metallic film constitutes.
2. semiconductor-based equipment structure according to claim 1 is characterized in that: the first above-mentioned metallic film is constituted by a bronze medal film.
3. semiconductor-based equipment structure according to claim 1 is characterized in that: the second above-mentioned metallic film is the cobalt metallic film.
4. semiconductor-based equipment structure according to claim 1 is characterized in that: the second above-mentioned metallic film is the palladium metal film.
5. semiconductor-based equipment structure according to claim 1 is characterized in that: the second above-mentioned metallic film is a thin nickel metal film.
6. semiconductor-based equipment structure according to claim 5 is characterized in that: the thickness of above-mentioned thin nickel metal film is between 200 dust to 1000 dusts.
7. semiconductor-based equipment structure according to claim 6 is characterized in that: the thickness of above-mentioned thin nickel metal film is 500 dusts.
8. semiconductor-based equipment structure according to claim 5 is characterized in that: above-mentioned alloy-layer is a monel layer.
CNU2004200590373U 2003-05-16 2004-05-17 Semiconductor substrate structure Expired - Lifetime CN2770096Y (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/439,358 US6955984B2 (en) 2003-05-16 2003-05-16 Surface treatment of metal interconnect lines
US10/439,358 2003-05-16

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CNB2003101142618A Expired - Fee Related CN1321439C (en) 2003-05-16 2003-11-06 Electroless plating method for copper wire
CNU2004200590373U Expired - Lifetime CN2770096Y (en) 2003-05-16 2004-05-17 Semiconductor substrate structure

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Publication number Publication date
US20060001160A1 (en) 2006-01-05
SG122792A1 (en) 2006-06-29
TWI317766B (en) 2009-12-01
US8053894B2 (en) 2011-11-08
US20040229460A1 (en) 2004-11-18
US6955984B2 (en) 2005-10-18
CN1551301A (en) 2004-12-01
TW200426244A (en) 2004-12-01
CN1321439C (en) 2007-06-13

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Expiration termination date: 20140517

Granted publication date: 20060405