TWI221398B - Circuit board with conductive barrier layers and method for fabricating the same - Google Patents

Circuit board with conductive barrier layers and method for fabricating the same Download PDF

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Publication number
TWI221398B
TWI221398B TW92128803A TW92128803A TWI221398B TW I221398 B TWI221398 B TW I221398B TW 92128803 A TW92128803 A TW 92128803A TW 92128803 A TW92128803 A TW 92128803A TW I221398 B TWI221398 B TW I221398B
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layer
circuit
conductive
barrier layer
board
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TW92128803A
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Chinese (zh)
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TW200515846A (en
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Ruei-Chih Chang
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Phoenix Prec Technology Corp
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Abstract

A circuit board with conductive barrier layers and a method for fabricating the same are proposed. A core substrate is formed with a conductive layer on the surface thereof, and an inner circuit layer is formed thereon with the conductive layer. An insulating layer is formed on the inner circuit layer with a plurality of openings to expose the inner circuit layer, and a first barrier layer for preventing metal migration is formed on the surface of the insulating layer and openings. Then, a patterned resist layer is formed on the first barrier layer with a plurality of openings to expose the barrier layer, and a patterned circuit layer is formed within the openings by an electroplating method to electrically connect to the inner circuit layer. After the resist layer and the first barrier layer underneath the resist layer are removed, a second barrier layer is formed on the outer surface of the patterned circuit layer to prevent short and interaction of the circuit layers owing to metal migration.

Description

五、發明說明(1) 【發明所屬之技術領域 本發明係有關於一種|邕兩从π泣Ρ 法,尤指一種在電路板之電路: :::::路板及其製 以阻絕金屬遷移現象,i ;電:二:-屬阻障層, 附著力之電路板結構及其製作 路板内笔路層舆絕緣層 【先前技術】 /V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a | two-pronged π method, especially a circuit on a circuit board: ::::: road board and its system to block metal Migration phenomenon, i; Electricity: Two:-Barrier layer, circuit board structure with adhesive force and its insulation layer on the circuit board [Previous technology] /

笔子產品輕小化,ρ B E 行動電話、手提電腦^ ^ ^以來眾所周知之趨勢,如 (PerS〇nal d. 、 錄放影機或個人數位助理 少制从y lgl a assistant)等;因此,這些電子產口 件衣】要使用比以前更小、$薄的電路板;電子元扣 侔禮嗖二: 小化之趨勢’係將各種不同功能之半導體元 、晨肷在一電路板上,以達縮小電路板之需求,如此一 來’ f I路板(Clrcuit board)之線路佈線必須有更高密 度之需求’因此對應用上述更薄且高佈線密度之多層電路 板於電子產品來說,電路板之製程與設計將面臨更高之挑 戰0 在電路板製作業,低成本,高可靠度及高佈線密度一 直是所追求之目標;為達此目標,於是發展出一種增層技 術(Bui ld-up),而所褶的挎芦技術,基本上是指在一核心 t ^ ^ (Core c , rcuV; l;r!)i ^ ^ 4 ^ ^ ^ 及導電層’再於絕緣層製作導電盲孔以提供各導電層間之 電性連接。 而習知之增層電路板,如第9圖所示,係於一芯層板 3 〇 0形成有第一電路層3 〇丨,且該芯層板3 0 0中設有導通孔Lightweight pen products, ρ BE mobile phones, laptops ^ ^ ^ well-known trends, such as (PerSonal d., Video recorders or personal digital assistants from y lgl a assistant), etc .; therefore, these Electronic products and clothing] To use smaller and thinner circuit boards than before; electronic element deduction 侔 2: the trend of miniaturization 'is to combine semiconductor elements and morning cells with various functions on a circuit board to To reduce the demand for circuit boards, so that 'f I circuit board (Clrcuit board) line wiring must have a higher density demand', so for the application of the above-mentioned thinner and high wiring density multilayer circuit boards to electronic products, The process and design of circuit boards will face higher challenges. 0 In circuit board manufacturing, low cost, high reliability, and high wiring density have always been the goals pursued. To achieve this goal, a layer-increasing technology (Bui ld-up), and the folded shoulder reed technology basically refers to the production of a core t ^ ^ (Core c, rcuV; l; r!) i ^ ^ 4 ^ ^ ^ and the conductive layer Conductive blind holes to provide electrical connection between conductive layers Pick up. As shown in FIG. 9, the conventional layered circuit board is formed on a core layer board 300 with a first circuit layer 3 〇 丨, and a through hole is provided in the core layer board 300.

17360全戀.ρΐοΐ 第6頁 友、發明說明(2) 電:以二卜層板上下表面之電路層301;再於該 ΚΪ t ίϊ,緣層303’且在該絕緣,3 0 3中形 战有目孔3 0 4,又该目孔3 〇 4得盥兮筮 _ 如此即可在該絕緣層3 0 3上形于成、/_弟/+電路層301相通, 層電路305得以透過該盲第-層上路3°5,使該第二 樓,俾製成多層之增層電路I:弟-電路層301電性連 但如前所)’為達電子產品縮小化與功能增加 永,電路板之線路設計越來越密集,且若受電路 而 +之限制,則線路必須再以增層的方式增加,作=積大 :度仍有-定的限制1此層與層之間也越來越γ板之 :路板之線路越緊密,或層與層之間越薄,因材料=,而 =,於線路電流導通時,構成線路之導電的銅粒勺特 有可能會遷移擴散而滲入至絕緣層3〇3,使得兩相〇6即 ^之間的絕緣部份有銅遷移(c〇pper migrati〇n =的緩 如第1〇圖所示,甚而導致線路短路問題。 見象, 在高佈線密度之電路板中,由於線路之間,或爲 :間相當密1,相對地絕緣部份較為狹小,當有:與層 夕見象產生B寸這成絕緣部分的絕緣層3 0 3内有導,、子遷 粒子306,則使絕緣效果降低,如此一來,則容易=銅 $之間’或層與層之間形成短路,使得電路板無。、線 作;且隨著使用眭pq w , $常私 〜 1間增加,銅遷移的現象會越加明翱 動 了絕緣部份内的銅粒子3G6 部貝’使 漸有導電失去絕緣的效果。 #份% 因此ik著線路高密度發展趨勢,使得增層電路 欠的層17360 全 恋 .ρΐοΐ Page 6 Friends and Inventions (2) Electricity: Take the circuit layer 301 on the upper and lower surfaces of the two-layer board; then in the ΚΪ t ίϊ, the edge layer 303 'and in the insulation, 3 0 3 shape There is an eye hole 3 0 4 and the eye hole 3 04 can be cleaned. In this way, the insulating layer 3 0 3 can be formed, and the / _ brother / + circuit layer 301 communicates, and the layer circuit 305 can pass through. The blind first-floor road is 3 ° 5, so that the second floor is made into a multi-layer build-up circuit I: Brother-circuit layer 301 is electrically connected but as previously mentioned) ' The circuit board circuit design is becoming more and more dense, and if it is limited by the circuit, the circuit must be increased by adding layers, as = large: the degree is still-a fixed limit 1 between this layer and the layer It is also becoming more and more γ board: the tighter the circuit of the circuit board, or the thinner the layer-to-layer, due to the material =, and =, when the line current is conducted, the conductive copper particles that form the line may migrate and diffuse. And the penetration into the insulating layer 303 caused copper migration in the insulating part between the two phases 〇6, that is, the slowness of cppper migrati〇n = as shown in Figure 10, and even led to the line Circuit short circuit. See, in the circuit board with high wiring density, because the wiring between, or is quite close to 1, the insulation part is relatively small. In the insulating layer 3 0 3 of the insulating part, there are conductive particles and sub-migration particles 306, which reduces the insulation effect. In this way, it is easy to form a short circuit between copper or between layers, making the circuit board non-existent. And wire work; and with the use of 眭 pq w, $ 常 私 ~ 1 increase, the phenomenon of copper migration will become more and more obvious, the copper particles in the insulation part will move 3G6 parts, which will gradually lose the effect of insulation. # 份 % Therefore, ik follows the trend of high-density development of circuits, which makes the layers of the layer increase.

1221398 五、發明說明(3) 與層之間或線與線之間,因材料的極限以及絕緣層越來越 薄,如何克服銅粒子遷移的現象,已成為未來電子產品發 展之急待解決的重要課題。 【發明内容】 鑑於前述習知技術之缺失,本發明之主要目的在提供 一種具導電性阻障層之電路板及其製法,係在電路層表面 形成有金屬阻障層,俾藉由該金屬阻障層阻絕金屬遷移現 象,以避免造成短路或干擾的情況,使多層電路板之線路 得以密集佈設,或使層與層之間得更薄小,俾以製成更多 層之電路板。 本發明之又一目的在提供一種具導電性阻障層之電路 板及其製法,係在電路層表面形成有金屬阻障層,俾得藉 由金屬阻障層增強電路板中電路層與絕緣層之附著力。 為達上述之目的,本發明係提供一種具導電性阻障層 之電路板及其製法,較佳之實施步驟係包括:提供一芯層 板,該芯層板表面具有導電層,並於該芯層板至少一表面 之導電層上形成基層電路層;於該基層電路層上增層至少 一非導電性之絕緣層,且在該絕緣層上形成有複數個開口 以外露該基層電路層;於該絕緣層及開口表面形成防止金 屬遷移的第一金屬阻障層(Barrier layer);在該第一金 屬阻障層上形成圖案化阻層,且該阻層形成有多數之開口 以外露出該金屬阻障層;在該阻層開口中電鍍形成圖案化 電路層;移除該阻層及其所覆蓋之第一金屬阻障層;以及 於該圖案化電路層表面形成第二金屬阻障層。俾藉由該第1221398 V. Description of the invention (3) Between the layers or between the wires, due to the material limit and the insulation layer is getting thinner and thinner, how to overcome the phenomenon of copper particle migration has become an urgent issue for the development of future electronic products. important topic. [Summary of the Invention] In view of the lack of the aforementioned conventional technology, the main object of the present invention is to provide a circuit board with a conductive barrier layer and a method for manufacturing the same. A metal barrier layer is formed on the surface of the circuit layer. The barrier layer blocks the metal migration phenomenon to avoid short circuits or interference, so that the wiring of the multilayer circuit board can be densely arranged, or the layers can be made thinner and smaller, so as to make more layers of circuit boards. Another object of the present invention is to provide a circuit board with a conductive barrier layer and a method for manufacturing the same. A metal barrier layer is formed on the surface of the circuit layer, so that the circuit layer and the insulation in the circuit board are enhanced by the metal barrier layer. Layer adhesion. To achieve the above object, the present invention provides a circuit board with a conductive barrier layer and a method for manufacturing the same. The preferred implementation steps include: providing a core board having a conductive layer on the surface of the core board, and A base circuit layer is formed on the conductive layer on at least one surface of the laminate; at least one non-conductive insulation layer is added on the base circuit layer, and a plurality of openings are formed on the insulation layer to expose the base circuit layer; A first barrier layer is formed on the insulating layer and the opening surface to prevent metal migration; a patterned barrier layer is formed on the first metal barrier layer, and the barrier layer is formed with a majority of the opening to expose the metal A barrier layer; electroplating in the opening of the barrier layer to form a patterned circuit layer; removing the barrier layer and the first metal barrier layer covered by the barrier layer; and forming a second metal barrier layer on the surface of the patterned circuit layer.该 With the first

17360 全懋.ptd 第8頁 1221398 五、發明說明(4) 一、第二金屬阻障層包覆該電路層表面以阻絕金屬遷移現 象,進而避免造成短路或干擾的情況,並可增強圖案化電 路層與絕緣層之附著力。 本發明亦提供一種具導電性阻障層之電路板,其主要 係包括:一芯層板,其表面形成有基層電路層,並藉由複 數電鍍導通孔以電性導接該基層電路層;至少一絕緣層, 其係形成在該芯層板之基層電路層上,且於該絕緣層中形 成有複數個得與基層電路層電性連接之導電盲孔;至少一 圖案化電路層,係形成在該絕緣層上;以及一金屬阻障層 (Barrier layer),係包覆住該圖案化電路層。 透過本發明中在電路層表面包覆阻隔有金屬阻障層, 使電路板中電路層相鄰線路之間的絕緣層或於電路板中之 層間絕緣層不會有銅遷移的現象,因此電路板中絕緣層之 設置將可更輕薄,故得以製作更輕薄的多層電路板。同時 該金屬阻障層除了得以用來防止金屬粒子遷移的現象外, 亦可用以增強電路層與絕緣層之附著力,使該電路層得緊 密結合在絕緣層上以避免產生脫離的情況,因此得有較佳 的使用效果。 【實施方式】 為使本發明之目的、特徵及功效,能更進一步的瞭解 與認同,茲配合圖式詳細說明如后。當然,本發明可以多 種形式實施之,以下所述係為本發明之較佳實施例,而非 用以限制本發明之範圍,合先敘明。 請參閱第1至8圖,為本發明實施例之具導電性阻障層17360 Quan 懋 .ptd Page 8 1221398 V. Description of the invention (4) 1. A second metal barrier layer covers the surface of the circuit layer to prevent metal migration, thereby avoiding short circuits or interference, and can enhance patterning. Adhesion between circuit layer and insulation layer. The invention also provides a circuit board with a conductive barrier layer, which mainly includes: a core layer board, a base circuit layer is formed on the surface, and the base circuit layer is electrically connected through a plurality of plated through holes; At least one insulating layer is formed on the base circuit layer of the core board, and a plurality of conductive blind holes electrically connected to the base circuit layer are formed in the insulating layer; at least one patterned circuit layer is Formed on the insulating layer; and a metal barrier layer covering the patterned circuit layer. By covering the circuit layer with a metal barrier layer on the surface of the present invention, the insulation layer between adjacent lines of the circuit layer in the circuit board or the interlayer insulation layer in the circuit board will not have copper migration, so the circuit The arrangement of the insulating layer in the board can be thinner and thinner, so that a thinner and lighter multilayer circuit board can be manufactured. At the same time, in addition to being used to prevent the migration of metal particles, the metal barrier layer can also be used to enhance the adhesion between the circuit layer and the insulating layer, so that the circuit layer is tightly bonded to the insulating layer to avoid detachment. Have a better effect. [Embodiment] In order to make the purpose, characteristics and effects of the present invention more understandable and agreeable, the detailed description with the drawings is as follows. Of course, the present invention may be implemented in various forms. The following description is a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, which will be described before. Please refer to FIGS. 1 to 8 for a conductive barrier layer according to an embodiment of the present invention.

17360 全懋.ptd 第9頁 1221398 五、發明說明(5) 之製程方法剖面示意圖。 如第1圖所示,首先提供〆芯層板、100,該芯層板100 係於一絕緣板101的兩側各具有〆第一導電層1〇2及第二導 電層1 0 3,且絕緣板1 〇 1設有電鍍導通孔^ 〇 1 a,使第一導電 層1 0 2與第二導電層1 〇 3得以電性導通。該導電層材質主要 係為金屬銅。 如第2圖所示,接著於該芯層板1 0 0之第一導電層1 0 2 上透過圖案化製程以形成基層電路層102a。 如第3圖所示,再於已形成基層電路層102 8之表面形 成一非導電性之絕緣層1 〇 4,且該絕緣層形成有複數個第 一開口 1 0 4 a以外露出部分基層電路層1 0 2 a。其中所述之第 一開口 1 0 4a係可形成為導電線路或導電盲孔之開口。而該 絕緣層104係為熱固性樹脂(Thermosetting re si η)或光顯 像樹脂(Photoimageable resin),若該絕緣層10 4為熱固 性樹脂則以雷射鑽孔形成開口 1 0 4a,又絕緣層1 0 4若為光 顯像樹脂則以曝光、顯影的方式形成開口 1 0 4 a。 又於該絕緣層1 〇 4及其開口 1 0 4 a表面形成防止金屬遷 移(Migration)與作為電鍍導電層之第一金屬阻障層 (Barrier layer)105,而該第一金屬阻障層10 5得為鉻 (Cr)、鎳(Ni)、始(Co)、妃(Pd)、鈕(Ta)、鈦(Ti)所構成 之群組之其中一者,且該金屬阻障層係可以物理氣相沈 積、化學氣相沈積、無電鍍或化學沈積等方式,例如濺錢 (Sputtering)、蒸鍍(Evaporation)、電弧蒸氣沈積(Arc vapor deposition)、粒子束濺鍍(i〇n beam17360 Quan 懋 .ptd Page 9 1221398 V. Schematic cross-sectional view of the process method of the invention description (5). As shown in FIG. 1, a core core board 100 is first provided, and the core board 100 is provided with a first conductive layer 102 and a second conductive layer 103 on each side of an insulating board 101, and The insulating plate 1 〇1 is provided with a plated-through hole ^ 〇1a, so that the first conductive layer 102 and the second conductive layer 103 can be electrically conducted. The material of the conductive layer is mainly metallic copper. As shown in FIG. 2, a patterning process is then performed on the first conductive layer 10 2 of the core board 100 to form a base circuit layer 102 a. As shown in FIG. 3, a non-conductive insulating layer 104 is formed on the surface of the base circuit layer 1028, and the insulating layer is formed with a plurality of first openings 104a to expose part of the base circuit. Layer 1 0 2 a. The first opening 104a is an opening that can be formed as a conductive line or a conductive blind hole. The insulating layer 104 is a thermosetting resin or a photoimageable resin. If the insulating layer 104 is a thermosetting resin, openings 1 0 4a are formed by laser drilling, and the insulating layer 1 If it is a light-developing resin, the opening 1 0 4 a is formed by exposure and development. A first metal barrier layer 105 is formed on the surface of the insulating layer 104 and the opening 104a to prevent metal migration, and the first metal barrier layer 10 is a conductive layer for electroplating, and the first metal barrier layer 10 5 may be one of the group consisting of chromium (Cr), nickel (Ni), origin (Co), princess (Pd), button (Ta), and titanium (Ti), and the metal barrier layer may be Physical vapor deposition, chemical vapor deposition, electroless plating, or chemical deposition, such as sputtering, evaporation, arc vapor deposition, particle beam sputtering

17360 全懋.ptd 第10頁 1221398 五、發明說明(6) sputtering)、雷射熔散沈積(Laser ablation deposition)、電漿促進之化學氣相沈積或無電鍍等方法 形成。 同時於室溫下金屬阻障層之電阻係數分別為··鎳(1 3 // Ω -cm)’ 鉻(6·84μ Ω -cm),始(6.24// Ω -cm),把(10. 8// Ω -cm)’ 组(11.5/ζ Ω -cm)’ 鈦(80// Ω -cm),因此該 些金屬阻障層均屬電之良導體,另銅之電阻值係數1. 6 7 3 // Ω - c m (參考 J 〇 h η,W i 1 e y & S ο n s,I n c 2 0 0 0年出版之 Μ 〇 d e r η E 1 e c ΐ r ο p 1 a t i n gp付錄)° 此外,發明人於先期研究中在一有機材質上濺鍍1 # 鉻層作為導電層,再以硫酸銅為電鍍液,可電鍍形成2 〇# 銅層。以此實驗基礎,可推知低電阻係數之鉻(Cr )、鎳 (Ni )、鈷(Co)、鈀(Pd)、钽(Ta)、鈦(Ti )作為導電層亦可 順利於其上電鍍形成銅材質之電路層。 如第4圖所示,接著在絕緣層1 〇 4之第一金屬阻障層 1 0 5上形成圖案化阻層1 〇 6,並在該阻層ΐ 〇 6上利用曝光、 择頁影寺方式形成有第二開口 1 〇 6 a,藉以外露出部分之金屬 阻障層1 〇 5,其中至少有一第二開口 ΐ 〇 6 a係對應至該第— 開口 1 0 4 a位置。 如笫5圖所示’接著以電鍍方式(e 1 ec t r op 1 a t i ng )對 該電路板進行電鍍製程,以於該第一開口 1 〇 4 a形成導電盲 孔,以及在該第二開口 1 〇 6 a中形成有電路層1 〇 7,使該電 路層1 0 7得以透過導電盲孔與第一導電層ΐ 〇 2上所形成的基 層電路層102 a電性導通,而電鍍成形之電路層1〇 7得為鋼17360 Quan 懋 .ptd Page 10 1221398 V. Description of the invention (6) sputtering), laser ablation deposition (laser ablation deposition), plasma-assisted chemical vapor deposition or electroless plating. At the same time, the resistivities of the metal barrier layer at room temperature are: · Nickel (1 3 // Ω -cm) 'Chromium (6 · 84μ Ω -cm), starting (6.24 // Ω -cm), and (10 8 // Ω -cm) 'group (11.5 / ζ Ω -cm)' titanium (80 // Ω -cm), so these metal barrier layers are all good conductors of electricity, and the coefficient of resistance of copper is 1 6 7 3 // Ω-cm (Reference J 〇h η, Wi i 1 ey & S ο ns, I nc 2000 Μ der η E 1 ec ΐ r ο p 1 atin gp Record) ° In addition, in the previous research, the inventor sputtered a 1 # chromium layer as a conductive layer on an organic material, and then used copper sulfate as a plating solution to form a 2 0 # copper layer by electroplating. Based on this experimental basis, it can be inferred that low-resistance chromium (Cr), nickel (Ni), cobalt (Co), palladium (Pd), tantalum (Ta), and titanium (Ti) can be smoothly plated on the conductive layer. Form a circuit layer made of copper. As shown in FIG. 4, a patterned resist layer 10 is then formed on the first metal barrier layer 105 of the insulating layer 104, and an exposure and a page shadow temple are selected on the resist layer 101 A second opening 1 0 6 a is formed, and at least one second opening ΐ 0 6 a corresponds to the position of the first opening 10 4 a by using the metal barrier layer 1 0 5 of the exposed portion. As shown in Fig. 5 ', the plating process is then performed on the circuit board by electroplating (e 1 ec tr op 1 ati ng) to form a conductive blind hole in the first opening 104a and a second opening in the second opening. A circuit layer 107 is formed in 106a, so that the circuit layer 107 can be electrically connected to the base circuit layer 102a formed on the first conductive layer 1002 through a conductive blind hole, and electroplated and formed. Circuit layer 107 is made of steel

Π360全懋.ptd 第11頁 1221398 五、發明說明(7) 金屬,且該電鍍製程係可藉由該芯層板1 0 0下表面之尚未 線路圖案化之第二導電層1 0 3、電鍍導通孔1 0 1 a、芯層板 上表面之基層電路層102a、及金屬阻障層10 5之具導電特 性,俾在進行電鍍時可作為電流傳導路徑,以使該第一開 口 104 a及第二開口 106 a中電鍍形成有一金屬層。 如第6圖所示,然後將該阻層1 0 6剝離,並以蝕刻方式 移除覆蓋於該阻層1 0 6下之金屬阻障層1 0 5,俾使電路層 1 0 7顯露出來。其中在移除部分之金屬阻障層1 0 5時,由於 其材質與電路層1 0 7不同,因此在移除時將得以避免同時 破壞電路層1 0 7結構’而維持原設計尺寸。 如第7圖所示,將該阻層1 0 6剝離後,該電路層1 0 7即 顯露出來,再於顯露的電路層1 0 7表面經由前述之電流傳 導路徑俾電鍍形成一第二金屬阻障層108,亦或可直接藉 由無電鍍方式形成該第二金屬阻層108;如此即可藉由第 一金屬阻障層1 0 5及第二金屬阻障層1 0 8以將該電路層1 0 7 完整包覆起來。 由於該以銅金屬電鍍形成之電路層10 7外表面包覆有 第一金屬阻障層10 5及第二金屬阻障層108,使以銅為主之 電路層1 0 7得藉由該第一金屬阻障層1 0 5及第二金屬阻障層 1 0 8阻絕銅遷移(C 〇 p p e r m i g r a t i〇η ),使該用以絕緣的絕 緣層1 0 4不至於因銅粒子擴散而滲入,如此即可使電路層 1 0 7之佈線方式更緊密,而不至於產生短路或干擾的情 況。 再者,該已形成第一金屬阻障層1 0 5、第二金屬阻障Π360 全懋 .ptd Page 11 1221398 V. Description of the invention (7) Metal, and the electroplating process can be carried out by the second conductive layer on the lower surface of the core board 100, which has not been patterned. 3. Plating The via hole 1 0 1 a, the base circuit layer 102 a on the core board surface, and the metal barrier layer 105 have conductive properties, and can be used as a current conduction path when electroplating, so that the first opening 104 a and A metal layer is formed in the second opening 106 a by electroplating. As shown in FIG. 6, the resist layer 106 is then peeled off, and the metal barrier layer 105 covered by the resist layer 106 is removed by etching, so that the circuit layer 107 is exposed. . Among them, when the part of the metal barrier layer 105 is removed, since the material is different from that of the circuit layer 107, the removal of the metal barrier layer 105 can be avoided to simultaneously destroy the structure of the circuit layer 107 and maintain the original design size. As shown in FIG. 7, after the resist layer 106 is peeled off, the circuit layer 107 is exposed, and a second metal is formed on the surface of the exposed circuit layer 107 through the aforementioned current conduction path and electroplating to form a second metal. The barrier layer 108, or the second metal barrier layer 108 may be directly formed by electroless plating; in this way, the first metal barrier layer 105 and the second metal barrier layer 108 can be used to The circuit layer 1 0 7 is completely covered. Because the outer surface of the circuit layer 10 7 formed by copper metal plating is covered with a first metal barrier layer 105 and a second metal barrier layer 108, the copper-based circuit layer 107 can pass through the first A metal barrier layer 105 and a second metal barrier layer 108 prevent copper migration (Coppermigrati), so that the insulating layer 104 used for insulation will not infiltrate due to the diffusion of copper particles, so That is, the wiring method of the circuit layer 107 can be made tighter, so as not to cause short circuit or interference. Furthermore, the first metal barrier layer 105 and the second metal barrier layer have been formed.

17360 全懋.ptd 第12頁 1221398 五、發明說明(8) 層108之電路層107上方得再形成另一絶緣層 述之步驟製作形戒另一具有第一金屬版障層' 障層之電路層,如此即可製作成多層電路板 而可再依上 第二金屬阻 如第8圖所示,之後即可在該多層電路板表面形成有 拒#干層2 0 〇,並使该拒銲層2 0 0形成有多數之開孔2 〇丨以外 露出包覆有第二阻障層10 8之電路層1〇7,該外露之電路層 1 0 7係可作為與外界電子裝置作電性導通之電性連接墊, 且該外露之電性連接墊表面可再形成有金屬保護層丨〇 g, 如鎳/金金屬層,以供導電元件,如銲球、銲線或金屬凸 塊等良好電性導接功能。該金屬保護層i 〇9係可利用無電 鍍(E 1 e c t r 〇 - 1 e s s )方式,以形成在該電性連接墊之外露表 面;亦或前述電流傳導路徑進行電鍍製程以在該電性連接 :备上電鑛形成金屬保護層。其中該金屬保護層得為金、 鎳、鈀、銀、錫、鎳/鈀、鉻/鈦、鎳/金、鈀/金及鎳/鈀/ 金所構成之群組之其中一者。 另於完成電鍍製程後可對該芯層板1 0 〇尚未線路圖案 化之第二導電層1 〇 3藉由蝕刻技術進行線路圖案化,即可 製得一具導電性阻障層之電路板。當然,本發明亦可同時 在該芯層板兩側同時進行增層製程以形成—對稱結構。 本發明中由於在電路層1〇 7表面形成有第一金屬阻障 層1 0 5及第二金屬阻障層1 〇 8包覆卩且隔,使電路板電路層 1 0 7相鄰線路之間的絕緣層1 〇 4或於電路板之層間絕緣層不 會有銅遷移的現象,因此電路板中絕緣層之設置將可更輕 薄,故得以製作更輕薄的多層電路板。17360 Quan 懋 .ptd Page 12 1221398 V. Description of the Invention (8) Another insulating layer can be formed on the circuit layer 107 of the layer 108 to form a circuit or another circuit with a first metal plate barrier layer. Layer, so that a multilayer circuit board can be fabricated and the second metal resistance can be added as shown in FIG. 8, and then a dry-rejection # 2 0 〇 can be formed on the surface of the multilayer circuit board, and the solder-rejection can be made. The layer 2 0 is formed with a plurality of openings 2 0. The circuit layer 10 7 covered with the second barrier layer 10 8 is exposed outside. The exposed circuit layer 10 7 can be used for electrical connection with external electronic devices. Conductive electrical connection pads, and a metal protective layer, such as a nickel / gold metal layer, may be further formed on the surface of the exposed electrical connection pads for conductive components such as solder balls, wires, or metal bumps. Good electrical conductivity. The metal protective layer i 〇09 can be formed by electroless plating (E 1 ectr 〇 1 ess) to form an exposed surface on the electrical connection pad; or the aforementioned current conduction path can be electroplated to perform electrical connection. : Prepare power ore to form a metal protective layer. The metal protective layer may be one of the group consisting of gold, nickel, palladium, silver, tin, nickel / palladium, chromium / titanium, nickel / gold, palladium / gold, and nickel / palladium / gold. In addition, after the electroplating process is completed, the second conductive layer 100 that has not been patterned on the core layer board 100 can be patterned with an etching technique to obtain a circuit board with a conductive barrier layer. . Of course, the present invention can also perform a build-up process on both sides of the core board at the same time to form a symmetrical structure. In the present invention, because the first metal barrier layer 105 and the second metal barrier layer 108 are formed on the surface of the circuit layer 107, the circuit board circuit layer 107 is adjacent to the circuit. There will be no copper migration between the insulating layer 104 and the interlayer insulating layer of the circuit board. Therefore, the arrangement of the insulating layer in the circuit board can be made lighter and thinner, so that a lighter and thinner multilayer circuit board can be produced.

17360 全懋.ptd 第13頁 1221398 五、發明說明(9) 又該第一金屬阻障層及第二金屬阻障層除了得以用來 防止金屬粒子遷移的現象外,據業界之習知技藝,當阻障 層為鉻時,亦可用以增強電路層與絕緣層之附著力,使該 電路層得緊密結合在絕緣層上以避免產生脫離的情況,因 此得有較佳的使用效果。 惟以上所述之具體實施例,僅係用以例釋本發明之特 點及功效,而非用以限定本發明之可實施範疇,在未脫離 本發明上揭之精神與技術範疇下,任何運用本發明所揭示 内容而完成之等效改變及修飾,均仍應為下述之申請專利 範圍所涵蓋。17360 Quan 懋 .ptd Page 13 1221398 V. Description of the invention (9) In addition to the first metal barrier layer and the second metal barrier layer can be used to prevent the migration of metal particles, according to the industry's know-how, When the barrier layer is chromium, it can also be used to enhance the adhesion between the circuit layer and the insulating layer, so that the circuit layer is tightly bonded to the insulating layer to avoid detachment, so it has a better use effect. However, the specific embodiments described above are only used to illustrate the features and effects of the present invention, rather than to limit the implementable scope of the present invention. Any application without departing from the spirit and technical scope of the present invention is disclosed. Equivalent changes and modifications made by the disclosure of the present invention should still be covered by the scope of patent application described below.

17360 全懋.ptd 第14頁 1221398 圖式簡單說明 法 製 板 路 電 之 層 障 阻 性 導 具 之 明 發 I本 明係 說圖 8 單; 至 簡1 圖 式第意 圖 示 t 視 及 以 圖 意 示 視 剖 之 板 路 電 層 多 知 習 係 圖 圖 ο 第第 圖 音5 示 之 象 現 移 遷 銅 之 板 路 ^00 ^ST 層 多 知 習 係 100 芯 層 板 101 絕 緣 板 101a 電 鍍 導 通 孔 102 第 一 導 電 層 102a 基 層 電 路 層 103 第 二 導 電 層 104 絕 緣 層 104a 第 一 開 V 105 第 一 金 屬 阻 障 層 106 阻 層 106a 第 二 開 π 107 電 路 層 108 第 — 金 屬 阻 障 層 109 金 屬 保 護 層 200 拒 銲 層 201 開 孔 300 芯 層 板 301 第 一 電 路 層 302 導 通 孔 303 絕 緣 層 304 盲 孔 305 第 二 電 路 層 306 銅 粒 子17360 Quan 懋 .ptd Page 14 1221398 Schematic description of the layered resistive guides of the circuit board of the French system I. This is illustrated in Figure 8; Schematic diagram of the electrical circuit of the circuit board of the multi-knowledge system. Picture 5: The image shown is now relocating to the copper circuit of the road. ^ 00 ^ ST-layer multi-knowledge system 100 core board 101 insulation board 101a electroplating Hole 102 First conductive layer 102a Base layer circuit layer 103 Second conductive layer 104 Insulating layer 104a First open V 105 First metal barrier layer 106 Resistive layer 106a Second open π 107 Circuit layer 108 First-Metal barrier layer 109 Metal Protective layer 200 Solder resist layer 201 Opening hole 300 Core board 301 First circuit layer 302 Via hole 303 Insulation layer 304 Blind hole 305 Second circuit layer 306 Copper particles

17360 全懋.ptd 第15頁17360 懋 .ptd Page 15

Claims (1)

1221398 六、申請專利範圍 1. 一種具導電性阻障層之電路板製法,係包括: 提供一芯層板,係於一絕緣板表面具有導電層, 且該絕緣板中設有電鍍導通孔,使該芯層板表面之導 電層得以電性導通; 將該芯層板之導電層形成基層電路層; 於已形成基層電路層之導電層表面形成一絕緣 層,且在該絕緣層形成有複數個得與基層電路層導通 之開口; 於該絕緣層及開口表面形成第一金屬阻障層; 於該第一金屬阻障層上形成圖案化阻層,且該阻 層具有多數開口以外露出部分第一金屬阻障層; 以電鍍方式在該阻層開口中形成圖案化電路層, 並使該圖案化電路層與基層電路層電性導通; 移除該阻層及其所覆蓋之第一金屬阻障層;以及 於顯露的圖案化電路層表面形成第二金屬阻障 層,而藉由第一、第二金屬阻障層將圖案化電路層包 覆隔絕。 2. 如申請專利範圍第1項之具導電性阻障層之電路板製 法,復包括於該已形成第一、第二金屬阻障層之圖案 化電路層上得再形成另一絕緣層,再依上述之步驟製 作形成另一具有第一、第二金屬阻障層之圖案化電路 層,俾以製作成多層電路板。 3. 如申請專利範圍第1或2項之具導電性阻障層之電路板 製法,復包括在該多層電路板表面形成有拒銲層,並1221398 VI. Application for Patent Scope 1. A method for manufacturing a circuit board with a conductive barrier layer includes: providing a core layer board having a conductive layer on the surface of an insulating board, and the insulating board being provided with a plated-through hole, Making the conductive layer on the surface of the core board electrically conductive; forming the conductive layer of the core board into a base circuit layer; forming an insulating layer on the surface of the conductive layer on which the base circuit layer has been formed, and forming a plurality of layers on the insulating layer An opening for conducting with the base circuit layer; forming a first metal barrier layer on the insulating layer and the surface of the opening; forming a patterned resist layer on the first metal barrier layer, and the resist layer having most exposed portions outside the opening A first metal barrier layer; forming a patterned circuit layer in the opening of the resist layer by electroplating, and electrically conducting the patterned circuit layer and the base circuit layer; removing the resist layer and the first metal it covers A barrier layer; and forming a second metal barrier layer on the surface of the exposed patterned circuit layer, and covering the patterned circuit layer with the first and second metal barrier layers. 2. If the method of manufacturing a circuit board with a conductive barrier layer according to item 1 of the scope of the patent application includes forming another insulating layer on the patterned circuit layer on which the first and second metal barrier layers have been formed, Then, according to the above steps, another patterned circuit layer having first and second metal barrier layers is formed to form a multilayer circuit board. 3. If the method of manufacturing a circuit board with a conductive barrier layer in the scope of patent application item 1 or 2 includes forming a solder resist layer on the surface of the multilayer circuit board, and 17360 全懋.ptd 第16頁 1221398 六、申請專利範圍 使該拒銲層形成有多數之開孔以外露出覆蓋於其下之 電路層作為電性連接墊部分,且該外露之電性連接墊 表面可再形成有金屬保護層。 4. 如申請專利範圍第3項之具導電性阻障層之電路板製 法,其中,該金屬保護層得為金、鎳、纪、銀、錫、 鎳/Ig、鉻/鈦、鎳/金、Ιε /金及鎳/把/金所構成之群 組之其中一者。 5. 如申請專利範圍第1或2項之具導電性阻障層之電路板 製法,其中,該芯層板一側之導電層係可先圖案化形 成基層電路層,並藉由該芯層板另一側尚未線路圖案 化之導電層與形成於該芯層板中之電鍍導通孔,俾在 進行電鍍時可作為電流傳導路徑,以在該芯層板單一 側形成增層電路。 6. 如申請專利範圍第1或2項之具導電性阻障層之電路板 製法,其中,該芯層板表面之導電層可同時圖案化形 成基層電路層,俾在該芯層板二側同時形成增層電 路。 7. 如申請專利範圍第1或2項之具導電性阻障層之電路板 製法,其中,該絕緣層係為熱固性樹脂,而該絕緣層 之開口係以雷射鑽孔形成。 8. 如申請專利範圍第1項之具導電性阻障層之電路板製 法,其中,該絕緣層係為光顯像樹脂,而該絕緣層之 開口係以曝光、顯影製程形成。 9. 如申請專利範圍第1項之具導電性阻障層之電路板製17360 Quan 懋 .ptd Page 16 1221398 6. The scope of the patent application makes the solder resist layer formed with a large number of openings and exposes the circuit layer covered thereunder as an electrical connection pad part, and the surface of the exposed electrical connection pad A metal protective layer may be further formed. 4. For the method for manufacturing a circuit board with a conductive barrier layer as described in the scope of patent application No. 3, wherein the metal protective layer may be gold, nickel, silver, silver, tin, nickel / Ig, chromium / titanium, nickel / gold , Iε / gold and nickel / barrel / gold. 5. For the method of manufacturing a circuit board with a conductive barrier layer according to item 1 or 2 of the scope of patent application, wherein the conductive layer on one side of the core board can be patterned to form a base circuit layer, and the core layer is used. The conductive layer that has not been patterned on the other side of the board and the plated through holes formed in the core board can be used as a current conduction path when plating is performed to form a build-up circuit on a single side of the core board. 6. For the method of manufacturing a circuit board with a conductive barrier layer according to item 1 or 2 of the scope of patent application, wherein the conductive layer on the surface of the core board can be patterned at the same time to form a base circuit layer, which is placed on two sides of the core board At the same time, a build-up circuit is formed. 7. For the method of manufacturing a circuit board with a conductive barrier layer according to item 1 or 2 of the patent application scope, wherein the insulating layer is a thermosetting resin, and the opening of the insulating layer is formed by laser drilling. 8. The method of manufacturing a circuit board with a conductive barrier layer according to item 1 of the patent application scope, wherein the insulating layer is a light developing resin, and the opening of the insulating layer is formed by an exposure and development process. 9. Circuit board system with conductive barrier layer such as the scope of patent application 17360 全懋.ptd 第17頁 1221398 六、申請專利範圍 法,其中,該圖案化電路層係為銅金屬。 1 0 .如申請專利範圍第1項之具導電性阻障層之電路板製 法,其中,該第一、第二金屬阻障層係為鉻(Cr )、鎳 (Ni)、銘(Co)、纪(Pd)、组(Ta)、鈦(Ti )所構成之群 組之其中一者。 1 1. 一種具導電性阻障層之電路板,包括: 一芯層板,其表面形成有基層電路層,且具有電 鍍導通孔,以電性導接該基層電路層; 至少一絕緣層,其係形成於該芯層板之基層電路 層上,且於該絕緣層中形成有複數個得與基層電路層 電性導通之導電盲孔; 至少一圖案化電路層,係形成在該絕緣層上;以 及 一金屬阻障層,係包覆住該圖案化電路層。 1 2 .如申請專利範圍第1 1項之具導電性阻障層之電路板, 復包括· 一拒銲層,該拒銲層形成有多數之開孔以外露出 覆蓋於其下之電路層之電性連接墊部分;以及 一金屬保護層,係形成於該外露之電性連接墊表 面〇 1 3 .如申請專利範圍第1 2項之具導電性阻障層之電路板, 其中,該金屬保護層得為金、錄、纪、銀、錫、錄/ I巴、鉻/鈦、鎳/金、Ιε /金及鎳/Ιε /金所構成之群組之 其中一者。17360 Quan 懋 .ptd Page 17 1221398 6. Application for Patent Scope Method, where the patterned circuit layer is copper metal. 10. The method for manufacturing a circuit board with a conductive barrier layer according to item 1 of the scope of patent application, wherein the first and second metal barrier layers are chromium (Cr), nickel (Ni), and inscription (Co) One of the groups consisting of, Ji (Pd), group (Ta), and titanium (Ti). 1 1. A circuit board with a conductive barrier layer, comprising: a core layer board having a base layer circuit layer formed on its surface and having plated through holes for electrically connecting the base layer circuit layer; at least one insulating layer, It is formed on the base circuit layer of the core board, and a plurality of conductive blind holes are formed in the insulation layer to be electrically connected with the base circuit layer. At least one patterned circuit layer is formed on the insulation layer. And a metal barrier layer covering the patterned circuit layer. 1 2. For a circuit board with a conductive barrier layer as described in item 11 of the scope of the patent application, it further includes a solder resist layer formed with a large number of openings and exposed circuit layers covering the solder resist layer. An electrical connection pad portion; and a metal protective layer formed on the surface of the exposed electrical connection pad. 013. For example, a circuit board with a conductive barrier layer as described in item 12 of the patent application scope, wherein the metal The protective layer may be one of the group consisting of gold, copper, silver, silver, tin, copper / Ibar, chromium / titanium, nickel / gold, Ιε / gold, and nickel / Ιε / gold. 17360 全懋.ptd 第18頁 1221398 六、申請專利範圍 1 4.如申請專利範圍第1 1項之具導電性阻障層之電路板, 其中,該絕緣層係為熱固性樹脂。 1 5 .如申請專利範圍第1 1項之具導電性阻障層之電路板, 其中,該絕緣層係為光顯像樹脂。 1 6 .如申請專利範圍第1 1項之具導電性阻障層之電路板, 其中,該圖案化電路層係為銅金屬。 1 7.如申請專利範圍第1 1項之具導電性阻障層之電路板, 其中,該金屬阻障層係為鉻(C r )、鎳(N i )、姑(C 〇 )、 鈀(Pd)、钽(Ta)、鈦(Ti )所構成之群組之其中一者。17360 Quan 懋 .ptd Page 18 1221398 6. Scope of Patent Application 1 4. For the circuit board with conductive barrier layer as described in item 11 of the patent application scope, the insulation layer is a thermosetting resin. 15. The circuit board with a conductive barrier layer according to item 11 of the scope of patent application, wherein the insulating layer is a light developing resin. 16. The circuit board with a conductive barrier layer according to item 11 of the scope of patent application, wherein the patterned circuit layer is copper metal. 1 7. The circuit board with a conductive barrier layer according to item 11 of the scope of patent application, wherein the metal barrier layer is chromium (C r), nickel (N i), palladium (C 〇), palladium (Pd), tantalum (Ta), or titanium (Ti). 17360 全懋.ptd 第19頁17360 懋 .ptd Page 19
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN114980477A (en) * 2021-02-18 2022-08-30 合肥鑫晟光电科技有限公司 Back plate, backlight source, illuminating device and display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114980477A (en) * 2021-02-18 2022-08-30 合肥鑫晟光电科技有限公司 Back plate, backlight source, illuminating device and display device

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