• 1298940 '嬗 九、發明說明： ' 【發明所屬之技術領域】 • 本發明係有關於一種形成半導體封裝基板阻障層的方 法’尤才曰一種間化無電鍵導線（n〇n piaHng—ηne，NPL) 製程之形成半導體封裝基板阻障層的方法，其只需要一道 微影製程’因此可廣泛應用於微小錫球間距（fine ball Pitch)之設計，以縮短製程時間並提高製程良率。 【先前技術】 隨著電子產品輕薄短小化的發展趨勢，半導體晶片半導 體封裝基板（或稱IC載板）製造業者亦面臨著製程上的許多 關鍵處。其中’於基板表面會形成若干由導電線路延伸之 電性接觸墊’以作為電子訊號或電源傳輸之路徑，而通常 在電性接觸墊之表面，會覆上一鎳/金（Ni/Au)層。該等 電性接觸墊，如半導體晶片半導體封裝基板之打線墊，即 1塾體表面覆上一層鎳/金層，於進行晶片封裝打金線 日守丄金線與基板之打線墊皆為金屬金之材質，而有利於兩 者儿成電性麵合結構；又該等電性接觸墊如半導體封裝基 板之=球塾，即於墊體表面覆上一層鎳/金層，以使錫球 塾之導電塾體（通常為金屬銅）不易因外界環境影響而氧 化，以提高封装錫球之電性連接品質。 圖一 A至圖一 H係為一習知形成半導體封裝基板阻障層 的方ΐ之不意圖。首先提供—基板1〇0 ,該基板100已完 成斤系之如#又製程’即已包括内層線路導通（interlayer connect)形成於其巾。並以微影、㈣等方式，在該基板 6 '1298940• 1298940 '嬗九,发明说明: ' [Technical field to which the invention pertains] • The present invention relates to a method for forming a barrier layer of a semiconductor package substrate 'Using a type of electrically-free conductor wire (n〇n piaHng-ηne) , NPL) The method of forming a barrier layer of a semiconductor package substrate, which requires only a lithography process, and thus can be widely applied to the design of a fine ball pitch to shorten the process time and improve the process yield. [Prior Art] With the trend of thinner and lighter electronic products, manufacturers of semiconductor wafer semiconductor package substrates (or IC carriers) are also facing many key points in the process. Wherein, 'a plurality of electrical contact pads extending from the conductive lines are formed on the surface of the substrate as a path for electronic signal or power transmission, and usually a nickel/gold (Ni/Au) layer is applied on the surface of the electrical contact pads. Floor. The electrical contact pads, such as the wire pad of the semiconductor chip semiconductor package substrate, that is, the surface of the first body is covered with a layer of nickel/gold, and the wire pad for the wafer package gold wire and the substrate is metal. The material of gold is beneficial to the two sides to form an electrical surface structure; and the electrical contact pads such as the semiconductor package substrate = ball, that is, a layer of nickel/gold is coated on the surface of the pad body to make the solder ball The conductive body of the crucible (usually metallic copper) is not easily oxidized by the external environment to improve the electrical connection quality of the packaged solder ball. Figure 1A to Figure 1H is a conventional method for forming a barrier layer of a semiconductor package substrate. First, a substrate 1 〇 0 is provided, and the substrate 100 has been completed, such as a process, which includes an inner layer connection formed in the towel. And in the form of lithography, (four), etc., on the substrate 6 '1298940
100之兩側形成線路圖案層1〇5,如圖_ A所示。接著，在 圖=B巾，於基板100兩側形成導電層11()，以作為後述 $仃電鍍之電流傳導路徑。在圖一 c +，形成第一光阻層 115以覆蓋該導電層110與該基板1〇〇。直中，該第—光阻 们15具有開孔丨⑸’以露出開孔下方為導電層山所覆 盍之電性接觸塾_。接著，移除未被該第一光阻層115 =蓋之導電層，此時該光阻層開孔區⑽底緣殘露有部 :=電層11〇2,如圖- D所示。在圖_E中，於基板1〇〇 =形成第二光阻層12〇，該第二光阻層⑽覆住殘露於 先阻層開孔區1151之導電層⑽。接著，對該基板 入00進行電鍍鎳/金步驟，使得各電性接觸塾腕外 讀上鎳/金層125，如圖-F所示。在圖一 G中，移 j阻層120與第一光阻層115及其所覆蓋之導電層山， 传線路圖案層105上之電性接觸墊1G51整個外側皆 金層125。最後，在基板⑽兩側覆上一絕緣保彻 ，係如綠漆（Solder Mask)，以完成基板1〇〇之表 護，如圖一 Η所示。 保 。然而，上述製程需要使用兩層光阻層以及兩道微影制 私’除了有礙產能之提升，而於半導體㈣基板 = 錫球間距（fine ball pitGh)之製程時，繁複賴影製= 不利於微小錫球間距之製程需求。 ’、 因此，亟需一種可以簡化上㈣程之形成半導體 基板阻障層的方法，以縮短製程時間並提高製程良率。衣 【發明内容】 7 1298940 有鑑於習知技術之缺失，本發明之一主要目的在於提 - 供一種形成半導體封裝基板阻障層的方法，可簡化習知無 _ 電鍍導線電鍍阻障層製程繁複之微影程序，以縮短製程時 間並提高製程良率。 本發明之另一目的在於提供一種形成半導體封裝基 板阻障層的方法，只需要一道微影製程，並可達成微小錫 球間距之設計的需求。 為達上述目的，本發明提供一種形成半導體封裝基板 • 阻障層的方法，包括以下步驟： 提供一已完成圖案化線路製程之電路板，該電路板之 置晶側與球側形成有圖案化線路層，以及複數個 電鍍導通孔貫穿該電路板並導通電路板置晶側與 球側之圖案化線路層，並各以一絕緣保護層，形 成於該電路板之置晶侧與球侧表面；其中該絕緣 保護層復形成有複數個第一開口，曝露出該圖案 化線路層之部分以形成複數個金屬連接墊，且該 • 置晶側與該球侧之金屬連接墊係可電性導通； 形成導電層，分別覆蓋該置晶側與該球側之該絕緣保 護層與該複數個金屬連接墊； 形成一第一阻層，覆蓋該球側之該導電層，並且移除 ^ 該置晶側之該導電層； - 移除該第一阻層； 形成一第二阻層，覆蓋該球側之該導電層，並藉由微 影製程形成複數個第二開口，以暴露出該球側金 屬連接墊； 1298940 以電鍍方式形成阻障層於該置晶側與該球側之該金 - 屬連接墊；以及 移除該球側之該絕緣保護層上之該第二阻層以及該 第二阻層所覆蓋之導電層。 本發明更提供一種形成半導體封裝基板阻障層的方 法，包括以下步驟： 提供一已完成圖案化線路製程之電路板，該電路板之 置晶側與球側形成有圖案化線路層，以及複數個 • 電鍍導通孔貫穿該電路板並導通電路板置晶側與 球側之圖案化線路層，並各以一絕緣保護層，形 成於該電路板之置晶側與球側表面；其中該絕緣 保護層復形成有複數個第一開口，曝露出該圖案 化線路層之部分以形成複數個金屬連接墊，且該 置晶側與該球侧之金屬連接墊係可電性導通； 形成一第一阻層，覆蓋該置晶側之該絕緣保護層； 形成導電層，分別覆蓋該置晶側之該第一阻層與該球 參 側之該絕緣保護層與該複數個金屬連接墊； 移除該第一阻層以及該第一阻層上之該導電層； 形成一第二阻層，覆蓋該球側之該導電層，並藉由微 影製程形成複數個第二開口，以暴露出該球側金 屬連接墊； - 以電鍍方式形成阻障層於該置晶側與該球側之該金 屬連接墊；以及 移除該球側之該絕緣保護層上之該第二阻層以及該 第二阻層所覆蓋之導電層。 9 1298940 較隹者，該阻障層係可為一鎳/金金屬層。 較隹者，該電路板係為一已完成線路圖案化製程之雙爲 電路板或一多層電路板。 曰 較隹者，該電鍍導通孔係以機械鑽孔及電鍍方式形戍。 較隹者，該第一阻層係為一乾膜或液態光阻。 較隹者，該第二阻層係為一乾膜或液態光阻。 較隹I，該導電層係包括錫（Sn)、銅（Cu)、鉻（Cr)、 纪（Pd)、鎳（Ni)、錫/鉛（Sn/Pb)與其合金之一者。、 丨 較隹奢，該導電層係以濺鍍、蒸鍍、無電電鍍及化學洗 積之/者形成。 較隹奢，該導電層係包括導電高分子。 較隹I，該第二開口係等於或小於該第一開D者。 【實施方式】 為使貴審查委員能對本發明之特徵、目的及功能有 更進一步的認知與暸解，茲配合圖式詳細說明如後。 • 圖二A至圖二G為本發明較佳具體實施例之形成半導 體封裝基板阻障層的方法之示意圖。 首先，如圖二A所示，提供一基板200，其已完成所 需之前段製程，因此包括··已完成線路圖案化製程之電路 板215，該電路板215之兩侧形成有圖案化線路層208，以 及複數個電鑛導通孔210貫穿該電路板215並導通電路板 215兩側之圖案化線路層208 ;絕緣保護層220，該絕緣保 護層220通常<為防焊材料例如綠漆，形成於該基板2〇〇 之該置晶側2 01與該球侧2 〇 2表面上’以覆蓋遠圖案化線 •1298940 路層208及電鍍導通孔210 ;該絕緣保護層220以微影方 • 式形成有複數個第一開口 225 ’以曝露出電路板215兩側 圖案化線路層208之部份作為金屬連接墊230。在本具體 實施例中，該電路板215係為一已完成線路圖案化製程之 雙層電路板或一多廣電路板。此外’電鍵導通孔210係以 機械鑽孔及電鍍一金屬層形成。該置晶側與該球侧之金屬 連接墊230係可電性導通。 接著，形成導電層235 ’該導電層235分別覆蓋該置 φ 晶側201與該球側2〇2之該絕緣保護層220與該複數個金 屬連接墊230 ’如圖一 B所示。在本具體實施例中’該導 電層235主要係作為後述進行電鑛之電流傳導路徑’其包 括錫（Sn)、銅（Cu)、鉻（Cr)、鈀（Pd)、鎳（Ni)、錫/ 鉛（Sn/Pb)與其合金之一者，並且以濺鍍、蒸鍍、無電電 鍍及化學沈積之一者形成。此外，該導電層235亦可包含 導電高分子，而以旋轉塗佈（spin coating)、喷墨印刷 (ink-jet printing)、網印（screen printing)或壓印 參 （imprinting)等方式形成。惟本發明並不以上述材質與 手段為限，任何具有本技術領域之一般技藝者當能構思出 其他變化之材質與手段。 在圖二c中’形成一第〜阻層24〇，覆蓋該球側202 ‘‘之該導電層235，並且移除該置晶側201之該導電層235。 ，在本具體實施例中，該第一卩且層24〇係為一乾膜或液態光 ' 阻。 接著’移除該第-阻層24〇，以曝露出該球側202之 導電層235，如圖二D所示。 1298940 ’ 在圖二E中，形成一第二阻層245，覆蓋該球側202 之該導電層235,並藉由微影製程形成複數個第二開口 250，以暴露出該球侧202金屬連接墊230。在本具體實施 例中，該第二阻層245係為一乾膜或液態光阻。此外，該 第二開口 250係可等於或小於該第一開口 225者。 接著，以電鍍方式形成阻障層255於該置晶側201與 該球侧202之該金屬連接墊230上，如圖二F所示。在本 具體實施例中，該阻障層255係可為一鎳/金金屬層。 • 最後，移除該球側202之該絕緣保護層220上之該第 二阻層245以及該第二阻層245所覆蓋之導電層235，以 獲得如圖二G之結構。 另外，本發明亦提供另一具體實施例之方法，如圖三A 至圖三G所示。 首先，在圖三A中，提供一基板200，其係相同於圖二 A之基板，故不予贅述。 接著，形成一第一阻層340，覆蓋該置晶側2〇1上之該 # 絕緣保護層220，如圖三B所示。在本具體實施例中，該 第一阻層340係為一乾膜或液態光阻。 在圖三C中，形成導電層335，分別覆蓋該置晶侧2〇1 之該第一阻層340與該球側202之該絕緣保護層220與該 ， 複數個金屬連接墊230。在本具體實施例中，該導電層335 主要係作為後述進行電鍍之電流傳導路徑，其包括錫 (811)、銅（(]11)、絡（(]1')、纪（？(1)、鎳（]^〇、錫/叙（811/卩5) 與其合金之一者，並且以濺鍍、蒸鍍、無電電鍍及化學沈 積之一者形成。此外，該導電層335亦可包含導電高分子， 12 * 1298940 % 而以旋轉塗佈、喷墨印刷、網印或壓印等方式形成。惟本 . 發明並不以上述材質與手段為限，任何具有本技術領域之 一般技藝者當能構思出其他變化之材質與手段。 接著，移除該第一阻層340以及該第一阻層340上之該 導電層335，如圖三D所示。 在圖三E中，形成一第二阻層345，覆蓋該球側202 之該導電層335,並藉由微影製程形成複數個第二開口 350,以暴露出該球側金屬連接墊230。在本具體實施例中， φ 該第二阻層345係為一乾膜或液態光阻。此外，該第二開 口 350係可等於或小於該第一開口 225者。 接著，以電鍍方式形成阻障層355於該置晶側201與 該球側202之該金屬連接墊230，如圖三F所示。在本具 體實施例中，該阻障層355係可為一鎳/金金屬層。 最後，移除該球側202之該絕緣保護層220上之該第 二阻層345以及該第二阻層245所覆蓋之導電層335，以 獲得如圖三G之結構。 φ 上述本發明之形成半導體封裝基板阻障層的方法雖然 係以雙層電路板加以說明，然而其也可以應用於包括增層 或壓合製程所形成之多層電路板。 綜上所述，當知本發明之形成半導體封裝基板阻障層的 ^ 方法，係為只需要一道微影製程之簡化無電鍍導線製程的 ， 方法，因此可廣泛應用於微小錫球間距（fine ball pitch) " 之設計，以縮短製程時間並提高製程良率。故本發明實為 一富有新穎性、進步性，及可供產業利用功效者，應符合 專利申請要件無疑，爰依法提請發明專利申請，懇請貴 13 1298940 審查委員早曰賜予本發明專利，實感德便。 . 惟以上所述者，僅為本發明之較佳實施例而已，並非用 來限定本發明實施之範圍，即凡依本發明申請專利範圍所 述之形狀、構造、特徵、精神及方法所為之均等變化與修 飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 圖一 A至圖一 Η係為一習知形成半導體封裝基板阻障 參 層的方法之示意圖； 圖二Α至圖二G係為本發明較佳具體實施例之形成半 導體封裝基板阻障層的方法之示意圖；以及 圖三A至圖三G係為本發明另一具體實施例之形成半 導體封裝基板阻障層的方法之示意圖。 【主要元件符號說明】 100基板 φ 105線路圖案層 1051 電性接觸墊 110 導電層 1102 導電膜殘露部分 ^ 115 第一光阻層 1151 光阻層開孔 120第二光阻層 125鎳/金層 130 絕緣保護層 14 1298940Line pattern layers 1〇5 are formed on both sides of 100, as shown in FIG. Next, in Fig. B, a conductive layer 11 () is formed on both sides of the substrate 100 to serve as a current conduction path for plating. In Fig. 1 c + , a first photoresist layer 115 is formed to cover the conductive layer 110 and the substrate 1 . In the straight middle, the first photoresist 15 has an opening 丨(5)' to expose an electrical contact 塾_ which is covered by the conductive layer below the opening. Then, the conductive layer not covered by the first photoresist layer 115 is removed. At this time, the bottom edge of the opening region (10) of the photoresist layer is exposed with a portion: = electrical layer 11 〇 2, as shown in FIG. In FIG. _E, a second photoresist layer 12 is formed on the substrate 1 〇〇, and the second photoresist layer (10) covers the conductive layer (10) remaining in the opening region 1151 of the first resist layer. Next, a nickel/gold plating step is performed on the substrate 00 so that the nickel/gold layer 125 is read out of each of the electrical contacts, as shown in Fig. -F. In FIG. 1G, the resistive layer 120 and the first photoresist layer 115 and the conductive layer covered thereon are disposed on the outer side of the electrical contact pad 1G51 on the line pattern layer 105. Finally, an insulating barrier is applied to both sides of the substrate (10), such as a green paint (Solder Mask), to complete the substrate 1 表, as shown in FIG. Guaranteed. However, the above process requires the use of two layers of photoresist layers and two lithography processes, in addition to hindering the increase in productivity, and in the process of semiconductor (four) substrate = fine ball pit Gh, the complicated film system = unfavorable The process requirements for tiny solder ball pitch. Therefore, there is a need for a method for simplifying the formation of a semiconductor substrate barrier layer in the upper (four) process to shorten the process time and improve the process yield. [Invention] 7 1298940 In view of the lack of the prior art, one of the main objects of the present invention is to provide a method for forming a barrier layer of a semiconductor package substrate, which can simplify the complicated process of electroplating barrier plating. The lithography program to shorten the process time and improve the process yield. Another object of the present invention is to provide a method of forming a barrier layer for a semiconductor package substrate that requires only a lithography process and achieves the need for a tiny pitch of solder balls. To achieve the above object, the present invention provides a method of forming a semiconductor package substrate and a barrier layer, comprising the steps of: providing a circuit board having completed a patterned circuit process, wherein the crystal side and the ball side of the circuit board are patterned a circuit layer, and a plurality of plating vias penetrating the circuit board and conducting the patterned circuit layer on the crystal side and the ball side of the circuit board, and each of the insulating layer is formed on the crystal side and the ball side surface of the circuit board Wherein the insulating protective layer is formed with a plurality of first openings exposing portions of the patterned wiring layer to form a plurality of metal connection pads, and the metal connection pads of the crystal side and the ball side are electrically Conducting a conductive layer covering the insulating protective layer and the plurality of metal connection pads on the side of the crystal and the ball, respectively; forming a first resist layer covering the conductive layer on the ball side, and removing Forming the conductive layer on the crystallized side; removing the first resist layer; forming a second resist layer covering the conductive layer on the ball side, and forming a plurality of second openings by a lithography process to expose the a ball-side metal connection pad; 1298940 is formed by electroplating to form a barrier layer on the crystal side and the ball side of the gold-based connection pad; and removing the second resistance layer on the insulating layer of the ball side and a conductive layer covered by the second resist layer. The present invention further provides a method for forming a barrier layer of a semiconductor package substrate, comprising the steps of: providing a circuit board having completed a patterned circuit process, wherein a patterned circuit layer is formed on a crystal side and a ball side of the circuit board, and a plurality of The electroplated via hole penetrates the circuit board and turns on the patterned circuit layer on the crystal side and the ball side of the circuit board, and each has an insulating protective layer formed on the crystal side and the ball side surface of the circuit board; wherein the insulating layer The protective layer is formed with a plurality of first openings, the portions of the patterned circuit layer are exposed to form a plurality of metal connection pads, and the metal connection pads of the crystal side and the ball side are electrically conductive; a resist layer covering the insulating protective layer on the crystallizing side; forming a conductive layer covering the first resistive layer on the crystallizing side and the insulating protective layer on the side of the ball and the plurality of metal connecting pads; And forming the first resist layer and the conductive layer on the first resist layer; forming a second resist layer covering the conductive layer on the ball side, and forming a plurality of second openings by the lithography process to expose a ball-side metal connection pad; - forming the metal connection pad of the barrier layer on the crystallizing side and the ball side by electroplating; and removing the second resist layer on the insulating protective layer on the ball side and the first A conductive layer covered by a second resist layer. 9 1298940 More preferably, the barrier layer can be a nickel/gold metal layer. More preferably, the board is a circuit board or a multi-layer board that has completed the line patterning process.隹 More than that, the plated vias are mechanically drilled and plated. More preferably, the first resistive layer is a dry film or a liquid photoresist. More preferably, the second resistive layer is a dry film or a liquid photoresist. Compared to 隹I, the conductive layer includes one of tin (Sn), copper (Cu), chromium (Cr), cadmium (Pd), nickel (Ni), tin/lead (Sn/Pb) and alloys thereof.丨 More luxurious, the conductive layer is formed by sputtering, evaporation, electroless plating and chemical cleaning. More luxurious, the conductive layer includes a conductive polymer. The second opening is equal to or smaller than the first opening D. [Embodiment] In order to enable the reviewing committee to have a further understanding and understanding of the features, objects and functions of the present invention, the detailed description will be made in conjunction with the drawings. 2A to 2G are schematic views showing a method of forming a barrier layer of a semiconductor package substrate in accordance with a preferred embodiment of the present invention. First, as shown in FIG. 2A, a substrate 200 is provided, which has completed the required previous stage process, and thus includes a circuit board 215 that has completed the line patterning process, and patterned circuits are formed on both sides of the circuit board 215. The layer 208, and the plurality of electrowinning vias 210 extend through the circuit board 215 and conduct the patterned circuit layer 208 on both sides of the circuit board 215; the insulating protective layer 220 is generally <for solder resist material such as green lacquer Forming on the crystallizing side 2 01 of the substrate 2 and the surface of the ball side 2 〇 2 to cover the far-patterned line • 1298940 road layer 208 and the plating via 210; the insulating protective layer 220 is lithographic A plurality of first openings 225' are formed to expose portions of the patterned wiring layer 208 on both sides of the circuit board 215 as metal connection pads 230. In this embodiment, the circuit board 215 is a two-layer circuit board or a multi-wide circuit board that has completed the line patterning process. Further, the 'keylet via hole 210 is formed by mechanical drilling and plating a metal layer. The metal connection pad 230 on the crystallizing side and the ball side is electrically conductive. Then, the conductive layer 235 is formed. The conductive layer 235 covers the insulating protective layer 220 of the φ crystal side 201 and the ball side 2 〇 2 and the plurality of metal connection pads 230 ′ as shown in FIG. In the present embodiment, the conductive layer 235 is mainly used as a current conducting path for conducting electric ore as described later, and includes tin (Sn), copper (Cu), chromium (Cr), palladium (Pd), nickel (Ni), One of tin/lead (Sn/Pb) and its alloy, and is formed by one of sputtering, evaporation, electroless plating, and chemical deposition. Further, the conductive layer 235 may also include a conductive polymer, and is formed by spin coating, ink-jet printing, screen printing, or imprinting. However, the present invention is not limited to the above materials and means, and any material and means that can be conceived by those skilled in the art can be conceived. A resistive layer 24 is formed in FIG. 2c to cover the conductive layer 235 of the ball side 202 and remove the conductive layer 235 of the crystallized side 201. In this embodiment, the first layer and the layer 24 are a dry film or a liquid light. The first resistive layer 24 is then removed to expose the conductive layer 235 of the ball side 202, as shown in Figure 2D. 1298940' In FIG. 2E, a second resist layer 245 is formed to cover the conductive layer 235 of the ball side 202, and a plurality of second openings 250 are formed by a lithography process to expose the ball side 202 metal connection. Pad 230. In this embodiment, the second resist layer 245 is a dry film or a liquid photoresist. Further, the second opening 250 may be equal to or smaller than the first opening 225. Next, a barrier layer 255 is formed on the metal connection pad 230 of the crystal side 201 and the ball side 202 by electroplating, as shown in FIG. In this embodiment, the barrier layer 255 can be a nickel/gold metal layer. Finally, the second resist layer 245 on the insulating protective layer 220 of the ball side 202 and the conductive layer 235 covered by the second resist layer 245 are removed to obtain the structure as shown in FIG. In addition, the present invention also provides a method of another embodiment, as shown in FIG. 3A to FIG. 3G. First, in FIG. 3A, a substrate 200 is provided, which is the same as the substrate of FIG. 2A, and thus will not be described again. Next, a first resist layer 340 is formed to cover the # insulating protective layer 220 on the crystallizing side 2〇1, as shown in FIG. 3B. In this embodiment, the first resist layer 340 is a dry film or a liquid photoresist. In FIG. 3C, a conductive layer 335 is formed to cover the first resist layer 340 of the crystallizing side 2〇1 and the insulating protective layer 220 of the ball side 202, and the plurality of metal connection pads 230. In this embodiment, the conductive layer 335 is mainly used as a current conduction path for electroplating, which includes tin (811), copper ((11), and ((1)), (?) Nickel (1), tin/s (811/卩5) and one of its alloys, and formed by one of sputtering, evaporation, electroless plating, and chemical deposition. In addition, the conductive layer 335 may also contain conductive The polymer, 12 * 1298940%, is formed by spin coating, ink jet printing, screen printing or embossing, etc. However, the invention is not limited to the above materials and means, and any one of ordinary skill in the art Other materials and means can be conceived. Then, the first resist layer 340 and the conductive layer 335 on the first resist layer 340 are removed, as shown in FIG. 3D. In FIG. 3E, a first The second resist layer 345 covers the conductive layer 335 of the ball side 202 and forms a plurality of second openings 350 by a lithography process to expose the ball side metal connection pads 230. In this embodiment, φ The second resist layer 345 is a dry film or a liquid photoresist. Further, the second opening 350 may be equal to or smaller than the first The opening 225. Next, the metal connection pad 230 of the barrier layer 355 on the crystallizing side 201 and the ball side 202 is formed by electroplating, as shown in FIG. 3F. In the specific embodiment, the barrier layer The 355 series can be a nickel/gold metal layer. Finally, the second resist layer 345 on the insulating protective layer 220 of the ball side 202 and the conductive layer 335 covered by the second resist layer 245 are removed to obtain Figure 3. Structure of G. φ The above method for forming a barrier layer of a semiconductor package substrate of the present invention is described by a two-layer circuit board, but it can also be applied to a multilayer circuit board formed by a build-up or press-bond process. In summary, the method for forming a barrier layer of a semiconductor package substrate of the present invention is a method for simplifying the electroless-plated wire process which requires only one lithography process, and thus can be widely applied to fine solder ball pitch (fine Ball pitch) " is designed to shorten the process time and improve the process yield. Therefore, the invention is a novel, progressive, and available for industrial use, should meet the requirements of the patent application, undoubtedly, In the case of the patent application, the stipulations of the present invention are only for the purpose of limiting the scope of the present invention, that is, the scope of the present invention is not limited to the scope of the present invention. Equivalent changes and modifications of the shapes, structures, features, spirits and methods described in the scope of the present invention should be included in the scope of the present invention. [Figure 1A to Figure 1 Η is a schematic diagram of a method for forming a barrier layer of a semiconductor package substrate; FIG. 2A to FIG. 2G are schematic diagrams showing a method for forming a barrier layer of a semiconductor package substrate according to a preferred embodiment of the present invention; 3A to 3G are schematic views of a method of forming a barrier layer of a semiconductor package substrate according to another embodiment of the present invention. [Main component symbol description] 100 substrate φ 105 line pattern layer 1051 electrical contact pad 110 conductive layer 1102 conductive film residual portion ^ 115 first photoresist layer 1151 photoresist layer opening 120 second photoresist layer 125 nickel / gold Layer 130 insulating protective layer 14 1298940
200 基板 201 置晶側 202 球側 208 圖案化線路層 210 電鍛導通孔 215 電路板 220 絕緣保護層 225 第一開口 230 金屬連接墊 235 導電層 240 第一阻層 245 第二阻層 250 第二開口 255 阻障層 335 導電層 340 第一阻層 345 第二阻層 350 第二開口 355 阻障層200 substrate 201 crystallizing side 202 ball side 208 patterned circuit layer 210 electrically etched via 215 circuit board 220 insulating protective layer 225 first opening 230 metal connection pad 235 conductive layer 240 first resistive layer 245 second resistive layer 250 second Opening 255 barrier layer 335 conductive layer 340 first resist layer 345 second resist layer 350 second opening 355 barrier layer