1307936 修正日期：97.12.31 第5110919喊專利說明書修正本 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種半導體元件及其製造方法，而特 耗特：於：有：低介電常數之複合介電層、低熱消 .和队 间應力遷移阻障以及高機械強度之溝槽及介層 固結構。 曰 【先前技術】 :導體元件的製造技術通常包括一以系列製程步驟 、° a、工作部件上製造大量的元件。半導體製程中， =矽作為基底’將其切割成適當的形狀，通常切成 ’稱之為晶圓。接著將純矽晶圓以硼或磷進行換 2再以—系列之製程步驟在晶圓的表面或其電 日日脰、電容或其他電子元件。 电 後，成複數個相同晶粒。製程結束 -外部ΐ:連接，將其包覆至一硬塑膠材料中’並提供 内部各個元件後，便完成晶片的製作。 蹊曰:杜匕括了數以萬計的元件用以形成功能性電 如第通。傳統之内連線結構 之截面圖！”R，第1A圖顯示半導體元件⑽ 圖，罘1B圖顯示半導體元件1〇〇 直軸轉90度之截面圖 負者弟1A圖垂 上，包括第—電路及nm成在基底101 罘一电路兩電路需加以導通。為 0503-A31345TWF2/Jeff 5 1307936 第95110919號專利說明書修正本 修正曰期：97.1231 了方便起見’第-線路及第二線路分別為圖中所 一主動區Π)5及第二主動區u〇，形成在基底ι〇ι上= 一層結構⑽中。值得注意的是，在此所述之「半導: ::丄可代表-完整的功能元件，但也可用來代表其; 「中填入導體115以電性連接第-主動區 ⑽及弟二主動區11G。導體115形成在内連線層⑻ 較佳為銘或銅， 中 為了碟保導體出不與半導體元件其 觸，在内連線層⑽的剩餘部分是以介電材料 導體115，(第1A及第1B圖雖未顯*， ： ΓΓ層或另—内連線層)，為了與主動區域電= 同時也填入如同導體115相同之導的 J，在製造如半導體元件之結構時，事先形成介電：： 層再填滿導電材料。如第1Α及第四圖所示成介;= 及118分別延伸至主動區域105及11〇。 曰 第1Α及第1Β圖所示之内連線結構 導體元件結構。當晶片中的電 :夕種半 結構逐漸縮小，伴隨而來的是：：加，而封裝 械強度等問題，熱桃、應力遷移以及機 因此，業界亟需要一種解決上述問題的結構與方法。 【發明内容】 0503-A31345TWF2/Jeff 6 1307936 第95110919號專利說明書佟正本 有鑑於此，θ本發明的日_ 修正日期m3! 製程之内連線結:發明的目的在於提供—種用於半導體 為達上述目的’本發明之内連線結構包括：—第 低：電常數層’形成在-基底上，該基底包括一電：； 主動區以與内連線相接觸。_第二 = .:第-低介電常數材料層之上，形成-複合= -主動區域作為内連線。較佳利用一二= 殊的曲率，《改層窗的通道具有特 來連接外部元性連接主動區域，或用 知δ ;丨電層中的溝槽及 可包括一钱刻停止層介 曰商、'、口構也 間，以便於钱刻溝槽及介層弟窗。及弟—低介電常數層之 本發明提供一種萝袢主道触七Λ 名^ ^ u . 裡衣坆+導體内連線的方法，包括· 在-基底上沈積—第一低介電常 =. 一主動區域。在第—低介電常數 ^該基底包括 常數層，其介電常數低於該第一；介電：：二低介電 圓化通道，以及形成福數们fu層窗銜接處形成- 動區域的接點區。接著以導電材料埴深、:伸至基底主 再以機械式移除多餘的導電材料。/…溝槽及介層窗， 為了讓本發明之上述和其他目的 特铽、和優點能 〇503*A31345TWF2/Jeff 训7936 第95]]〇9】9號專利說明書修正本 修正曰期· 97.12.31 較4貫施例，並配合所附圖示， 更明顯易懂，下文特舉 作洋細說明如下·· 【實施方式】 本發明貫施例詳述 供許多可廣泛應用的創作丄值得注意的是，本發明提 是用以表達本發明之精神，而二’而以下所述之實施方式 本發明之較佳實扩彳丨士 ^用以限制本發明之範圍。 層中形成溝槽及介；於在-半導體元件之介電 連接兩主動區域，本發關作為内連線材料來 例如其他多層处構…可應用至其他半導體元件， 意的是，雖二：易=連接多個主動區域。值得注 除，而需純殊的製程步^的㈣製程進行選擇性的移 (咖)’但由於銅之導二寺性甚二如口化學機械研磨製程 連線之材料。铁而，也了:隐，因此仍然用來作為内 *本發明;:例:可::其上^^ :層，包括-第-介電層及-第二介電 電層之介電常數低於第一介電 …、中弟二介 刻停止層分開以便於溝槽及介㈣的::層：:以-钱 使導線的距離縮小，但d: 通銅與低介電常數材料的搭配使用他問 ::因為低介電常數材料相較於銅的 係數，且-般具有較差_著性。丄:' '、，、知脹 發明的結構及方法加以克服。…、l缺點可以本 〇5〇3-A31345TWF2/Jeff 8 1307936 第95110919號專利說明書修正本 本發明有關於一種半導^ .97.12.31 應用於半導體之内連線結構^ ^特财關於-種 係利用雙鑲嵌製程將銅填入—種新==較佳 中。内連線之溝槽及介層窗係形、及雙"層窗 介電常數材料層所組成之_人人由兩層或多層低 線結構具有較高的二發明之内連 及較=應力遷移阻抗。本發明之内線細 本發明之内連線結構係用來連接—主 與另一主動區域或電路。舉例來說，内連線；用路 兩，=或連接主動區域與外部元件或導體。1 溝样及介ΪΪ本發明，㈣線較佳彻雙鑲嵌製程形成 虏才曰及,丨層南亚以銅做為導 W成 材料。第2圖顯示样1,用其他的導電 截面圖。在此實施例&例之半導體内逹、線200的 啦此只施例中主動區域21〇 第一層結構201中，麸而^ 、、形成在基底209的 其他應用，例如，接點區二内連線也可做為 並他主動FA, μ 」早純為與另—内連線之接面。 2、圓中。關的接點區域則為了簡化而未顯示於第 結構:=層：:成在包括主動區域210的第-層 材料可使導線二==數材料。低㈣ :::材枓—般密度較低，常低 低介電常數是指介雷當與，认士 ^ Wm在此， (FSG)之介電常數 *於4.2,例如氟矽玻璃 电带數、力3.7。其他低介電常數材料包括··碳 〇^-A31345TWF2/Jeff 9 1307936 第95110919號專利說明書修正本 修正日期：97 摻雜氧化物’其介電常數約介於2 Μ 9 ·1307936 Revision Date: 97.12.31 5110919 Calling for Patent Specification Revision 9. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and the special consumption is as follows: Constant composite dielectric layer, low heat dissipation and inter-team stress migration barriers, and high mechanical strength trench and via-structure.曰 [Prior Art]: The manufacturing technology of conductor components usually involves a series of process steps, ° a, and a large number of components on the working components. In the semiconductor process, =矽 is cut into a suitable shape as a substrate, and is usually cut into a wafer. The pure tantalum wafer is then replaced with boron or phosphorous. The process is then performed on the surface of the wafer or its electric calendar, capacitors or other electronic components. After electricity, a plurality of identical grains are formed. At the end of the process - the external ΐ: connect, wrap it in a hard plastic material' and provide the internal components to complete the wafer fabrication.蹊曰: Du Fu includes tens of thousands of components to form functional electricity such as the first pass. A cross-section of the traditional interconnect structure! "R, Figure 1A shows the semiconductor device (10), and Figure 1B shows the semiconductor device 1 with a straight axis rotated 90 degrees. The negative one is on the 1A, including the first circuit and the nm is on the substrate 101. The two circuits need to be turned on. For the 0503-A31345TWF2/Jeff 5 1307936 Patent Specification No. 95110919, the revision period is: 97.1231 For convenience, the first line and the second line are respectively the active area in the figure. The second active area u〇 is formed on the substrate ι〇ι = one layer structure (10). It is worth noting that the "semiconductor: ::丄 can represent a complete functional element, but can also be used to represent The middle portion of the conductor 115 is electrically connected to the first active region (10) and the second active region 11G. The conductor 115 is formed in the inner wiring layer (8), preferably in the case of copper or copper, in order to prevent the conductor from being out of the semiconductor component. The contact, the remaining portion of the interconnect layer (10) is a dielectric material conductor 115 (not shown in Figures 1A and 1B, : ΓΓ layer or another - interconnect layer), in order to communicate with the active area = At the same time, J is filled in the same direction as the conductor 115, and is fabricated in, for example, a semiconductor component. At the time of construction, the dielectric is formed in advance: the layer is filled with conductive material, as shown in Figures 1 and 4; = and 118 extend to the active regions 105 and 11 respectively. 曰1曰 and 1Β The structure of the conductor structure of the interconnected structure. When the electricity in the wafer: the half-structure of the eve is gradually reduced, it is accompanied by:: addition, and the problem of the strength of the package, the hot peach, the stress migration and the machine, therefore, the industry needs A structure and a method for solving the above problems. [Description of the Invention] 0503-A31345TWF2/Jeff 6 1307936 Patent Specification No. 95110919 In view of this, θ is the date of the invention _ correction date m3! The purpose of the present invention is to provide an interconnect structure for use in the semiconductor for the above purposes. The lower wiring structure comprises: a lower: electrical constant layer formed on a substrate, the substrate comprising an electric:; an active region to be interconnected Contact: _ second = .: above the first low dielectric constant material layer, forming - composite = - active region as an interconnect. Preferably using one or two = special curvature, "the channel of the layered window has a special To connect external meta-connected masters The area, or the use of the knowledge of δ; the trench in the layer of electricity and can include a money to stop the layer of the mediator, ', mouth structure also, in order to facilitate the money groove and the layer of the younger brother. And brother - low media The present invention provides a method for the inner conductor of the radix of the radix, the lining of the lining, and the inner conductor of the conductor, including: deposition on the substrate - the first low dielectric constant =. In the first-low dielectric constant ^ the substrate comprises a constant layer, the dielectric constant is lower than the first; the dielectric:: two low dielectric rounding channels, and the formation of the fu-fu layer interface forming The contact area of the area. The conductive material is then deepened, extending to the base and mechanically removing excess conductive material. /...Grooves and vias, in order to make the above and other objects and advantages of the present invention 〇 503*A31345TWF2/Jeff Training 7936 95]]〇9] No. 9 patent specification to amend this revision period · 97.12 .31 is more obvious and easy to understand than the four examples, and the following is a detailed description of the following: [Embodiment] The embodiments of the present invention are described in detail for many widely applicable creations. It is noted that the present invention is intended to be illustrative of the spirit of the invention, and the embodiments described below are intended to limit the scope of the invention. A trench is formed in the layer; in the active region of the dielectric connection of the semiconductor element, the hair switch is used as an interconnect material, for example, other multilayer structures can be applied to other semiconductor components, meaning that although two: Easy = connect multiple active areas. It is worthy of note, but it requires a special process step (4) process to selectively move (coffee), but because of the copper guide two temples, such as the material of the chemical mechanical polishing process. Iron, also: hidden, so it is still used as the inner invention;: Example: can be: on the ^^: layer, including - the first dielectric layer and - the second dielectric layer has a low dielectric constant In the first dielectric..., the second brother and the second layer stop the layer to facilitate the groove and the (4):: layer:: - the distance of the wire is reduced, but d: the combination of copper and low dielectric constant material Use him to ask:: Because the low dielectric constant material is compared to the coefficient of copper, and generally has a poorer nature.丄: ' ',,, swell, the structure and method of the invention are overcome. The disadvantages of ..., l can be 〇5〇3-A31345TWF2/Jeff 8 1307936 Patent No. 95110919. The invention is related to a semi-conducting ^97.12.31 applied to the inner structure of the semiconductor ^ ^ special wealth about - germline Copper is filled in with a dual damascene process - a new == preferred. The inner channel of the trench and the interlayer window, and the double " layered window dielectric constant material layer composed of _ everyone consists of two or more layers of low-line structure with higher two inventions of the interconnection and comparison = Stress migration impedance. The inner wiring structure of the present invention is used to connect the main and another active area or circuit. For example, an interconnect; use a path, = or connect the active area to an external component or conductor. 1 Ditch sample and mediation According to the invention, the (4) line is preferably formed by a double damascene process, and the tantalum layer is made of copper as a conductive material. Figure 2 shows sample 1, using other conductive cross-sections. In the semiconductor layer of the embodiment & example, the active region 21 〇 in the first layer structure 201, the bran layer, and other applications formed on the substrate 209, for example, the contact region The second internal connection can also be used as the active FA, μ "previously pure connection with the other - interconnection. 2, in the circle. The closed contact area is not shown in the first structure for the sake of simplicity: = layer:: The first layer of material comprising the active area 210 allows the wire to be == number of materials. Low (4) ::: 枓 枓 般 般 般 般 般 般 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常 常Number, force 3.7. Other low dielectric constant materials include ··Carbon 〇^-A31345TWF2/Jeff 9 1307936 Revision No. 95110919 Patent Revision Date: 97 Doped Oxide' has a dielectric constant of approximately 2 Μ 9 ·
Diamond'應用材料公司）以及芳香族基的旋塗古八: (spin on polymer, SOP) ^ ^ t t 2.6-2.9^11 (Dow化學公司）或其他低介電常數材料。 在-較佳實施例中’第一介電層之介電常數介於 2.9-4比2之間。介層窗22Q卩奶大抵形成在第—介電芦 内^皆作為接點區215,形成所謂的雙介層窗結構曰θ 注思的是，在此處由雙介層窗連 于 同的訊號。因此，接點巴可、“ £域可傳輸相 接2&可透過一個或兩個介層 訊號。這樣可提供-额外的訊號傳輸管道，即使其 介層窗=導電特性衰退仍可快速進行訊號傳輸。” -介_停土層203選擇性地形成在第 笔-：：二於後續溝槽及介層窗的形成。 弟-；丨電層2G4置於_停止層加之上 綱人，圭為低介電常數材料。在一較物 一；丨也層204之介電常數約介於1-2.5，較佳低於該第— ;丨电層202之介電常數。雖然在第2 介 = ===層窗⑽。通道-簡 再？日240介層窗220的交接處。 第1 月^通道230是由弧形侧壁232所構成（相對於 L 方形轉角處），其中弧形侧壁主要是利用 步驟中，阻障層如Herlayer)形成前的氬濺 SPUttenng)製程來達成，其製程參數大致如下^ 〇503-A31345TWF2/Jeff 1307936 第95]]0919號專利說明書修正本 修正曰期：97.12.31 _10 ，時間約5-30秒。弧形側壁232的長度定義 是從自切線大抵平行側壁之切點至切線大抵垂直侧壁之 切f間的距離。在—實施例中，侧壁232之曲率半徑大 二第；1¾層202或第二介電層2Q4之厚度。同樣的， 溝槽24〇也與介層窗奶銜接於由側壁加所定義 道况。雖然第2圖中難攻的曲率大抵與側壁237的 曲率相同，但也可不相同。 溝槽及介層窗結構25G以内連線導體245 連線導體可為各種全眉 ." 内 佳連⑽= 較佳為銅。導體245較 成於_及介層窗中。 性料至半導體元件之其他部分(未顯示Γ 弟;3A Μ 31圖顯示本發明__實施例 =同製程階段的結構截面圖。第3 半= ::主Τ’包括基底3〇9’其材質例== 需要連接至位於另—區域的部分。了為電路或一電路中 =圖顯示沈積一第一介電層3 丘為低介電常數材料。内連 "电層較 介電層302中。接罢石奸π 、1曰®大抵形成在第一 3〇3於第一介電層’沈積—钱刻停止層 形成蝕刻停止層θ 具施例中（未顯示）’不需 及介層窗。之後如第3:斤:種彻成内連線之溝槽 較佳也為低介電常數 ^ ，尤積—第二介電層304， 電層3。“辑常數低於第—介電二，第二介 电層302。内連線之溝槽 O5〇3-A31345TWF2/Jeff 1307936 第95110919號專利說明書修正本 主要形成在第二介電層辦中。如第:日期：咖 表面沈積並以微影技術圖案化—光阻 在晶因 刻製程。第3f圖顯示經飿刻製程後在；4:=:: 形成溝槽爆並移除殘餘的光阻中 所示，沈積並圖案化另_光阻362 ^_ 行-尚功率韻刻步驟以钱穿钱刻停止層3 =刻液， 320、325，即完成如第3H 曰 4介層窗 材料的溝槽及介層窗結構。Θ ^"“填入内連線導電 第2圖中藉由明顯的弧形侧壁切來定 ，、中弧形侧壁的長度為切線平行侧壁的切二 側壁的切點間的距離。在— ，·”刀線垂直 半徑大於第一入带昆 声'施例中，侧壁332的曲率 ；"电層302或第二介電層304的戸声η 樣的，溝槽340經由通遣π'々括a 的厗度。同 _中侧壁切與侧325。雖然第 發明之精神兩_之㈣也可"^ A抵相同，但根據本 如鋼3他^與介層1結構350填滿導電材料祕，例 =他適s的導體材料，在一些製程中 摩囪結構中合J：言a 士口 π k入p />L )} ...曰/、同的益屬材料。接著再以一平扫化 製各，例如化學機械研磨製程，移除第二 十:化 多，。第31 _半導體元 成的内連線結構截曰面及圖1層商結構中填入導電材料後所完 料來連線結構中，利用銅結合低介電常數材 仏小切體元件中導體間的寬度，並利用S]化的通 12 1 〇3-A3i345TWF2/Jeff 1307936 ' 第95110919號專利說明書修正本 道區域大幅降低了因不鬥以 修正日期：97]2^ 生應力遷移。如第4圖^材料間熱膨脹係數的差異所產 移，其中曲線彻代^示本發明内連線結構之應力遷 圖示4〇〇可得知，㈣他具®化通道的内連線結構。由 連線結構大致相同，而曲線4 〇 :者之内 •及介層窗間具有一圓化 連線^構中，溝槽 -中的現象。 k ’可牛低介層s底部應力集 結合圓化通道之、、番姐Diamond's Applied Materials, Inc. and aromatic-based spin-on polymer (SOP) ^ ^ t t 2.6-2.9^11 (Dow Chemical Co.) or other low dielectric constant materials. In the preferred embodiment, the dielectric constant of the first dielectric layer is between 2.9 and 4 and 2. The via window 22Q is mostly formed in the first dielectric reed as the contact region 215, forming a so-called double-layered window structure 曰θ. Here, the double-layered window is connected to the same Signal. Therefore, the contact Barco, "£ domain can be connected to the 2 & can pass through one or two layers of signals. This can provide - additional signal transmission pipeline, even if its via window = conductive characteristics are still able to quickly signal Transmission." - The stop layer 203 is selectively formed in the first pen-:: two in the formation of subsequent trenches and vias. Brother-; the electric layer 2G4 is placed on the _stop layer plus the top, and the guise is a low dielectric constant material. In a first embodiment, the dielectric constant of the layer 204 is about 1-2.5, preferably lower than the dielectric constant of the first layer 202. Although in the 2nd = === layer window (10). Channel - Jane again? The junction of the day 240 via window 220. The first month ^ channel 230 is formed by the curved side wall 232 (relative to the corner of the L square), wherein the curved side wall is mainly used in the step of forming a barrier layer such as Herlayer before the formation of argon splash SPUttenng) To achieve, the process parameters are as follows: ^ 〇 503-A31345TWF2 / Jeff 1307936 95]] Patent specification No. 0919 Amend this revision period: 97.12.31 _10, time is about 5-30 seconds. The length of the curved side wall 232 is defined as the distance from the tangent point of the tangent to the parallel side wall to the tangent of the tangent to the vertical side wall. In an embodiment, the radius of curvature of the sidewall 232 is greater than the thickness of the layer 128 or the second dielectric layer 2Q4. Similarly, the trenches 24 are also interfaced with the vias to define the conditions defined by the sidewalls. Although the curvature of the difficult attack in Fig. 2 is substantially the same as the curvature of the side wall 237, it may be different. The interconnect conductors of the trench and via structure 25G can be various full eyebrows. The inner joint (10) = preferably copper. Conductor 245 is formed in the _ and via windows. The material is to other parts of the semiconductor component (not shown; 3A Μ 31 shows the invention __embodiment = structural cross-section of the same process stage. The third half = :: main Τ' includes the substrate 3〇9' Material example == needs to be connected to the part located in the other area. In the circuit or a circuit = the figure shows the deposition of a first dielectric layer 3 mound is a low dielectric constant material. Inline " electrical layer is more dielectric layer 302. The next step is to form a etch stop layer θ in the first dielectric layer 'deposition—the etch stop layer θ is used in the first dielectric layer (not shown). After the third layer: the groove is preferably a low dielectric constant ^, especially the second dielectric layer 304, the electric layer 3. The "complex constant is lower than the first - Dielectric 2, second dielectric layer 302. Trench of interconnects O5〇3-A31345TWF2/Jeff 1307936 The amendment to the patent specification No. 95110919 is mainly formed in the second dielectric layer. For example: Date: Date: The surface is deposited and patterned by lithography - the photoresist is processed in the crystal. The 3f is shown after the engraving process; 4:=:: Except for the residual photoresist, deposit and pattern another _ photoresist 362 ^ _ line - still power rhyme steps to stop the money to stop layer 3 = engraving, 320, 325, that is, as done 3H 曰 4 The trench and via window structure of the via material. Θ ^" "Into the interconnect wiring, Figure 2 is determined by the obvious curved sidewall cut, and the length of the middle curved sidewall is tangent The distance between the tangent points of the two side walls of the parallel side wall. The curvature of the side wall 332 in the embodiment where the vertical radius of the cut line is greater than the first entrance sound, and the electric layer 302 or the second dielectric The squeak of the layer 304 is η, and the groove 340 passes through the π's enthalpy of a. The same side wall is cut with the side 325. Although the spirit of the first invention is _ (four) The same, but according to the current steel 3 and the layer 1 structure 350 filled with conductive material secret, for example = his suitable s conductor material, in some processes in the structure of the structure of the J: a 士 a mouth π k into p />L)} ...曰/, the same beneficial material. Then use a flat sweep system, such as chemical mechanical polishing process, remove the twentieth: more, the 31st _ semiconductor element Inline In the connection structure and the structure in which the conductive material is filled in the layer structure of Fig. 1, the copper is combined with the low dielectric constant material to reduce the width between the conductors in the small body element, and the S] is used. Passing 12 1 〇3-A3i345TWF2/Jeff 1307936 'The patent specification No. 95110919 modifies the area of the road to significantly reduce the date of the correction: 97] 2^ the stress transfer. As shown in Fig. 4, the difference in thermal expansion coefficient between materials The shifting curve shows that the stress distribution diagram of the interconnect structure of the present invention shows that (4) it has an interconnect structure of the channel. The structure of the wiring is roughly the same, and the curve 4 〇 : inside the inside and the window has a rounded connection, the phenomenon in the groove -. k ’ can be low-layer s bottom stress set combined with rounded channel,
爾、—入人币 /才日及7丨層窗内連線結構中，若佶 用複合介電層更可強化内連線：中右使 溝槽的介^>禺+人〜 、、 罪又其中用來形成 电層之介電常數較 層。在此實施例中，刼咖 /取"層ϋ之介電 埶、脹係數的差異可降至最低，且 熱4耗权低，同時可縮小 m Λ4, at- ^ 再匕甲¥屯材枓與其他相似結 構W的距離。利用本發雔人 的可#•声士 之又；丨層構可提高内連線 了罪度，同％也可提高其效能。 、：然本發明已以較佳實施例揭露如上，然其並非用 梦、發明’任何熟f此技藝者’在不脫離本發明之 I: J3:圍内’當可作些許之更動與潤飾，因此本發明 呆4範圍#視後附之巾請專職H所界定者為準。In the case of the connection between the Renminbi and the Renminbi and the 7-layer window, if the composite dielectric layer is used, the interconnection can be strengthened: the middle right makes the trenches>>禺+人~, The sin is also used to form the electrical layer with a dielectric constant. In this embodiment, the difference between the dielectric enthalpy and the expansion coefficient of the 刼 / / / ϋ 可 layer can be minimized, and the heat 4 has low power consumption, and can be reduced by m Λ 4, at- ^ 匕 armor ¥ The distance between 枓 and other similar structures W. The use of this hairpin can be used to improve the efficiency of the internal connection. However, the present invention has been disclosed above in the preferred embodiment, but it is not intended to be a dream, and the invention may be modified by the skilled person without departing from the invention of the invention: J3: Therefore, the scope of the present invention is 4, and the attached towel is subject to the definition of full-time H.
°5〇3-A3l345TWF2/JefF 13 1307936 修正日期：97.12.31 第95110919號專利說明書修正本 【圖式簡單說明】 第1A圖顯示先前技術中半導體元件之截面圖。 第1B圖顯示第1A圖半導體元件轉卯度之截面圖。 f 2圖顯示本發明一實施例之内連線截面圖。 、第3人至31圖顯示本發明—實施例中不同製程階段 . 之截面圖。 第4圖顯不本發明—實施例中内連線之應力遷移°5〇3-A3l345TWF2/JefF 13 1307936 Revision date: 97.12.31 Amendment to Patent Specification No. 95110919 [Simplified description of the drawings] Fig. 1A shows a cross-sectional view of a semiconductor element in the prior art. Fig. 1B is a cross-sectional view showing the degree of transition of the semiconductor element of Fig. 1A. Figure 2 is a cross-sectional view showing the interconnection of an embodiment of the present invention. Figures 3 through 31 show cross-sectional views of different process stages in the present invention - the examples. Figure 4 shows the stress migration of the interconnects in the present invention - the examples
主要元件符號說明】 101 ' 209、309〜基底； 103〜内連線層； 110〜第二主動區； H6、240、340〜溝槽； 320、325〜介層窗； 200〜半導體内連線； 203、303〜钮刻停止層； 210、310〜主動區域； 100、300〜半導體元件； 102、201〜第一層結構； 105〜第一主動區； 115、245〜導體； 117 、 118 、 220 、 225 、 12 0〜介電材料； 202、302〜第一介電層； 204、304〜第二介電層； 215〜接點區； 230、235、330、335〜通道 232、237、332、337〜側壁 345〜導電材料； 360、362〜光阻； 405、410〜曲線。 250〜溝槽及介層窗結構； 350〜介層窗結構； 400〜圖示； 0503-A31345TWF2/Jeflf 14Main component symbol description] 101 '209, 309~ substrate; 103~ interconnect layer; 110~ second active region; H6, 240, 340~ trench; 320, 325~ via; 200~ semiconductor interconnect 203, 303~ button stop layer; 210, 310~ active area; 100, 300~ semiconductor element; 102, 201~ first layer structure; 105~ first active area; 115, 245~ conductor; 117, 118, 220, 225, 12 0~ dielectric material; 202, 302~ first dielectric layer; 204, 304~ second dielectric layer; 215~ contact area; 230, 235, 330, 335~ channel 232, 237, 332, 337 ~ sidewall 345 ~ conductive material; 360, 362 ~ photoresist; 405, 410 ~ curve. 250~ trench and via window structure; 350~ via window structure; 400~illustration; 0503-A31345TWF2/Jeflf 14