TW200834816A - Semiconductor devices having metal interconnections, semiconductor cluster tools used in fabrication therof and methods of fabricating the same - Google Patents

Abstract

A method of fabricating a semiconductor device is provided. The method includes providing a semiconductor substrate having a conductive pattern and forming an insulating layer on the conductive pattern and the semiconductor substrate. The insulating layer is patterned to form an opening which exposes a portion of the conductive pattern. A preliminary diffusion barrier layer is formed on an inner wall of the opening and a top surface of the insulating layer. Oxygen atoms are supplied onto the preliminary diffusion barrier layer to form a first diffusion barrier layer. A metal layer is formed on the first diffusion barrier layer. The metal layer is formed to fill the opening surrounded by the first diffusion barrier layer. A semiconductor device fabricated by the method and a semiconductor cluster tool used in fabrication of the semiconductor device are also provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, and more particularly to a method of fabricating a semiconductor device and a tool for fabricating the same. [Prior Art] ', Ik's semiconductor device's accumulation gradually increases, the width, thickness and thickness of the metal interconnect are gradually reduced, so the resistance of the metal interconnect is gradually increased. Φ Thus, the aluminum layer, which is widely used as a metal interconnect layer, is gradually replaced by a low-resistivity copper layer. However, the copper layer used to form the topmost interconnect (e.g., bond pads) is susceptible to oxidation. Therefore, in the copper interconnect, the aluminum layer is still used to form the topmost interconnect. In this case, the aluminum interconnect will contact the copper interconnect in the contact area (for example, the contact hole), and the copper atoms in the two/internal lines or the aluminum atoms in the aluminum interconnect will diffuse out. And an alloy layer containing copper atoms and aluminum atoms is formed. Since the alloy layer has a high electrical resistivity, the electrical characteristics of the semiconductor device are impaired. Ν #又的铝内线线 may be formed in the opening, for example, in contact with the hole. The accumulation density of the (4) semiconductor device increases, and the aspect ratio of the contact hole ' (4) (10) (4) may increase. Therefore, in the formation of the _ wire, it is quite difficult to completely fill the contact hole without any void. The gaps in the contact holes may impair the electrical properties of the half. SUMMARY OF THE INVENTION A method of the present invention relates to a semiconductor device having a metal interconnection and a method of fabricating the same, and a semiconductor group 200834816 zoyzipii group tool for fabricating the semiconductor device. In one embodiment, a half-body semiconductor substrate. _ is set in the guide, the edge layer has a through-insulation Μ exposure - part of the conductive pattern 忒 = is an internal connection = in the insulation layer cut and open _. The first oxygen atom. Between electric beech. Brother-diffusion barrier pattern package. In some embodiments, the oxygen atom is located in the first diffusion barrier pattern.

Within the grain boundaries. In still other embodiments, the <conducting' includes copper and the metal interconnect comprises aluminum. In still other embodiments, the semiconductor device further includes a second diffusion barrier pattern between the first diffusion barrier pattern and the metal interconnect. The first and second diffusion barrier patterns may include a refractory metal. The refractory metal may include titanium (Ti), group (Ta), strontium (10), strontium (V), erbium (Zr), strontium (Hf), strontium (M〇), chain (Re), crane (W), and chin. At least one of (TiZr). Alternatively, the first and second diffusion barrier patterns may each comprise a refractory metal nitride. In this case, the refractory metal nitride layer may include titanium nitride (TiN), tantalum nitride (TaN), tantalum nitride (NbN), nitriding (VN), zirconium nitride (ZrN), nitriding. One of HfN, MoN, ReN, WN, and TiZrN. The second diffusion barrier pattern may extend onto the sidewall of the opening. In this case, the semiconductor device further includes an anti-deposition pattern between the upper sidewall of the second diffusion barrier pattern disposed in the opening and the upper sidewall of the metal interconnection within the opening. Therefore, the lower sidewall of the second diffusion barrier pattern in the opening may be in direct contact with the metal interconnect. Second diffusion barrier 7 200834816 The zoyzipn pattern may include a first metal nitride layer. The anti-deposition pattern may be omitted. The nitrogen content of the second metal nitride layer can be - two? The nitrogen of the layer is set. The first and second metal nitride layers may comprise the same fumes metal. The second diffusion barrier pattern may include a refractory full sound, and the anti-deposition pattern may include a refractory metal nitride layer.曰—In another embodiment, the semiconductor group i includes a first chamber, and at least one of the following processes is performed: • initial diffusion barrier layer; supply of oxygen atoms to preliminary: barrier formation a diffusion barrier layer; and in the first-expansion; two-expanding soil =, two to diffuse the barrier layer. The second chamber is configured to be capable of depositing at the opening, the second layer. The anti-deposition layer exposes the opening _ the first to form a resistance.筮 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄 玄The metal layer fills the opening. Attacking to the genus - In some embodiments, the semiconductor group tool can include a fourth chamber and a five-chamber. In this case, in the first chamber and in the fourth chamber (4) oxygen; ^ ϋ flute / into the initial 乂 diffusion barrier layer, layer ang four to medium i, [subtraction, and form a second in the chamber Diffusion Barrier In other embodiments, the fourth chamber can be one of a clean room, and a cooling chamber. The cleaning chamber may be provided with a "surface of the substrate." In other embodiments, the substrate may have an insulating layer and be placed to penetrate the insulating layer. ^ In another embodiment, - a semiconductor I The method of the station is to add a semiconductor substrate. The insulating layer is formed on the conductor and the conductor substrate. The insulating layer is patterned to form an opening of =. The initial diffusion barrier layer is formed in the opening; the wall: two: filling the brother-diffusion barrier (four) package _ opening.

child. In other embodiments, a thermal oxygen treatment process can be used to supply the oxygen source. In other embodiments, an oxygen plasma process is used to supply the oxygen atoms. In the example of the second square, an oxygen atom is supplied by using a mixture of helium 2 gas, helium 20 gas, H2Q gas, a mixture of helium 2 gas and H 2 gas, and an alpha gas. In other Bega cases, before the formation of the metal layer, a diffusion barrier layer can be formed on the first expansion of the early childhood layer. The first and second diffusion barrier layers may each be formed of a refractory metal layer. The refractory metal layer may include titanium (Ta), tantalum (Ta), niobium (Nb), vanadium (V), niobium (Zr), hafnium (Hi), hafnium (Mo), antimony (Re), and tungsten (W). At least one of them. Alternatively, the first and second diffusion barrier layers are each formed of a refractory metal nitride layer. The refractory metal nitride layer may include titanium nitride (TiN), nitride nitride (TaN), tantalum nitride (NbN), tantalum nitride (VN), tantalum nitride (ZrN), hafnium nitride (HfN), nitrogen. Molybdenum (MoN), nitriding chain (ReN), tungsten nitride (WN), and titanium zirconium nitride (TiZrN). In other embodiments, the conductive pattern may be formed from a copper layer, while the metal 9 200834816 zoyzipn layer may be formed from an inscribed layer. In still other embodiments, the method further includes forming a second diffusion barrier layer on the first diffusion barrier layer, and the patterned metal layer, the second diffusion barrier layer, and the first diffusion barrier layer, before forming the metal layer. A first diffusion barrier pattern, a second diffusion barrier pattern, and a metal interconnection are sequentially stacked. In this case, the metal interconnect may fill the opening surrounded by the second diffusion barrier pattern. An anti-deposition layer may be formed on the substrate having the second diffusion barrier layer before the formation of the metal layer. The anti-deposition layer may be formed on a top surface of the first diffusion barrier layer outside the opening and on an upper sidewall of the second diffusion barrier layer in the opening to expose the lower side of the second diffusion barrier layer in the opening In the process of metal interconnects, the anti-deposition layer is patterned to form an anti-deposition® case underneath the 4-Simen-genus interconnect. Chemical vapor deposition (CVD: ^ into a metal layer. In this case, the exposed second diffusion barrier layer macro to the genus - layer deposition rate 彳 higher than the anti- &amp; layer on the metal layer deposition two diffusion barrier The layer may be formed of a first metal nitride layer, and the ?T is higher than the nitrogen content of the first metal nitride layer. The second expanded H layer may comprise the same refractory metal. The second diffusion may be (four) fire The metal layer is formed 'the anti-deposition layer can be reinforced by the refractory metal nitrogen: the second diffusion barrier layer can be chemical vapor deposition (CVD) 1 and the anti-deposition layer can be electrically patterned using physical vapor deposition (PVD) technology, preliminary diffusion The barrier layer, the first diffusion barrier layer, the first = early wall layer, the anti-deposition layer, and the metal layer may be formed using a single group tool. 200834816 ZWZipll [Embodiment] The U diagram is more fully described, and the drawings show However, the present invention can be embodied in various forms and is interpreted as being inconsistent with the embodiments of the present invention. More specifically, the embodiments are provided to make the disclosure thorough and complete, and Well known The scope of the invention is conveyed by those skilled in the art, and the dimensions and relative dimensions of the layers and regions are exaggerated for clarity. In addition, the embodiments of the present description and the illustrated embodiments include elements whose complementary electrical conductivity always represents similar. It will be understood that when an element or layer is referred to as being "in" or "in" or "in" or "in" or "" = or the opposite of the layer, when a piece is called "gu and / or "directly connected to, another element two = directly connected to" or layer. In addition, the θ code does not exist in the middle of the arbitrary and related enumeration One or more of the descriptions of the item are different, first, second, and third, such as parts, zones, and (1) s, layers, and/or parts, but these elements are only used Distinguishing ^ injuries should not be limited by these terms. This is the ancient five emotions, / Ding 7 spears / or bruises. For example, the first element, t Ming can be removed without divorcing The scope of the two parts, zones, layers and / or parts. 4 parts called the second 'On the door relative to the street language, such as "below,", "below,", "above" 200834816 zovzipn is used in this case to facilitate the description of one element and / or feature and another element and / or feature shown in the figure It is to be understood that the terms are intended to include different orientations of the device in the <Desc/Clms Page number> The elements are located "above" other elements or features. Thus, the term "below" can include both upper and lower orientations. The device can also be otherwise positioned (rotated 90° or other orientation) and the space used in this case The relative description is explained accordingly. Further, as the figure is shown, the term "below" means the relationship of one layer or zone to another substrate or zone relative to the substrate. The terminology used in the description is for the purpose of describing particular embodiments and is not intended to be limiting. The singular forms "a", "the", and "the" It is to be understood that the terms "comprises" and "comprises" or "includes", when used in the context of the present invention, are intended to mean the presence of the features, integers, steps, operations, components and/or components mentioned, but do not exclude the presence or addition of one or more other features. , whole, steps, operations, components, components, and/or their ethnic groups. Embodiments of the present invention are described with reference to the plan and sectional drawings, which are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. Shape changes of the illustrations due to manufacturing techniques and/or tolerances are contemplated. Accordingly, the embodiments of the present invention are not to be construed as limited to the particular s For example, an implanted region illustrated as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a two-bit change from the implanted zone to the non-implanted zone. Similarly, a certain degree of implantation can be created in the region between the buried region and the surface through which implantation takes place by implantation of the implanted region. Thus, the regions illustrated in the figures are illustrative and are not intended to limit the scope of the present invention, and are not intended to limit the scope of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. It is to be understood that the meanings of those terms, such as those defined in commonly used dictionaries, should be interpreted as having the same meaning as in the context of the present specification and related fields and should not be interpreted in an idealized or overly formal form 'unless otherwise clear in this case Defined like this. 1 to 8 are cross-sectional views showing a method of fabricating a semiconductor device and a semiconductor device fabricated in this manner according to an embodiment of the present invention. The corpse and the 圔 两 are two, so the supply has a conductive map for "V dry and other HI board 100. The pattern 105 may include copper (Cu). That is, the conductive pattern can be formed by =. The insulating layer m may be formed on the conductive pattern 10 and the oxygen-cut i1G may be a part of the conductive pattern i 2 using a chemical vapor deposition (CVD) technique. The insulating layer 110 is patterned to form an opening 115 that is exposed in a linear or linear configuration. The opening 115 may have a hole-shaped matte view 2, forming an inner wall of the preliminary diffusion barrier = 115 on the pan u and a sidewall of the top surface of the insulating layer (10) and the gate layer 12{). The inner wall of the opening 115 includes an opening U5 2 which initially picks the surface of the exposed conductive pattern 105. As shown in the figure, only the barrier layer 120 can be formed using a CVD technique, so that the surface profile of the substrate is substantially identical to the surface profile of the substrate including the insulating layer no and the opening Π5. The preliminary diffusion barrier layer 120 may be formed of a refractory metal layer. For example, the preliminary diffusion barrier layer 120 may be a titanium (Ti) layer, a button (Ta) layer, a niobium (Nb) layer, a vanadium (V) layer, a zirconium (Zr) layer, a hafnium (Hf) layer, a molybdenum (Mo) layer, At least one of a ruthenium (Re) layer, a tungsten (w) layer, and a titanium hammer (TiZr) layer is formed. Alternatively, the preliminary diffusion barrier layer 120 may be formed of a refractory metal nitride layer. For example, the preliminary diffusion barrier layer 12 may be a titanium nitride (butadiene) layer, a nitride button (TaN) layer, a tantalum nitride (NbN) layer, a tantalum nitride (VN) layer, a nitrided (ZrN) layer, At least one of a hafnium nitride (HfN) layer, a molybdenum nitride (M〇N) layer, a nitrided chain (ReN) layer, a nitrided (WN) layer, and a titanium nitride tantalum (TiZrN) layer is formed. Referring to Fig. 3, oxygen atoms are supplied onto the preliminary diffusion barrier layer 12 () to form a first diffusion barrier layer 12a. The oxygen atoms may react on the preliminary diffusion barrier layer 120 to oxidize the grain of the preliminary diffusion barrier layer 12 or fill the grain boundary of the preliminary diffusion barrier layer 12A. An oxygen-based gas can be used to supply oxygen atoms. The oxygen-based J body may include at least one of helium 2 gas, n2 helium gas, h2 helium gas, helium 2 gas and gas mixture, and helium 3 gas. ^ Alternatively, an oxygen treatment process is used to supply oxygen f. The oxygen treatment process may include a thermal treatment process performed at a high temperature. For example, under a process condition of a temperature of about 2 〇 drought 600 C, an oxygen flow rate of about 1:1 to 1 〇〇〇〇 standard cubic centimeter (seem), and a pressure greater than about 〇 Torr (t〇rr) and less than about 1000 Torr. Perform an oxygen treatment process. In another embodiment 14 200834816 zwzipn, oxygen atoms are supplied in an oxygen plasma process. For example, at a temperature of about 20 ° C to 600 t:, the oxygen flow rate is about 1 to 1000 sccm, and the inert gas flow rate is about! Under the process conditions of i〇〇〇〇scem and a pressure greater than about Otorr and less than or equal to 1 〇Q〇t〇rr, the oxygen plasma process is performed using oxygen radicals and oxygen ions.

Referring to FIG. 4, a second diffusion barrier layer 13A may be formed on the first diffusion barrier layer 120a. As shown in FIG. 4, the second diffusion barrier layer 13 can be formed using a CVD technique, and thus its surface profile substantially coincides with the surface profile of the first diffusion barrier layer i2a. The second diffusion barrier layer 13 can be formed of a refractory metal layer. For example, the second diffusion barrier layer 13 may be made of titanium (Ti), button (Ta), sharp (Nb), 鈒 (V), junction (Zr), 铪 (Hf), 锢 (M〇), 铢 (Re). At least one of tantalum (w) and titanium germanium (TiZr) is formed. Alternatively, the second diffusion barrier layer bo may be formed of a (four) fire metal nitride layer. For example, the second diffusion barrier layer 130 may be composed of titanium nitride (TiN), nitride button (lane), nitrided (NbN), vanadium (VN), nitrogen (four), nitrided, and Molybdenum

A formation of at least one of tantalum nitride (ReN), tungsten nitride (WN), and titanium nitride (TiZrN). V Referring to Fig. 5, an anti-deposition layer is formed on the second diffusion barrier layer (10). In the illustrated embodiment, the method of forming the anti-deposition layer (10)a is, for example, a deposition process in which the step coverage is poor (poor step c〇ve zero). Therefore, the = stacking theory can be formed on the upper side wall of the scoop of the σ 115 (4) di-diffusion barrier layer (10) and the top ice of the second diffusion barrier layer 13 outside the opening 115. Further, an anti-deposition layer 14A is formed on the surface of the dipole-diffusion barrier layer 13G_ above the bottom surface of the opening US. Thus, such as riding *, anti-deposition 15 200834816 zoyzipn layer 140a may include a protrusion (〇verhang) covering the upper corner of opening ii5. Further, as shown, the anti-deposition layer 14A &amp; can expose the lower sidewall of the second diffusion barrier layer 130 within the opening 115. The anti-deposition layer 140a can be formed from a refractory metal nitride layer using physical vapor deposition (PVD) techniques. For example, the anti-//, layer 14 〇a can be formed using a SpU tiering technique. In this case, 'nitrogen gas may be used to form the anti-deposition layer 14〇a. The second diffusion barrier layer 130 may be formed of a first metal nitride layer, and φ and resistant to the buildup layer 140a may be formed of a second metal nitride layer. In this case, the nitrogen content of the 5 second metal nitride may be greater than the nitrogen content of the first metal nitride layer. The material of the refractory metal contained in the anti-deposition layer 140a is the same as that of the refractory metal contained in the second diffusion barrier layer 130. When the second diffusion barrier layer 130 is formed of a refractory metal layer, the anti-deposition layer 14 may be formed of a refractory metal nitride layer. Referring to Fig. 6, a first metal layer 152 is formed on a substrate 1A including an anti-deposition layer 140a. The first metal layer 152 can be formed using a CVD technique. The first metal layer 152 may comprise aluminum. When the first metal layer is formed by CVD technology, the first metal layer 152 is deposited on the second diffusion barrier layer 13〇 exposed to the inside of the opening 115 at a first deposition rate, and deposited at a second deposition rate. On the anti-deposition layer 140a. Here, since the nitrogen content of the second diffusion barrier layer I30 is lower than the nitrogen content of the anti-deposition layer 14a, the first deposition rate may return to the second deposition rate. Therefore, the first metal layer 152 can completely fill the opening 115 without any gap. Referring to FIG. 7, a second metal layer 154 is formed on the first metal layer 152. In order to reduce the deposition time of the second metal layer 154, a second metal layer 154 may be formed using pVD technology to 16 200834816 2692 Ipif. If you borrow 筮 _ &quot; 匕 弟 ― 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 However, if the second metal layer 15 is deposited at a high temperature, the process is slightly reflowed. First and second metal layers 152 ^ layer 150. 152 and 154 constitute metal 120, first diffusion barrier layer i4〇a, and metal layer 15〇

The conductive pattern 105, the preliminary diffusion barrier layer 120a, the second diffusion barrier layer 130, and the anti-deposition layer may be formed using a single group tool. Only = upper = embodiment, the first and second crucible layers 12 钢 the steel atoms in the U conductive pattern 105 diffuse to the metal layer 15 〇 同 = = = = = = = = = = = = = = = = = = = = = = = = milk inside. In other words, the first and second diffusion barrier layers = 30 can be used to block the diffusion of copper, while the other can be used for static diffusion. In detail, since the grain edge of the first diffusion barrier layer has milk atoms, the atom in the metal layer 15G may be opposite to the oxygen atom to form oxygen at the grain boundary. The oxygen brain blocks the diffusion path of the young atoms. Referring to FIG. 8, a metal layer (9), an anti-deposition layer 1 , a first barrier layer 13G, and a first diffusion barrier layer 12 〇 a may be patterned to form a first diffusion 卩 early wall pattern, and a second The diffusion barrier pattern 1 is, for example, a k deposition pattern 140a' and a metal interconnection 15〇. The metal interconnect 15 〇 may include a first metal mesh 152 of sequentially stacked $ and a second metal pattern 154'. A metal interconnect 150 can cover the opening 115. Next, a semiconductor package 17 200834816 2692 Ipit according to an embodiment of the present invention will be described with reference to FIG. The photo substrate 8' provides a semiconductor substrate 1 having a conductive pattern i〇5. The conductive pattern 1〇5 may include copper. That is, the conductive pattern may be a copper line. The interlayer insulating layer 110 may be disposed on the conductive pattern 105. And • On the conductor substrate (10), In 115 penetrates the interlayer insulating layer 11 (), and the storm/road guide package pattern l (b-part. Metal lining, 15 〇, set in the interlayer, 彖 layer uo And the opening π 115. The metal interconnection 15〇, may include the first layer of the metal lazy 152, and the second metal _ 154. The first metal pattern 152 may be formed by using a CVD technique to fill The opening ιΐ5, and the second metal pattern 154 can be formed using a PVD technique. The metal interconnect 150 1 includes !g ' and has a cylindrical configuration or a linear configuration. The first diffusion barrier pattern 120a can be disposed in the metal interconnection 150, between the conductive pattern 105. The first diffusion barrier pattern 120a may extend to the sidewall of the opening Π5 and the top surface of the interlayer insulating layer 11〇. That is, the first diffusion barrier pattern 12〇a may be disposed on the metal The interconnect 15 (), and the interlayer insulating layer" between 1 。. The diffusion barrier pattern 120a may include oxygen. For example, the oxygen diffusion atoms are filled at the grain boundaries of the first diffusion barrier pattern 120a. The second diffusion barrier pattern 130 may be disposed on the first diffusion barrier pattern l2a, ' Between the first and second diffusion barrier patterns 120a, 130, respectively, the refractory metal may be included. For example, the first and second diffusion barrier patterns l2a, and 13〇 may respectively include Titanium (Ti), neon (Ta), niobium (Nb), vanadium (¥), junction), niobium (_, indium (Mo), antimony (Re), tungsten (W), and titanium zirconium (TiZr) At least one or 'the first and second diffusion barrier patterns 12a, and 130, respectively, may include 18 200834816 2 (3 like pil refractory metal nitrides, such as first and second diffusion barrier patterns 120a, and 130_, Titanium nitride (), nitrided (TaN), nitrided (NbN), varnish (VN), tantalum nitride (ZrN), nitrided yttrium, molybdenum nitride, nitrided crane Titanium nitride and Titanium nitride And 130, can prevent the copper atoms in the conductive pattern H)5 from diffusing to the metal ϋί metal (four) line (9), the inside of the atom diffuses into the conductive pattern Κ) 5 Ϊ 2 = 1 metal interconnect 15 &quot; _ atom diffusion to the first When the diffusion barrier is 120a', the shoulders are long-lived; ^ Guang 7 Ba Fanlu #士.../,, the atom is a human milk atomic reaction and is located at the edge of the grain &quot; Oxygen can block the atomic_scatter path. The whole pattern 14〇a can be disposed on the portion of the interface between the second diffusion barrier pattern 130 and the connection (=4). For example, Figure -130^ Π0 ί 图安un is an inline, line 15〇, between the edges. In addition, the anti-slitter scorpion t-white ridge extends to cover the side of the second diffusion barrier in the opening 115. Furthermore, the anti-deposition pattern 1 is disposed on the top surface of the aperture 115 of the opening 115 and the opening 1 b = the inner connecting line 15G, the m metal interconnecting line 15G, the contact opening The second diffusion barrier in layer 115 may include refractory metal nitriding; The lower side of the spoon. The anti-sinking anti-sinking film 13G may include a first metal nitride layer, and the yttrium 140a may include a second metal nitride layer. In this case 19 200834816 2692 Ipif, the nitrogen content of the second metal nitride is greater than the nitrogen content of the first metal nitride layer. The material of the refractory metal contained in the anti-deposition pattern 14〇a' is the same as the refractory metal contained in the second diffusion IV wall pattern 130'. When the second diffusion barrier pattern 130' includes a refractory metal layer, the anti-deposition pattern i4〇a may include a refractory metal nitride layer. Fig. 9 is a graph showing changes in sheet resistance of various metal layers manufactured according to the prior art and the present invention. In Figure 9, the horizontal seat

Represents a conventional metal layer and a metal layer fabricated in accordance with the present invention, and the ordinate represents the first surface resistance RS1 of the metal layer (before the annealing process is performed) and the second surface resistance RS2 of the metal layer (after the annealing process) The surface resistance of the gate changes RV. On the abscissa, the conventional metal layers are labeled as ", ^, "Ta2", "TaNl" and "TaN2", and the metal layer produced according to the present invention is not "Tal (oxygen treatment),", "Ta2 (oxygen treatment),", "τ N1 (oxygen and 'TM (oxygen treatment),). The copper layer is formed on each of the metal layer substrates by the following steps; A diffusion barrier layer is formed on the layer; a layer is formed on the diffusion barrier layer, and the layer is expanded and scaled. In this case, before the annealing process, the resistor RS1 is measured and the annealing process is performed. Then, the second surface resistance RS2c is measured; thus, the surface resistance RV can be calculated using the following equation. RV={(RS2-RSl)xl〇〇}-^Rsl In the conventional Lai towel, the thickness of the rhyme is 5 (4) "TM,,", thickness (10) ang: (4) (see "如,,) ί 4〇ν^ ! ^ ^UTaNl (ί see a 2). In contrast, the diffusion barrier layer of the present invention is formed by the oxygen filling process after the formation of the initial layer 20 200834816 ZDWipi P. Xygen stuffmgproeess), formed by treatment (see "Tai (oxygen treatment),", "Ta2 (oxygen treatment),", "TaNl (oxygen treatment)" or "TaN2 (oxygen treatment),). In this case The preliminary diffusion barrier layer is one of the conventional diffusion barrier layers. Referring to Figure 9, the surface resistance change RV of the conventional metal layers Tai, Ta2, TaN1, and TaN2 is about 80% to 120%. Conversely, the present invention The sheet resistance change RV of the metal layer is about 5% to 25%. The above phenomenon can be attributed to the fact that in the annealing process, since an alloy layer containing copper and aluminum is formed in a conventional metal layer, the conventional knowledge is remarkably increased. The sheet resistance of the metal layer. Fig. 10 is a graph showing the physical parameters and electrical parameters of the metal layer of the nitrided layer having different nitrogen contents. In Fig. 1 , the abscissa represents various kinds of nitrogen having different nitrogen contents. Nitrided layers TaNl, TaN2, ..., and TaN8 'left side stand The cvd deposited on the nitrided layer is in the thickness of the layer, and the right side is the resistivity of each nitride layer. The tantalum nitride layer TaNl, TaN2 is formed by nitrogen reactive sputtering technology. ··· and aN8, respectively, forming a cVD aluminum layer on the nitride button layer. The CVD aluminum layer is deposited with the same deposition time. The nitrogen content of the nitride button layer is gradually changed from the left ordinate to the right ordinate. In other words, the eighth nitride button layer TaN8 has the largest nitrogen content, and the first tantalum nitride layer TaN1 has the smallest nitrogen content. As can be seen from Fig. 10, the higher the nitrogen content of the tantalum nitride layer, the lower the deposition rate of the CVD aluminum layer on the nitride button layer. Thus, when the second diffusion barrier layer 130 and the anti-deposition layer 14 〇a % described in FIG. 4 to FIG. 5 are formed with a nitride layer, in order to completely fill the ruthenium nitride layer without voids 21 Preferably, the nitrogen content of the second diffusion barrier layer 130 is lower than the nitrogen content of the anti-deposition layer 140a. ', 曰 Figure 11 is a graph of the sheet resistance of a CVD aluminum layer deposited on various nitrided layers having different nitrogen contents. In Fig. u, the abscissas represent various titanium nitride layers TiN1, TiN2, TiN3 having different nitrogen contents, and the ordinate represents the sheet resistance of the CVD aluminum layer deposited on the titanium nitride layers TiN1, TiN2, TiN3 and above. The titanium nitride layers TiN1, TiN2, TiN3, and TM4 are formed by a nitrogen active sputtering technique. The CVD aluminum layer was deposited with the same deposition time. The nitrogen content of the titanium nitride layer gradually increases toward the right ordinate. That is, the fourth titanium nitride layer TiN4 has the highest nitrogen content, and the first titanium nitride layer TiN1 has the lowest nitrogen content. As is apparent from Fig. 11, the higher the nitrogen content of the titanium nitride layer, the higher the sheet resistance of the CVD aluminum layer on the titanium nitride layer. This phenomenon is understood to mean that the thickness of the CVD aluminum layer deposited on the titanium nitride layer is opposite to the nitrogen content of the titanium nitride layer. Figure 12 is a schematic illustration of a semiconductor group tool for fabricating a semiconductor device in accordance with an embodiment of the present invention. Referring to Fig. 12, the semiconductor group tool 10 can include first and second loading lock chambers 20, first and second transfer chambers 3A, first and second cooling chambers 2, and a plurality of processing chambers. The first and second load lock chambers 20 are connectable to the first transfer to 30 and the first and second cooling chambers 44 are disposed in parallel between the first and second transfer chambers 30. The processing chamber may include a cleaning chamber 42, a degassing chamber 46, and first to seventh chambers 52, 54, 56, 58, 62, 64, and %. The cleaning chamber 42, the degassing chamber 46, the third chamber 56, and the fourth chamber 58 are connected to the first transfer chamber 30, and the first chamber 52, the second chamber 54, the fifth to seventh chambers 62, 22 200834816 ^Oy^ Ipx [64 and 70 are connected to the second transfer chamber 3〇. Each of the transfer chambers 30 may include a wafer transfer unit for moving the wafer, and the wafer transfer unit may have a mechanical arm 35 placed on the mechanical arm 35. The robot arm 35 can move the wafer located in the transfer chamber 3A into a chamber connected to the transfer chamber 30. Further, the robot arm % can transfer the wafer located in one chamber connected to the transfer chamber 30 into the transfer chamber 3A.

Next, a method of manufacturing a semiconductor device using the semiconductor group tool 1 will be described. ^ Referring again to Figures 1 through 7 and Figure 12, the wafer can be fabricated with openings 115' such as contact holes or linear grooves. The ^ having the opening I]; can be loaded into a load lock chamber 20. The wafers in the load lock chamber 2' can be transferred to the clean room 42 by the transfer to 30. In the clean room 42, the crystal having the opening ΐ5 is cleaned using gas and/or helium gas. The cleaned wafer is transferred to the first chamber 52 via the first and second transfer chambers 3G and the cooling chamber 44, and 廿 s ^ ^ ^ to 2 in the inner Asia and in the first one to the 52, the preliminary formation of the cleaning crystal Diffusion barrier layer 12G. Next, oxygen atoms are supplied into the first to 52 to form the first diffusion barrier layer 12a. Alternatively, after the wafer in which the barrier layer is dispersed is transferred into the second chamber 54, the oxygen chamber 2 is again supplied. That is, the first diffusion barrier layer 120a may be formed in the first chamber 52 or the second chamber 54. The wafer having the first diffusion barrier layer 12A can be moved to the third chamber 56 via the first and second transfer chambers 30 and a cooling chamber 44. A second diffusion barrier layer is formed on the third diffusion barrier layer 12Ga in the third chamber, or the second diffusion barrier layer 130 may be formed in the first chamber 52. 23 200834816 zoyzipn t The barrier layer 120, the first diffusion barrier layer 12, and the dipole wall layer 13Q may be formed in the same chamber to which oxygen atoms are supplied. The wafer of the diffusion barrier layer 130 can be transferred to the fourth chamber 58 connected to the first pass, and the anti-deposition layer 14A is formed on the wafer having the second diffusion barrier layer (10). In the case of ^ 曰 ^ ^ ^ ^, the fourth chamber 58 y 疋 有 % ^ ^ ^ ^ ^ PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV (4) On the top surface. Therefore, after the 抗y becomes the anti-deposition layer 14〇a, the lower side wall of the opening 115 130 is purely held. Spreading the wafer: the wafer having the anti-deposition layer 14Ga is transferred into the fifth chamber a, and the wafers forming the first-metal reed-metal layer 152 in the deposition layer and the opening 115 are transferred to the sixth t 64, and Forming a second metal layer 154 on the first 152 ^ 〒 层 layer ' WPVDt 〇 M wood 1 υ: &gt; In the opening 115 shape, the formation of a conductive pattern 1Q5 in the seventh chamber 70 To form a first-diffusion barrier; In the case of 12Ga / 2%, the chamber 46 or the cooling chamber 44 is inside. The (10) sub-layer is supplied to the degassing. According to the above embodiment, the diffusion barrier layer may be filled with gas atoms at the grain boundaries of the diffusion layer. Therefore, the diffusion barrier layer of the second layer can be used as a copper diffusion and the anti-deposition layer of the antimony atom, and the anti-deposition layer can form a nitrogen network on the diffusion barrier layer to form a nitrogen content of 24 200834816 zoy/ipn. Therefore, when an aluminum layer is formed on the anti-deposition layer outside the opening and the diffusion barrier layer in the opening, the aluminum layer can completely fill the opening without any void. Although the invention has been described in connection with the embodiments shown in the drawings, the invention is not limited thereto. It is apparent to those skilled in the art that various substitutions, modifications and changes can be made without departing from the spirit and scope of the invention. Embodiments of the invention have been disclosed in the drawings and the description. The specific terms are used, but they are used in a generic and descriptive manner only, and not for the purpose of limitation, the scope of the invention is set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. δ are cross-sectional views showing a method of fabricating a semiconductor device and a semiconductor device manufactured by the method according to an embodiment of the present invention. 9 to 11 are graphs showing some characteristics of a semiconductor device in accordance with the present invention. Figure 12 is a schematic illustration of a semiconductor group tool for fabricating a semiconductor device in accordance with an embodiment of the present invention. [Main component symbol description] 10: semiconductor group tool 20: load lock chamber 30: transfer chamber 35: robot arm 42: clean room 25 200834816 丄丄 44: cooling chamber 46: degassing chamber 52: first chamber 54: Two chambers 56: third chamber 58: fourth chamber 62: fifth chamber 64: sixth chamber 70: seventh chamber 100: semiconductor substrate 105: conductive pattern 110: insulating layer 115: opening 120: preliminary diffusion barrier layer 120a: First diffusion barrier layer 120a': first diffusion barrier pattern 130: second diffusion barrier layer 13 (^: second diffusion barrier pattern 140a: anti-deposition layer 140a': anti-deposition pattern 150 · metal layer 150': within metal Connection 152: first metal layer 1521: first metal pattern 26 200834816

2〇y2ipiI 154 : second metal layer 154f : second metal pattern

Claims (1)

200834816 Zb^Zlpit X. Patent Application Scope 1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate having a conductive pattern; patterning the insulating layer on the conductive pattern and the semiconductor substrate, Forming an opening exposing ~ 70% of the 'edge layer, the conductive pattern on the inner wall of the opening and the insulating layer diffusion barrier layer; forming an oxygen supply atom on the M surface to the preliminary diffusion barrier layer And a layer formed on the first diffusion barrier layer to form a metal layer, wherein the metal layer is filled with the opening of the self-touching-heart. 2. The scope of the patent application scope is as follows: The oxygen atom is supplied to the manufacturing boundary of the preliminary ugly second. The grain edge of the wall layer of the bee, the wheat, 3 = Shen Shen The semi-finished product mentioned in the first paragraph of the patent scope / 'The manufacturer of the thermal oxygen treatment process supply device in the factory 4 · If the patent application of the residual solid milk atom. The law, which uses the semiconductor system described by the gas project 5. , ::::: The plasma process provides the first box method for the production of the oxygen atomic clothing, which is a mixture of the two gases of the semiconductor device using Q2 gas, n2〇A^, and 〇3 In the gas, the gas is supplied to the gas, and the gas is supplied to the gas. The gas is supplied to the gas source. The method for producing the semiconductor device according to the first aspect of the invention is further included in the method of manufacturing the semiconductor device. Before the formation of the metal layer, a second diffusion barrier layer is formed on the first diffusion barrier layer. The method for manufacturing a semiconductor device according to claim 6, wherein the first and second diffusions The barrier layer is formed of a refractory metal layer, respectively. - 8 · The manufacturing method of the abundance conductor device according to claim 7 of the patent application method, wherein the refractory metal layer comprises titanium, tantalum (Ta), niobium (10) , at least one of vanadium (V), errone (Zr), strontium (Hi), molybdenum (M 〇), hydrazine (Re), and crane (w) ° 9 as described in claim 7 A method of fabricating a semiconductor device, wherein the refractory metal layer comprises titanium zirconium (TiZr). The method of manufacturing a semiconductor device according to the sixth aspect of the invention, wherein the first and second diffusion barrier layers are respectively formed of a refractory metal nitride layer. 11. The semiconductor device according to claim 10 A succinct method, wherein the refractory metal nitride layer comprises titanium nitride (TiN), nitride #s(TaN), nitrided (NbN), vanadium nitride (VN), zirconium nitride (ZrN), nitrogen At least one of hydrazine oxide (HfN), molybdenum nitride (M〇N), nitrided chain (ReN), and tungsten nitride (WN). The method of fabricating a semiconductor device according to the first aspect of the invention, wherein the refractory metal nitride layer comprises titanium zirconium nitride (TiZrN). The method of manufacturing a semiconductor device according to claim 1, wherein the conductive pattern comprises copper and the metal layer comprises aluminum. The method for manufacturing a semiconductor device according to claim 6, further comprising: ~ patterning the metal layer, the second diffusion barrier layer, and the first diffusion An early P-wall layer to form a first diffusion barrier pattern, a second diffusion barrier pattern, and a metal interconnection, which are sequentially stacked, the metal interconnection filling the opening surrounded by the second diffusion barrier pattern . 〃 15 · The semiconductor method according to claim 14 of the patent application, further comprising: before the formation of the metal layer, the surface layer of the substrate is deposited on the substrate, An anti-deposition layer is formed on a top surface of the second diffusion barrier layer outside the opening and on an upper sidewall of the second diffusion barrier layer in the opening to expose the inside of the opening a lower sidewall of the second diffusion barrier layer, and during formation of the metal interconnect, patterning the anti-deposition layer, thereby forming an anti-deposition pattern under the metal interconnect. 16. The method of manufacturing a semiconductor device according to (4) a fiber-optic material, wherein the metal layer is formed by chemical vapor deposition (CV), and wherein the exposed second diffusion barrier layer The deposition rate of the metal layer is greater than the deposition rate of the metal layer on the anti-deposition layer. The method for manufacturing a semi-conductive device according to the 16th aspect of the invention, wherein the second diffusion barrier layer Formed by a first metal nitride layer, wherein the anti-deposition layer is formed of a second metal nitride layer, and the gas content of the first metal nitride layer is higher than the first gold 30 200834816 zoy/ipi The nitrogen content of the nitride layer. The manufacturing method of the semi-conducting county according to claim 17 wherein the (four) two diffusion barrier phase and the anti-deposition layer comprise the same refractory metal. The method of manufacturing a semiconductor device according to Item 16, wherein the second diffusion barrier layer is formed of a refractory metal layer, and the anti-deposition layer is formed of a refractory metal nitride layer. 15 items The method of fabricating the semiconductor device, wherein the second diffusion barrier layer is formed using a chemical vapor deposition (CVD) technique, and the anti-deposition layer is formed using a physical vapor deposition (pVD) technique. The method of manufacturing a semiconductor device according to Item 15, wherein the conductive pattern, the preliminary diffusion barrier layer, the first diffusion barrier layer, the second diffusion barrier layer, the anti-deposition layer, and the The metal layer is formed using a single group of tools. 22 - A semiconductor device comprising: a semiconductor substrate including a conductive pattern; an insulating layer on the conductive pattern and the semiconductor substrate, the insulating layer having a penetration An opening of the insulating layer to expose a portion of the conductive pattern; a metal interconnect to fill the opening; and a first diffusion barrier pattern disposed between the metal interconnect and the conductive pattern, wherein The first diffusion barrier pattern includes an oxygen atom. 31 200834816 厶丄Pu 23, the semiconductor device according to claim 22, The oxygen atom is located in a grain boundary of the first diffusion barrier pattern. The semiconductor device of claim 22, wherein the conductive pattern comprises copper and the metal interconnect comprises aluminum The semiconductor device according to claim 22, further comprising a second diffusion barrier pattern between the first diffusion barrier pattern and the _ metal interconnection. The semiconductor device of claim 25, wherein the first and second diffusion barrier patterns respectively comprise a refractory metal. The semiconductor device according to claim 10, wherein the refractory metal comprises titanium ( At least one of Ti), group (Ta), sharp (Nb), hunger (V), wrong (Zr), hydrazine (Hf), molybdenum (Mo), strontium (Re), and crane (W). The semiconductor device according to claim 26, wherein the refractory metal comprises TiZr. The semiconductor device of claim 25, wherein the first and second diffusion barrier patterns respectively comprise a refractory metal nitride. The semiconductor device according to claim 29, wherein the refractory metal nitride layer comprises titanium nitride (TiN), nitride button (TaN), nitrided (NbN), nitrogen One of the chemical (VN), nitrided (ZrN), tantalum nitride (HfN), molybdenum nitride (MoN) 'nitrided chain (ReN), and tungsten nitride (WN). The semiconductor device according to claim 29, wherein the refractory metal nitride layer comprises a titanium nitride hammer (TiZrN). The semiconductor device of claim 25, wherein the second diffusion barrier pattern extends to a sidewall of the opening. 32 200834816 /0^2ip^ 33. The semi-finished anti-deposition pattern as described in item 32 of the patent application, the device disposed in the opening, the upper body of the case, and the upper side wall of the case Between the metal two-diffusion barrier patterns in the opening π, the second diffusion barrier in the opening of the upper side wall of the 1 line contacts the metal interconnection. The lower sidewall of the U pattern is straight 34. The second diffusion barrier pattern of the semiconductor of claim 33 includes a first metal, a ^ 沉积 deposition pattern including a second fiber layer, a mouse layer, and The high nitrogen content of the second metal nitride layer is the nitrogen content of the nitride layer.弟孟3^. For example, please refer to the semiconductor device described in Item 34 of Weiwei, the first and second metal nitride layers of 1 include the same refractory metal. /, 36. The semiconductor device of claim 33, wherein the barrier pattern comprises a refractory metal layer, and the anti-deposition pattern comprises a refractory metal nitride layer. a Bayer 37-based semiconductor group tool, comprising: (10)^f' configured to form a preliminary diffusion on a substrate having an opening to supply oxygen atoms to the preliminary diffusion barrier layer to form a ... a layer, and/or a diffusion barrier layer formed on the first diffusion barrier layer; first, configured to be capable of overlying the second diffusion barrier layer in the opening a top surface of the second diffusion barrier layer outside the opening 幵 y is resistant to sinking and layer 'to expose the second diffusion barrier 33 in the opening; 200834816 ZD^ZipiI layer lower sidewall; and second And forming a metal layer on the substrate having the anti-deposition layer to fill the opening. 38. The semiconductor group tool as described in claim 37, further comprising: a fourth room; and a fifth room Wherein the first one is configured to form a preliminary diffusion barrier layer, the fourth chamber is configured to supply oxygen atoms, and the fifth chamber is configured to form a second diffusion barrier layer. 39. The semiconductor group tool of claim 38, wherein the fourth chamber is configured as a clean room, a degassing chamber, and/or a cooling chamber. 40. The semiconductor grouping of claim 39, wherein the clearing is configured to clean a surface of the substrate having the opening 0 41 · as claimed in the patent 圚篦 ^ ^ ^ ^ brother The semiconductor group process of claim 37, wherein the substrate has an insulating layer, and the opening of the trace is positioned to penetrate the layer 0 34