TWI304655B - Thin film transistor and method of manufacturing the same - Google Patents
Thin film transistor and method of manufacturing the same Download PDFInfo
- Publication number
- TWI304655B TWI304655B TW095112469A TW95112469A TWI304655B TW I304655 B TWI304655 B TW I304655B TW 095112469 A TW095112469 A TW 095112469A TW 95112469 A TW95112469 A TW 95112469A TW I304655 B TWI304655 B TW I304655B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- thin film
- film transistor
- gate
- source
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000002161 passivation Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 6
- 239000010408 film Substances 0.000 claims description 5
- -1 hydrogen compound Chemical class 0.000 claims description 5
- 238000000746 purification Methods 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229930195733 hydrocarbon Natural products 0.000 claims description 2
- 239000004575 stone Substances 0.000 claims description 2
- 229910052691 Erbium Inorganic materials 0.000 claims 1
- 239000002253 acid Substances 0.000 claims 1
- 125000003118 aryl group Chemical group 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 claims 1
- 150000002430 hydrocarbons Chemical class 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 238000007373 indentation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- RTZKZFJDLAIYFH-UHFFFAOYSA-N ether Substances CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 150000004945 aromatic hydrocarbons Chemical class 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920000412 polyarylene Polymers 0.000 description 2
- KWTSXDURSIMDCE-QMMMGPOBSA-N (S)-amphetamine Chemical compound C[C@H](N)CC1=CC=CC=C1 KWTSXDURSIMDCE-QMMMGPOBSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229920004449 Halon® Polymers 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229940025084 amphetamine Drugs 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001709 polysilazane Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Description
1304655 - 九、發明說明： : 【發明所屬之技術領域】 本發明係關於薄膜電晶體(Thin Film Transistor, TFT)及其製造 方法。 【先前技術】 在薄膜電晶體液晶顯示器當中，顯示區之透光度取決於液晶 層上下電極之間的電壓差。當薄膜電晶體打開將訊號線電壓寫至 φ 液晶之後，立即將薄膜電晶體關閉，將電荷保持在液晶電容上， 此時所儲存的電荷若有漏失，即會造成液晶電壓的改變，直到新 的電壓再次寫入之前，此電壓的改變不能使受影響的亮度變化量 超過一個灰階，否則可能導致晝質異常。造成電荷漏失的原因， 包括液晶本身和TFT的漏電流。故，薄膜電晶體的漏電流大小會 影響到薄膜電晶體關閉狀態下的電訊號精確度。 請參閱圖1，係一種先前技術薄膜電晶體之結構示意圖。該薄 膜電aa體100包括一基底1〇1、一位於該基底上且位於同一層 _之通道區域U3、源極114及汲極115、一設置於該通道區域113、 源極114及汲極115上之閘極絕緣層1〇4、於該閘極絕緣層綱 上且對應於該通道區域113設置之一閘極1〇5、一形成於該閘極 1〇5及閘極絕緣層104上之鈍化層1〇6、該鈍化層1〇6及閘極絕緣 層1〇4上形成有三接觸孔(未標示)及對應該三接觸孔形成之金屬 層圖案107。其中，該閘極絕緣層1〇4係單純的採用業界常用之氧 化石夕SiOx材質構成，其介電常數約為3.9。 請一併參閱圖2，係上述薄膜電晶體100之製造方法之流程 圖’該薄膜電晶體100之製造方法包括如下步驟： 6 1304655 ” 步驟S10 :提供一玻璃基底ιοί ; ‘ 步驟S11 ··形成汲極、源極及通道區域 於玻璃基底101上沈積非晶石夕層，並使其結晶成多晶石夕薄膜， 摻雜多晶石夕，形成P型半導體層，於該p型半導體層上之一部份 塗佈光阻劑’後由光_做為遮蔽，於該p型 摻雜五價離子，形成-通道_ 113、—雜114及—汲極進= 步驟S12 :形成閘極絕緣層 •,於該通道區域113、源極114及及極II5上沈積氧化石夕si0x 薄膜’形成閘極絕緣層1〇4 ; 步驟S13 :形成閘極圖案 於該閘極絕緣層104上形成閘極1〇5圖案； 步驟S14 :形成鈍化層及接觸孔 於該雜絕緣層104及閘極1〇5上形成鈍化層，依序對該 鈍化層106及閘極絕緣層1〇4進行蝕刻形成接觸孔； 步驟S15 :形成金屬層圖案 • 形成金屬層圖案107，該金屬層圖案搬藉由該接觸孔與該閘 極ι〇5、源極m和汲極lls部分區域歐姆接觸⑽mic _⑽）。 准’先刖技術薄膜電晶體100中，閘極1〇5和通道區域出 之間的介電質，即閘極絕緣層104係單純的採用業界常用之氧化 矽Si〇X材質構成，其介電常數約為3·9，可以看的出，該絕緣層 104之絕緣性有限，故該閘極1〇5與源極114及汲極間會存在 漏電流。該漏電流能給薄膜電晶體1〇〇帶來不良效果，特別當薄 膜電晶體100為關閉狀態時，該漏電流會影響電訊號之精雜， 減低薄膜電晶體100之可靠性，從而影響顯示品質。 7 1304655 φ . 【發明内容】 :有鑑於上述内容，提供一種漏電流較小、可靠性高之薄膜電 晶體實為必要。 還有必要提供一種薄膜電晶體製造方法。 種溥膜電晶體，其包括一基底、一源極、一汲極、一通道 區域、一閘極絕緣層、一鈍化層及一閘極，該源極、汲極及通道 區域开>成於該基底上且位於同一層，該通道區域位於該源極及汲 _ 極之間，該閘極絕緣層形成於該通道區域上，該鈍化層形成於該 源極、汲極及通道區域上，且位於該閘極絕緣層兩側，該鈍化層 介電常數小於閘極絕緣層介電常數，該閘極形成於該閘極絕緣層 及部份鈍化層上，且與該通道區域對應。 一種薄膜電晶體製造方法，其包括以下步驟：提供一基底， 其上形成一半導體層；於該半導體層上沈積氧化矽形成閘極絕緣 層；該閘極絕緣層上形成具預定圖案之閘極；以該閘極為遮蔽， 濕蝕刻該閘極絕緣層，使部份閘極絕緣層餘留於該閘極下方，同 • 時該閘極兩端下方分別形成一缺口；利用閘極當作遮罩，於半導 體層内進行重摻雜，形成汲極及源極；於該閘極、汲極、源極上 及該二缺口内旋塗-鈍化層，該純化層介電常數小於閉極絕緣層 介電常數。 曰 相較於先前技術，本發明之薄膜電晶體將介電常數小於閘極 絕緣層介電常數材質，旋塗於閘極下方兩端，使閉極兩端下方的 等效閘極絕緣層厚度較厚，因此該閘極兩端下方之電阻較大，當 開極輕不變時，鄰近源極及沒極之通道區域兩端之電場較弱: 進而減少電晶體的漏電流和提升電晶體的可靠性。 8 1304655 【實施方式】 清參閱圖3 ’係本發明薄膜電晶體之一較佳實施方式所揭示之 結構示意圖。該薄膜電晶體200包括絕緣基底2〇1、設置於該絕緣 基底201上且位於同一層之通道區域212、源極215及汲極216、 依序設置於該通道區域212上之閘極絕緣層203及閘極214、設置 於該通道區域212、源極215、汲極216及閘極214上之純化層206 及一設置於該鈍化層206上之金屬層圖案207，其中，該鈍化層 _ 206上設置有三接觸孔(未標示），該金屬層圖案2〇7藉由該三接觸 孔與閘極214、源極215和没極216之部分區域歐姆接觸，該通道 區域212長度與該閘極214之長度一致，該閘極絕緣層203相較 於該閘極214兩端分別向内縮進一部份，即該閘極214兩端下方 刀別具有一缺口（未標示）’該純化層206亦延及該閘極214兩端下 方之二缺口。 請一併參閱圖4,係本發明薄膜電晶體200製造方法一較佳實 施方式的流程圖。該薄膜電晶體2〇〇之製造方法具體步驟如下： | 步驟S20 :形成p型半導體層及閘極絕緣層 請參閱圖5，提供一基底201，該基底201為透明基底，且不 可繞性’其材質為玻璃，於該玻璃基底上沈積非晶矽層，並用雷 射退火結晶法使其結晶成多晶矽薄膜，於該多晶石夕薄膜内摻雜三 價離子，形成P型半導體層202，後於該P型半導體層2〇2上沈 積氧化矽Si〇x，形成閘極絕緣層203。其中，該氧化矽Si0x材質 介電常數約為3.9。 步驟S21 :形成閘極圖案 請一併參閱圖6,在該閘極絕緣層203上依序形成一閘極金屬 9 1304655 ;光阻層測，以第—道光罩的圖案對該第一光阻層 • ΓΓ 影，從而形成一預定光阻圖案243，再對該閉極金 曰204進行乾朗，進而形成一閉極214圖案(如圖7所示）。 步驟S22 :形成閛極絕緣層圖案 請-併參閲圖8，移除該光阻圖案243，並以該閘極214當遮 罩’ 刻該閘極絕緣層2〇3，由於·刻為一種等向性㈣ _，因此閘極絕緣層2〇3除了會被向下_之外，也會發生側 #向钱刻，使閘極叫兩端下方的閘極絕緣層2〇3部分 刻分別產生一缺口 213。 步驟S23 :重摻雜形成通道區域、源極及汲極 請一併參閱圖9，利用閘極214當作遮罩，於部分p型半導體 層202 0進行重摻雜五價離子，形成源極215及沒極216。該利用 閘極遮住之部份為通道區域212。 步驟S24 :形成鈍化層，並韻刻形成接觸孔 請一併參閱圖ίο，於該源極215、汲極216及閘極214上旋 •塗(Spin 〇n)一鈍化層206 ’該鈍化層206亦旋塗於該閘極214兩端 下方的二缺口 213内，該鈍化層206上一第二光阻層25〇，以第二 道光罩的圖案對該第二光阻層250進行曝光顯影，從而形成一預 定光阻圖案253，再對該鈍化層206進行乾蝕刻形成三接觸孔 216(如圖11所示）。 該鈍化層206採用之材質為介電常數小於閘極絕緣層介電常 數之一低介電常數材質，其介電常數小於3·9 ,該低介電常數材質 為氨氧氮化物(Hydrogen Silsesquioxane，。 步驟S25 ··形成金屬層圖案 1304655 • 請一併參閱圖12，於該鈍化層206上及三接觸孔内沈積一金 : 屬層，並使圖案化，形成金屬層圖案207，此時該金屬層圖案207 與閘極214、源極215和汲極216部分區域歐姆接觸。 相較於先前技術，本發明之薄膜電晶體200於閘極絕緣層203 兩端為介電常數小於閘極絕緣層203介電常數之一低介電常數材 質’在相同的厚度時，低介電常數材質的跨壓較大，通道區域212 兩端所受到的閘極214電壓耦合較小，因此通道區域212兩端電 I 場強度較小，進而減少薄膜電晶體200的漏電流和提升電晶體的 可靠性，更可以降低電晶體在off狀態下的漏電流。另外，由於閘 極214與金屬層圖案207之間的介電質為一低介電常數材質，因 此閘極214與金屬層圖案207之間的訊號串擾效應也可以同時獲 得減輕緩和(alleviation)。故，進一步提高薄膜電晶體200之可靠 性。 惟，本發明薄膜電晶體及其製造方法並不限於第一實施方式 所述，該低介電常數材質亦可為其他，如矽氧碳氫化合物 ⑩（Methylsilsesquioxane，MSQ)、多孔聚矽氨烷(porous_polysilazane， PPSZ)、苯丙環丁稀(Benzocyclobutene，BCB)、氟化亞芳香 _ (Fluorinated Arylene Ether，FLARE)、芳香族碳氫化合物(SILK)、黑 鑽石（Black Diamond)、有機矽烷高分子（Hybrid Organic
SiloxanePolymer，HOSP)、聚亞芳香醚(p〇lyaryiene Ether, PAE)、類 金剛石(Diamond-like Carbon，DLC)等，該鈍化層206所採用之材 質不限於一種材質，亦可為氨氧氮化物、矽氧碳氫化合物、多孔 聚石夕氨烧、苯丙環丁稀、氟化亞芳香醚、芳香族碳氫化合物、零 鑽石、有機矽烷高分子、聚亞芳香醚或類金剛石等材質中之二種 11 1304655 或二種以上，該基底2〇1亦可為可繞性基底。 綜上所述，本發明確已符合發明專利之要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之較佳實施方式，本發明之 乾圍並不社述實細為限，舉凡熟胃本紐藝之人士援依本發 明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍 内。 【圖式簡單說明】 _ 圖1係一種先前技術薄膜電晶體之結構示意圖。 圖2係一種先前技術薄膜電晶體製造方法流程圖。 圖3係本發明薄膜電晶體之結構示意圖。 圖4係本發明薄膜電晶體製造方法流程圖。 圖5係本發明薄膜電晶體製造方法之形成p型半導體層及閘極絕 緣層之示意圖。 圖6係本發明薄膜電晶體製造方法之沈積閘極金屬層之示意圖。 圖7係本發明薄膜電晶體製造方法之形成閘極之示意圖。 • 圖8係本發明薄膜電晶體製造方法之餘刻閘極絕緣層之示意圖。 圖9係本發明薄膜電晶體製造方法之重摻雜形成源極及汲極之示 意圖。 圖10係本發明薄膜電晶體製造方法之形成純化層之示意圖。 圖Π係本發明薄膜電晶體製造方法之形成接觸孔之示意圖。 圖12係本發明薄膜電晶體製造方法之形成金屬層圖案之示意圖。 【主要元件符號說明】 薄膜電晶體 200 絕緣基底 2Q1 p型半導體層 202 閘極絕緣層 12 1304655 閘極金屬層 204 第一光阻層 240 光阻圖案 243 、 253 閘極 214 缺口 213 金屬層圖案 207 源極 215 汲極 216 通道區域 212 鈍化層 206 接觸孔 216 第二光阻層 250 13
Claims (1)
1304655 ~—j 、 I年月日修(¾正替換頁 十、申請專利範園： 一 ^ 1· 一種薄膜電晶體，其包括： 一基底； 一形成於该基底上之一源極、一通道區域及一汲極，該通道 區域位於該源極及汲極之間； 一形成於该通道區域上之一閘極絕緣層， · 一形成於該源極、汲極及通道區域上，且位於該閘極絕緣層 兩側之鈍化層，該鈍化層介電常數小於閘極絕緣層介電常 一形成於該閘極絕緣層及部份鈍化層」 應之閘極。 «項所述之_電晶體，其中，該閘極絕緣 ittn第=斤述之薄膜電晶體，其中，該鈍化層材 i ，氫化合物、多孔聚魏院、苯丙環^ 八；、取Ϊ日酸、、芳香族碳氫化合物、黑鑽石、有機矽燒言 刀子、♦亞芳香醚或類金剛石之一種戋多種。 问 4=申請專利範圍第！項所述之薄膜電晶體，盆中， 閘極兩端分別向内縮進-部份’於該閘贿兩:形 5.及如至申ifr内圍第4項所述之薄膜電晶體，其中，該純化層延 6·=申請專利範圍第工項所述之薄膜電晶體， 括複數接觸孔。 /、中该鈍化層包 7·利範圍第6項所述之薄膜電晶體，其中 進一步設置有一金屬層圖案， 以鈍化層上 與該閘極、源極及汲極^接觸案错由該複數接觸孔 8.如申请專利範圍第1項所述之薄膜電晶I#， 明且不可繞絲底。仪雜$日日體’財，該基底為透 14 ^ 08 1304655 正替换頁| 方法，其包括以下步驟：… 挺供-基底，其上形成—半導. 於該半導體層上沈積氧化矽形士 具預定圖案緣層; 以=下==，使部份_緣層 沒極及通道區域；、”仏體勒進行錄雜，形成源極 於該閑極、源極、汲極 化層介電常數小於介m塗—鈍化層’該純 10.如申請專利範圍第9項 二電日2 閘極絕緣層材質為氧化石夕材質賴电曰曰體㈣方法，其中，該 策丙^ 丁鍤、虱物、矽氧碳氫化合物、多孔聚矽氨烷、 括蝕㈣π ’進一步包 13ί^ίίΐ=2項所述之薄膜電晶體製造方法，其中，對 方式。 括於該鈍化層上圍：以， 16ίΧ?Η^Γ 15賴述之薄製造綠，其中，該 ^屬層圖—由該接觸孔與該閘極觸。 基底為透明且不可繞性基底。 15 1304655 ^ > 十一、圖式： 97. 8 . 08
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| US11/784,865 US20070235805A1 (en) | 2006-04-07 | 2007-04-09 | TFT array substrate and method for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9773915B2 (en) * | 2013-06-11 | 2017-09-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| KR102065764B1 (ko) | 2013-12-31 | 2020-03-03 | 삼성디스플레이 주식회사 | 박막 트랜지스터 표시판 |
| WO2018068221A1 (en) * | 2016-10-12 | 2018-04-19 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate and display apparatus having the same, and fabricating method thereof |
| CN106898624B (zh) * | 2017-04-28 | 2019-08-02 | 深圳市华星光电技术有限公司 | 一种阵列基板及制备方法、显示装置 |
| US10411047B2 (en) | 2017-04-28 | 2019-09-10 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Array substrate, manufacturing method thereof and display device |
| CN114038761B (zh) * | 2021-09-29 | 2024-10-15 | 苏州矩阵光电有限公司 | 一种半导体钝化结构的制备方法 |
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| JPH0816756B2 (ja) * | 1988-08-10 | 1996-02-21 | シャープ株式会社 | 透過型アクティブマトリクス液晶表示装置 |
| KR100617039B1 (ko) * | 2004-02-26 | 2006-08-30 | 엘지.필립스 엘시디 주식회사 | 액정 표시 장치 및 이의 제조 방법 |
| US7179708B2 (en) * | 2004-07-14 | 2007-02-20 | Chung Yuan Christian University | Process for fabricating non-volatile memory by tilt-angle ion implantation |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW200739914A (en) | 2007-10-16 |
| US20070235805A1 (en) | 2007-10-11 |
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