1299400 -九、發明說明： •【發明所屬之技術領域】 本發明係提供一種凸塊測試方法，尤指一種先利用測 試板與複數個凸塊接合，再將測試板與基板分離產生斷裂 面之測试方法，藉以在單次操作中測試複數個凸塊。 【先前技術】 • 隨著電子科技的不斷進步，凸塊(bump)製程已被大量 應用於帶式自動焊接(tape automatic bonding)、覆晶封裝 (flip chip type package)、覆晶接合技術、晶片尺寸級封裝 (chip scale package，CSP)、光電元件的對外連接(off-chip interconnect)及晶圓級封裝（WLCSP)等技術中。而凸塊與晶 圓、晶粒或是光電元件間是否形成.良好的接合，便是半導 體與封裝繁複之製程中相當重要的一環。倘若此接合之製 • 程中有任何一步驟的操作有所閃失或是材料品質不佳，就 可能導致積體電路產生短路現象、連接點之電阻值過高或 是連接點容易於遭受外力時斷裂等缺陷，而且這些因素都 會造成後續生產出的產品品質不良而難以順利運作。因 此，凸塊與晶圓、晶粒或是光電元件間的接合需經過適當 的測试品管’以確保後續封裝製程的良率。若能於凸塊製 ^ 程中及早察覺問題之所在，就可以阻止品質不良的產品繼 續進行後續的製程，並且立即尋求解決之方案，如此一來 便可以避免浪費不必要的生產成本。 5 1299400 而為了測試凸塊與基板間的接合良度，目前大多是利 用凸塊拉力測試或凸塊剪力測試，以了解凸塊接合之可靠 度或一併找出凸塊接合中最脆弱的環節。 常用的凸塊剪力測試方法，是利用一精密的平切剪力 工具或探針測試凸塊與基板間的附著力。凸塊剪力測試方 法是先將基板固定於測試裝置的平台上，使探針接觸基板 上的凸塊側面，接著移動探針沿著與基板表面平行之方向 移動以使凸塊由基板上移除，.同時得到此移除過程中的應 力數據及斷裂情況。有關於凸塊剪力測試方法相關之技術 可參閱如美國專利號第6,912,915號專利與美國公告第 6,341，530號專利，在此不再詳述其内容。然而，於進行凸 塊剪力測試時，探針在基板表面上的高度必須有相當準確 的控制，這是因為現今積體電路日趨精密化，一般來說探 針的控制精確度需控制在正、負一微米之間，否則探針可 能會與基板表面接觸進而破壞基板。另外，在測試中遭移 除之凸塊碎屑亦可能彈落至基板表面而造成積體電路之破 壞。由於凸塊剪力測試相較之下較為複雜，因此一般要測 試凸塊與基板間的接合機械強度通常是採用凸塊拉力測試 而非凸塊剪力測試。 常用的凸塊拉力測試方法，是將測試裝置之一端與凸 6 1299400 .塊焊接以測試凸塊與基板間的附著力。請參考第1圖與第 2圖。第1圖與第2圖為習知凸塊14拉力測試方法示意圖。 如第1圖所示，首先將基板10固定於測試裝置的平台16 上，接著加熱測試裝置的一金屬端12使之融熔，而後離開 加溫裝置並迅速使融熔金屬端12接觸基板10上的凸塊 • 14，再靜待金屬端12冷卻後與凸塊14接合固定成為一接 合結構。如第2圖所示，然後對測試裝置施加一作用力18， φ 使測試裝置的金屬端12沿基板10之法線方向脫離基板 10，藉以得到此脫離過程.中的應力數據及接合結構之斷裂 ._ 情況。 如上所述，凸塊14拉力測試常用的方式係將測試裝置 的金屬端12焊接至基板10的凸塊14上，而完成測試裝置 至基板10的連接。但由於進行測試的過程要經過加溫與冷 卻兩步驟，而這兩步驟更需要時間來等待溫度變化，所以 * 焊接步驟非但耗能又會使得測試時間增加。另外，融熔金 屬端12 —次只能接合一凸塊14，可是單次取樣的測試方 式卻會有失公允，然若要藉由習知凸塊14拉力測試以了解 待測基板10上之凸塊14與基板10間的接合情形，就必須 在同一待測基板10上針對不同凸塊14反覆進行多次之凸 塊14拉力測試，這卻會致使測試時間更加漫長，且能量消 耗量也隨之增加。 1299400 【發明内容】 種凸塊測試方 進而提升凸塊 因此，本發明之主要目的在於提供一 法，以解決習知技術技術無法克服之難題， 測試之便利性。 、、根據本發明之巾請專難圍，其係揭露—種凸塊測試 Ιΐ接I先提供—基板，且該基板表面包括有複數個凸塊。 ==:Γ板’且該測試板係用以與該基板之該等凸 塊接觸而接合。最後對該測試板施加一作用力，用 測试板與該基板分離產生一斷裂面。^ 可大幅提升單次測試時所測試之方法’本發明 省凸塊測試時間。 凸塊數1，故能有效地節 方式不再侷限於烊 ^本^明中測試板與凸塊接合之 逮且更有效率。 ❿疋利用㈣方式接合，方便、快 為了使責審查委員# 技術内容， 請參二二步了解本㈣之特徵及 而所附圖式僅供友 X明之詳細說明與附圖。然 以限制者。'與輔助說明用，並非用來對本發明加 8 1299400 【實施方式】 請參考第3圖與第4圖。第3圖與第4圖為本發明之 車乂佳實施例進行凸塊24測試之方法示意圖。如第3圖所 示，首先，提供一基板20,基板2〇表面包含有複數個晶 粒區（未示於圖中）以及至少一無效晶粒區22。接著，進行 傳統之凸塊製程，例如可以利用網印或電鍍等方式，於基 板20表面之晶粒區（未示於圖中）與無效晶粒區22上同時 形成複數個凸塊24 ,此為習知相關技藝者或通常知識者所 熟知，在此不多加贅述。在完成凸塊製程之後，基板2〇與 各凸塊24之間可包括有一銲墊26、一保護層28與一凸塊 底層金屬層（under bump metallurgy，UBM) 32 等之凸塊 24 必要結構。根據製程之需要，本發明可於凸塊24形成後即 進行凸塊24測試，亦可於凸塊24經迴焊製程（refi〇w process)後再進行凸塊24測試。此外，本發明亦可利用正 常產品線之生產製程，直接在一測試用之基板上形成複數 個凸塊24來進行測試。 接著提供一測試板34 ’測試板34包含有一平板36與 一黏著層38，並使測試板34之黏著層38與基板20上之 凸塊24接觸而接合。其中，測試板34之黏著層38可以是 一環氧樹脂膠(epoxy glue)等具有高黏著度之材質，用以黏 著基板20上的凸塊24，而黏著層38係設置於平板36之 1299400 部分表面，其配置範圍可根據所對應之無效晶粒區22之凸 塊24數量、大小及配置範圍而定。 隨後將測試板34連接至一測試機台，例如一萬能試驗 機（universal testing machine) 42等裝置，用以對測試板34 施加一作用力44，並紀錄測試時測試板34之位移量以及 紀錄測試時所施加作用力44大小等相關實際測試數據。此 外，為了順利進行凸塊24測試，本發明更可透過真空吸附 的方式固定基板20位置或是利用兩凹槽（未示於圖中）叙固 基板20位置，使得基板20不會隨著測試板34而移動。 如第4圖所示，迨測試板34與基板20接合後，隨即 藉由萬能試驗機42對測試板34施加一作用力44。作用力 44之方向係與基板20之法線平行且朝著遠離基板20的方 向作用，用以把測試板34與基板20分離而產生一斷裂面 46。上述作用力44之施加方向可以測試需求調整，並不侷 限於要與基板20之法線平行且朝著遠離基板20的方向作 用。隨後再進行一破壞模式（failure mode)分析步驟，用以 根據斷裂面46的位置與相關測試數據來分析銲墊26、保 護層28、凸塊底層金屬層32或是凸塊24之製程條件之優 劣。破壞模式分析步驟可以藉由光學顯微鏡（optical microscope, OM)或是電子顯微鏡（scanning electron microscope，SEM)等裝置觀察凸塊24之斷裂面46位置。 1299400 的位置的疋1^著凸塊結構之製程變異，斷裂面46 層_ m板2g，26、賴層28、凸塊底 2〇ir 4等各個結構之中，或是位於基板 =㈣、保護層28、凸塊底層金屬層32或是凸塊24 ;=介面。因此本發明即可藉由測試時所得 :=_面46的位置，來進行破壞模式分析，用 Γ π t ^鮮塾26、保護層28、凸塊底層金屬層以 24之結構強度或是用以檢測基板2。、鲜塾％、 :=8、：塊底層金屬層32或是凸塊24間之各介面的 “強度。透過破壞模式分析，可以整理相 結果’並歸納所需調整之凸塊製程參數成為-整理表用 以當作製程之線上操作及調整參數的依據。 由前述之較佳實施例可知’本發明凸塊測試之方法可 利用黏著層38與基板2G上之凸塊24接合，不^過加、西 與冷卻兩步驟，所以既能節省能源消耗又能減少温度改: 的專待時間。科，本㈣進行單次測試便料合複數個 凸塊，並同時加以測試’不似習知技術一般，在同一美 板上針對不同凸塊反覆進行多次之凸塊測試❹ 試方法更加快速且方便。 凸鬼^ 此外，本發明之測試板％除了可包含有一平板％以 11 1299400 、及一黏著層38之外，亦可同時包含有一平板36、一黏著 層38以及一加熱裝置68。請參考第5圖，第5圖為本發 明之另一較佳實施例進行凸塊24測試之方法示意圖，其中 第5圖之圖示符號係沿用第3圖之相同元件符號。本較佳 實施例係利用加熱裝置68來加熱測試板34之黏著層38以 使黏著層38溫度升高而軟化，接著利用軟化之黏著層38 與基板20之凸塊24相黏結，再分離測試板34與基板20 φ 而產生一斷裂面（未示於圖中），以進行一破壞模式分析步 驟，進而檢測各介面的結合強度。 上述二實施例皆利用測試板34之黏著層38與基板20 上之凸塊24接觸而黏合。由於在測試時基板20上之凸塊 24無須經過加熱軟化之步驟，因此接合後並不會改變凸塊 24之結構，即可用以測試基板20上各結構強度或各結構 之介面的結合強度。 然而，本發明並不受上述二實施例所偈限，其亦可利 用其他方式使測試板34與基板20接合。請參考第6圖。 第6圖為本發明之又一較佳實施例進行凸塊24測試之方法 示意圖，其中第6圖之圖示符號係沿用第3圖之相同元件 符號。如第6圖所示，首先，提供一基板20，並於基板20 表面形成複數個凸塊24,而且在基板20與各凸塊24之間 " 同樣包括有銲墊26、保護層28與凸塊底層金屬層32等之 12 1299400 、凸塊24必要結構。與前述之較佳實施例不同的是，此較佳 實施例之測試板34與凸塊24相接合之方法係利用一迴焊 — 製程加以完成。如此，本較佳實施例更可實際模擬並測試 完成迴焊製程後之凸塊24的結構強度，而第3圖至第5圖 所揭露之較佳實施例則是實際模擬並測試完成各沉積製程 後之各介面的結合強度。 φ 如第6圖所示，本發明之測試板34係包含有一平板 56以及一加熱裝置58，因此可直接利用加熱裝置58來加 熱平板56之部分表面以使基板2〇之凸塊24軟化而與平板 56相黏結。同樣地，測試板34之面積大小係相對應於凸 塊24之數量、大小及配置範圍而設置。迨測試板34與基 板20接合後，再對測試板34施加一作用力44，以使測試 板34與基板2〇分離而產生一斷裂面（未示於圖中），最後 _ 進灯一破壞模式分析步驟，以分析銲塾26、保護層28、凸 塊底層金屬層32或是凸塊24在完成迴焊製程後之結構與 接合強度的狀丨兄。 由；本么明測試凸塊之方法係先利用測試板與複數個 凸塊接觸，接合，接著再施加作用力將測試板與基板分 ，離，因此單次剩試即可測試複數個凸塊，大幅提升單次測 •"式夺所可以/則试之凸塊數量，因此有S地節省凸塊測試之 時間與月匕源。此外，本發明之測試板與凸塊接合的方式不 13 1299400 再侷限於焊接，而可以利用黏著方式接合，方便、快速且 更有效率。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 I 第1圖與第2圖為習知凸塊拉力測試方法示意圖。 第3圖與第4圖為本發明之一較佳實施例進行凸塊測試之 方法示意圖。 第5圖為本發明之另一較佳實施例進行凸塊測試之方法示 ' 意圖。 第6圖為本發明之又一較佳實施例進行凸塊測試之方法示 意圖。 • 【主要元件符號說明】 10 基板 12 金屬端 14 凸塊 16 平台 18 作用力 20 基板 22 無效晶粒區 24 凸塊 26 銲墊 28 保護層 32 凸塊底層金屬層 34 測試板 36 平板 38 黏著層 14 1299400 42 萬能試驗機 44 作用力 46 斷裂面 58 加熱裝置 56 平板 68 加熱裝置1299400 - Nine, the invention description: • [Technical field of the invention] The present invention provides a bump test method, in particular, a method in which a test board is used to bond with a plurality of bumps, and then the test board is separated from the substrate to generate a fracture surface. Test method to test a plurality of bumps in a single operation. [Prior Art] • With the continuous advancement of electronic technology, the bump process has been widely used in tape automatic bonding, flip chip type package, flip chip bonding technology, and wafer. Technology such as chip scale package (CSP), optoelectronic component off-chip interconnect, and wafer level package (WLCSP). Whether the bumps are formed with the crystal, the crystal grains or the photovoltaic elements, a good joint is a very important part of the process of the semiconductor and the packaging. If any of the steps in the process of the joint process are lost or the material quality is poor, it may cause a short circuit in the integrated circuit, the resistance value of the connection point is too high, or the connection point is easy to be subjected to external force. Defects such as breakage, and these factors will cause the quality of the products produced subsequently to be poor and difficult to operate smoothly. Therefore, the bond between the bump and the wafer, the die or the optoelectronic component needs to be properly tested to ensure the yield of subsequent packaging processes. If you can detect the problem early in the bump process, you can prevent the poor quality product from continuing the subsequent process and immediately seek a solution, so as to avoid wasting unnecessary production costs. 5 1299400 In order to test the bonding between the bump and the substrate, most of the current use of the bump tensile test or the bump shear test to understand the reliability of the bump joint or to find the most vulnerable in the bump joint Link. A commonly used bump shear test method uses a precision flat shear tool or probe to test the adhesion between the bump and the substrate. The bump shear test method is to first fix the substrate on the platform of the test device, so that the probe contacts the side of the bump on the substrate, and then move the probe to move in a direction parallel to the surface of the substrate to move the bump from the substrate. In addition, the stress data and the fracture condition during the removal process are obtained at the same time. Techniques relating to the method of the bump shear test can be found in, for example, U.S. Patent No. 6,912,915 and U.S. Patent No. 6,341,530, the disclosure of which is hereby incorporated herein. However, when performing the bump shear test, the height of the probe on the surface of the substrate must be fairly accurately controlled. This is because the current integrated circuit is becoming more and more precise. Generally, the control accuracy of the probe needs to be controlled in the positive. Between one micron and negative, otherwise the probe may contact the surface of the substrate to damage the substrate. In addition, the bumps removed during the test may also bounce off the surface of the substrate and cause damage to the integrated circuit. Since the bump shear test is relatively complicated, the joint mechanical strength between the test bump and the substrate is generally measured by a bump pull test rather than a bump shear test. A commonly used bump pull test method is to solder one end of the test device to the bump 6 1299400 to test the adhesion between the bump and the substrate. Please refer to Figure 1 and Figure 2. Fig. 1 and Fig. 2 are schematic views showing a conventional tensile test method for the bump 14. As shown in Fig. 1, the substrate 10 is first fixed to the platform 16 of the test device, followed by heating a metal end 12 of the test device to melt it, and then leaving the warming device and rapidly bringing the molten metal end 12 into contact with the substrate 10. The upper bumps 14 are then cooled until the metal ends 12 are cooled and joined to the bumps 14 to form a joint structure. As shown in Fig. 2, a force 18 is then applied to the test device, and φ causes the metal end 12 of the test device to be detached from the substrate 10 in the normal direction of the substrate 10, thereby obtaining the stress data and the joint structure in the detachment process. Break._ Situation. As described above, the usual method of the bump 14 tensile test is to solder the metal end 12 of the test device to the bump 14 of the substrate 10 to complete the connection of the test device to the substrate 10. However, since the process of testing is subjected to two steps of heating and cooling, and these two steps require more time to wait for temperature changes, the welding step not only consumes energy but also increases the test time. In addition, the molten metal end 12 can only engage one bump 14 at a time, but the test method of single sampling is unfair, but the conventional bump 14 tensile test is used to understand the substrate 10 to be tested. In the case of the bonding between the bumps 14 and the substrate 10, the bump 14 tensile test must be repeated for the different bumps 14 on the same substrate 10 to be tested, which results in a longer test time and energy consumption. It will increase. 1299400 [Summary of the Invention] The bump test method further enhances the bump. Therefore, the main object of the present invention is to provide a method for solving the problem that the prior art technology cannot overcome, and the convenience of the test. The towel according to the present invention is specifically difficult to cover. It is disclosed that the bump test is provided first, and the substrate surface includes a plurality of bumps. ==: Γ plate' and the test board is used to engage with the bumps of the substrate. Finally, a force is applied to the test plate, and the test plate is separated from the substrate to produce a fracture surface. ^ The method tested in a single test can be greatly improved. The present invention saves the bump test time. Since the number of bumps is 1, it is no longer limited to the effective joint mode and the test board and the bump joint are more efficient. ❿疋 Use (4) to join, convenient and fast. In order to make the review committee # technical content, please refer to the second and second steps to understand the characteristics of this (4) and the drawings are only for the detailed description and drawings of the friend X Ming. However, the limiter. 'With the aid of the explanation, it is not used to add 8 1299400 to the present invention. [Embodiment] Please refer to Figs. 3 and 4. 3 and 4 are schematic views showing a method of testing the bumps 24 in the preferred embodiment of the rudder of the present invention. As shown in Fig. 3, first, a substrate 20 is provided. The surface of the substrate 2 includes a plurality of grain regions (not shown) and at least one invalid grain region 22. Then, a conventional bump process is performed. For example, a plurality of bumps 24 can be simultaneously formed on the surface of the substrate 20 (not shown) and the invalid die region 22 by means of screen printing or plating. It is well known to those skilled in the art or to those skilled in the art, and will not be described here. After the bump process is completed, the substrate 2 and the bumps 24 may include a pad 26, a protective layer 28, and a bump bump metal layer (UBM) 32, etc. . According to the needs of the process, the present invention can perform the bump 24 test after the bump 24 is formed, or the bump 24 test after the bump 24 is subjected to the refi〇 process. In addition, the present invention can also be tested by forming a plurality of bumps 24 directly on a substrate for testing using a production process of a normal product line. Next, a test board 34' is provided. The test board 34 includes a flat plate 36 and an adhesive layer 38, and the adhesive layer 38 of the test board 34 is brought into contact with the bumps 24 on the substrate 20 for bonding. The adhesive layer 38 of the test board 34 may be a high-adhesive material such as epoxy glue for adhering the bumps 24 on the substrate 20, and the adhesive layer 38 is disposed on the flat plate 36 of 1299400. The surface area may be arranged according to the number, size and arrangement range of the bumps 24 of the corresponding invalid crystal grain regions 22. The test board 34 is then coupled to a test machine, such as a universal testing machine 42 for applying a force 44 to the test board 34 and recording the displacement and recording of the test board 34 during the test. The actual test data such as the magnitude of the applied force 44 during the test. In addition, in order to smoothly perform the bump 24 test, the present invention can fix the position of the substrate 20 by vacuum adsorption or fix the position of the substrate 20 by using two grooves (not shown), so that the substrate 20 does not follow the test. The board 34 moves. As shown in Fig. 4, after the cymbal test board 34 is bonded to the substrate 20, a force 44 is applied to the test board 34 by the universal testing machine 42. The direction of the force 44 is parallel to the normal to the substrate 20 and faces away from the substrate 20 for separating the test plate 34 from the substrate 20 to create a fracture surface 46. The direction of application of the force 44 described above can be tested for demand adjustment and is not limited to be parallel to the normal to the substrate 20 and toward the direction away from the substrate 20. A failure mode analysis step is then performed to analyze the process conditions of the pad 26, the protective layer 28, the under bump metal layer 32, or the bumps 24 based on the location of the fracture surface 46 and associated test data. Good or bad. The destruction mode analysis step can observe the position of the fracture surface 46 of the bump 24 by means of an optical microscope (OM) or a scanning electron microscope (SEM). The position of 1299400 is 变异1^ the process variation of the bump structure, the fracture surface is 46 layers _ m plate 2g, 26, the lamella layer 28, the bump bottom 2 〇ir 4 and other structures, or is located on the substrate = (four), Protective layer 28, under bump metal layer 32 or bump 24; = interface. Therefore, the present invention can perform the failure mode analysis by using the position of the == face 46 during the test, using Γ π t ^ fresh 塾 26, the protective layer 28, the underlying metal layer of the bump to have a structural strength of 24 or To detect the substrate 2. , 塾 塾%, :=8,: the underlying metal layer 32 or the interface between the bumps 24 "strength. Through the failure mode analysis, you can sort the phase results" and summarize the required adjustment of the bump process parameters become - The finishing table is used as a basis for online operation and adjustment of parameters of the process. It can be seen from the above preferred embodiment that the method of bump testing of the present invention can utilize the adhesive layer 38 to bond with the bumps 24 on the substrate 2G. Adding, west and cooling two steps, so it can save energy consumption and reduce the temperature change: the special treatment time. Branch, this (four) for a single test will be combined with a number of bumps, and at the same time test 'not like the conventional In general, the bump test method for repeating multiple bumps for different bumps on the same US board is faster and more convenient. In addition, the test board % of the present invention may include a flat panel % to 11 1299400, and In addition to an adhesive layer 38, a flat plate 36, an adhesive layer 38, and a heating device 68 may be simultaneously included. Referring to FIG. 5, FIG. 5 shows a bump 24 test according to another preferred embodiment of the present invention. Method The symbol of Figure 5 is the same as that of Figure 3. The preferred embodiment utilizes a heating device 68 to heat the adhesive layer 38 of the test panel 34 to soften the temperature of the adhesive layer 38, followed by softening. The softened adhesive layer 38 is bonded to the bumps 24 of the substrate 20, and the test board 34 and the substrate 20 φ are separated to generate a fracture surface (not shown) for performing a failure mode analysis step, thereby detecting each interface. The bonding strength of the above two embodiments is bonded by the adhesive layer 38 of the test board 34 in contact with the bumps 24 on the substrate 20. Since the bumps 24 on the substrate 20 do not need to be subjected to the heating softening step during the test, the bonding is performed after the bonding. The structure of the bumps 24 is not changed, and the strength of each structure on the substrate 20 or the bonding strength of the interfaces of the structures can be tested. However, the present invention is not limited to the above two embodiments, and other methods may be used. The test board 34 is bonded to the substrate 20. Please refer to Fig. 6. Fig. 6 is a schematic view showing the method of testing the bumps 24 according to another preferred embodiment of the present invention, wherein the symbol of Fig. 6 follows the third figure. It The same component symbol. As shown in FIG. 6, first, a substrate 20 is provided, and a plurality of bumps 24 are formed on the surface of the substrate 20, and between the substrate 20 and each of the bumps 24, a solder pad 26 is also included. The structure of the protective layer 28 and the underlying metal layer 32 of the bump 12 1299400 and the bump 24 are different. The difference from the preferred embodiment described above is that the test board 34 of the preferred embodiment is bonded to the bump 24. This is accomplished by a reflow process. Thus, the preferred embodiment can more realistically simulate and test the structural strength of the bumps 24 after completion of the reflow process, and the preferred embodiment disclosed in FIGS. 3 through 5 Then, the bonding strength of each interface after each deposition process is actually simulated and tested. φ As shown in Fig. 6, the test board 34 of the present invention comprises a flat plate 56 and a heating device 58, so that the heating device 58 can be directly used. A portion of the surface of the flat plate 56 is heated to soften the bumps 24 of the substrate 2 to bond with the flat plate 56. Similarly, the area of the test board 34 is set corresponding to the number, size, and arrangement range of the bumps 24. After the test board 34 is bonded to the substrate 20, a force 44 is applied to the test board 34 to separate the test board 34 from the substrate 2 to generate a fracture surface (not shown). Finally, the lamp is destroyed. The mode analysis step is to analyze the structure of the solder bump 26, the protective layer 28, the under bump metal layer 32, or the bump 24 after completion of the reflow process. The method of testing the bumps is to first contact the plurality of bumps by using the test board, join, and then apply force to separate the test board from the substrate, so that a plurality of bumps can be tested in a single test. , greatly improve the single-test •" type of the number of bumps that can be / can be tested, so there are S to save the time and the source of the bump test. In addition, the manner in which the test board of the present invention is joined to the bumps is not limited to welding, but can be joined by adhesion, which is convenient, quick and more efficient. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. [Simple diagram of the diagram] I Figures 1 and 2 are schematic diagrams of the conventional bump test method. 3 and 4 are schematic views showing a method of bump testing in accordance with a preferred embodiment of the present invention. Figure 5 is a schematic illustration of a method of bump testing in accordance with another preferred embodiment of the present invention. Figure 6 is a schematic illustration of a method of bump testing in accordance with yet another preferred embodiment of the present invention. • [Main component symbol description] 10 Substrate 12 Metal end 14 Bump 16 Platform 18 Force 20 Substrate 22 Invalid die area 24 Bump 26 Pad 28 Protective layer 32 Bump bottom metal layer 34 Test board 36 Plate 38 Adhesive layer 14 1299400 42 universal testing machine 44 force 46 fracture surface 58 heating device 56 plate 68 heating device
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