TWI297853B - Method for performing in a simd execution engine, apparatus for a simd execution engine, and processing system - Google Patents

Method for performing in a simd execution engine, apparatus for a simd execution engine, and processing system Download PDF

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Publication number
TWI297853B
TWI297853B TW094144840A TW94144840A TWI297853B TW I297853 B TWI297853 B TW I297853B TW 094144840 A TW094144840 A TW 094144840A TW 94144840 A TW94144840 A TW 94144840A TW I297853 B TWI297853 B TW I297853B
Authority
TW
Taiwan
Prior art keywords
bit
execution engine
channel
flag register
output
Prior art date
Application number
TW094144840A
Other languages
English (en)
Chinese (zh)
Other versions
TW200636573A (en
Inventor
Michael Dwyer
Hong Jiang
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200636573A publication Critical patent/TW200636573A/zh
Application granted granted Critical
Publication of TWI297853B publication Critical patent/TWI297853B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
TW094144840A 2004-12-17 2005-12-16 Method for performing in a simd execution engine, apparatus for a simd execution engine, and processing system TWI297853B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/015,778 US7219213B2 (en) 2004-12-17 2004-12-17 Flag bits evaluation for multiple vector SIMD channels execution

Publications (2)

Publication Number Publication Date
TW200636573A TW200636573A (en) 2006-10-16
TWI297853B true TWI297853B (en) 2008-06-11

Family

ID=36123387

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094144840A TWI297853B (en) 2004-12-17 2005-12-16 Method for performing in a simd execution engine, apparatus for a simd execution engine, and processing system

Country Status (8)

Country Link
US (1) US7219213B2 (enExample)
JP (1) JP4901754B2 (enExample)
KR (1) KR100958964B1 (enExample)
CN (1) CN100422979C (enExample)
DE (1) DE112005003130B4 (enExample)
GB (1) GB2436499B (enExample)
TW (1) TWI297853B (enExample)
WO (1) WO2006066262A2 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI427533B (zh) * 2009-12-22 2014-02-21 Intel Corp 用於同步化simd向量的方法，處理器，及系統
TWI562074B (en) * 2011-11-30 2016-12-11 Intel Corp Method to provide vector horizontal compare functionality and processor thereof
TWI587137B (zh) * 2014-12-15 2017-06-11 英特爾公司 經改良之單一指令多重資料（ｓｉｍｄ）的ｋ最近鄰居法之實施技術
US10318291B2 (en) 2011-11-30 2019-06-11 Intel Corporation Providing vector horizontal compare functionality within a vector register

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008071130A (ja) * 2006-09-14 2008-03-27 Ricoh Co Ltd Ｓｉｍｄ型マイクロプロセッサ
EP2478440A1 (en) * 2009-09-17 2012-07-25 Nokia Corp. Multi-channel cache memory
US10255228B2 (en) * 2011-12-06 2019-04-09 Nvidia Corporation System and method for performing shaped memory access operations
GB2536069B (en) * 2015-03-25 2017-08-30 Imagination Tech Ltd SIMD processing module
US20200341772A1 (en) * 2019-04-29 2020-10-29 DeGirum Corporation Efficient Architectures For Deep Learning Algorithms

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2768803B2 (ja) * 1990-04-26 1998-06-25 株式会社東芝 並列演算処理装置
JP2793357B2 (ja) * 1990-11-20 1998-09-03 株式会社東芝 並列演算装置
JP2793342B2 (ja) * 1990-08-09 1998-09-03 株式会社東芝 演算処理装置
US5659722A (en) 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
JP3442225B2 (ja) * 1996-07-11 2003-09-02 株式会社日立製作所 演算処理装置
US5805875A (en) * 1996-09-13 1998-09-08 International Computer Science Institute Vector processing system with multi-operation, run-time configurable pipelines
JP3652518B2 (ja) 1998-07-31 2005-05-25 株式会社リコー Ｓｉｍｄ方式の演算器及び演算処理装置
US20020083311A1 (en) * 2000-12-27 2002-06-27 Paver Nigel C. Method and computer program for single instruction multiple data management
GB2382886B (en) * 2001-10-31 2006-03-15 Alphamosaic Ltd Vector processing system
US6986023B2 (en) * 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags
JP3958662B2 (ja) * 2002-09-25 2007-08-15 松下電器産業株式会社 プロセッサ

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI427533B (zh) * 2009-12-22 2014-02-21 Intel Corp 用於同步化simd向量的方法，處理器，及系統
US8996845B2 (en) 2009-12-22 2015-03-31 Intel Corporation Vector compare-and-exchange operation
TWI562074B (en) * 2011-11-30 2016-12-11 Intel Corp Method to provide vector horizontal compare functionality and processor thereof
US9665371B2 (en) 2011-11-30 2017-05-30 Intel Corporation Providing vector horizontal compare functionality within a vector register
US10318291B2 (en) 2011-11-30 2019-06-11 Intel Corporation Providing vector horizontal compare functionality within a vector register
TWI587137B (zh) * 2014-12-15 2017-06-11 英特爾公司 經改良之單一指令多重資料（ｓｉｍｄ）的ｋ最近鄰居法之實施技術

Also Published As

Publication number Publication date
CN100422979C (zh) 2008-10-01
JP2008524723A (ja) 2008-07-10
JP4901754B2 (ja) 2012-03-21
DE112005003130B4 (de) 2009-09-17
GB2436499A (en) 2007-09-26
US20060149924A1 (en) 2006-07-06
WO2006066262A3 (en) 2006-12-14
US7219213B2 (en) 2007-05-15
CN1790310A (zh) 2006-06-21
GB0713878D0 (en) 2007-08-29
DE112005003130T5 (de) 2007-11-22
TW200636573A (en) 2006-10-16
WO2006066262A2 (en) 2006-06-22
KR20070089208A (ko) 2007-08-30
KR100958964B1 (ko) 2010-05-20
GB2436499B (en) 2009-07-22

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