DE112005003130B4 - Verfahren und Vorrichtung zum Bewerten von Flag-Registern in einer Einzelbefehl-Mehrdaten-Ausführungsmaschine - Google Patents

Verfahren und Vorrichtung zum Bewerten von Flag-Registern in einer Einzelbefehl-Mehrdaten-Ausführungsmaschine Download PDF

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Publication number
DE112005003130B4
DE112005003130B4 DE112005003130T DE112005003130T DE112005003130B4 DE 112005003130 B4 DE112005003130 B4 DE 112005003130B4 DE 112005003130 T DE112005003130 T DE 112005003130T DE 112005003130 T DE112005003130 T DE 112005003130T DE 112005003130 B4 DE112005003130 B4 DE 112005003130B4
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DE
Germany
Prior art keywords
bit
bits
output
execution engine
flag register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE112005003130T
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German (de)
English (en)
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DE112005003130T5 (de
Inventor
Michael El Dorado Hills DWYER
Hong San Jose Jiang
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Intel Corp
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Intel Corp
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Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE112005003130T5 publication Critical patent/DE112005003130T5/de
Application granted granted Critical
Publication of DE112005003130B4 publication Critical patent/DE112005003130B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
DE112005003130T 2004-12-17 2005-12-15 Verfahren und Vorrichtung zum Bewerten von Flag-Registern in einer Einzelbefehl-Mehrdaten-Ausführungsmaschine Expired - Fee Related DE112005003130B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/015,778 2004-12-17
US11/015,778 US7219213B2 (en) 2004-12-17 2004-12-17 Flag bits evaluation for multiple vector SIMD channels execution
PCT/US2005/046321 WO2006066262A2 (en) 2004-12-17 2005-12-15 Evalutation unit for single instruction, multiple data execution engine flag registers

Publications (2)

Publication Number Publication Date
DE112005003130T5 DE112005003130T5 (de) 2007-11-22
DE112005003130B4 true DE112005003130B4 (de) 2009-09-17

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE112005003130T Expired - Fee Related DE112005003130B4 (de) 2004-12-17 2005-12-15 Verfahren und Vorrichtung zum Bewerten von Flag-Registern in einer Einzelbefehl-Mehrdaten-Ausführungsmaschine

Country Status (8)

Country Link
US (1) US7219213B2 (enExample)
JP (1) JP4901754B2 (enExample)
KR (1) KR100958964B1 (enExample)
CN (1) CN100422979C (enExample)
DE (1) DE112005003130B4 (enExample)
GB (1) GB2436499B (enExample)
TW (1) TWI297853B (enExample)
WO (1) WO2006066262A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008071130A (ja) * 2006-09-14 2008-03-27 Ricoh Co Ltd Ｓｉｍｄ型マイクロプロセッサ
US9892047B2 (en) * 2009-09-17 2018-02-13 Provenance Asset Group Llc Multi-channel cache memory
US8996845B2 (en) * 2009-12-22 2015-03-31 Intel Corporation Vector compare-and-exchange operation
US10318291B2 (en) 2011-11-30 2019-06-11 Intel Corporation Providing vector horizontal compare functionality within a vector register
CN105955704B (zh) * 2011-11-30 2018-12-04 英特尔公司 用于提供向量横向比较功能的指令和逻辑
US10255228B2 (en) * 2011-12-06 2019-04-09 Nvidia Corporation System and method for performing shaped memory access operations
US10042813B2 (en) * 2014-12-15 2018-08-07 Intel Corporation SIMD K-nearest-neighbors implementation
GB2536069B (en) * 2015-03-25 2017-08-30 Imagination Tech Ltd SIMD processing module
US20200341772A1 (en) 2019-04-29 2020-10-29 DeGirum Corporation Efficient Architectures For Deep Learning Algorithms

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0682309A2 (en) * 1994-04-28 1995-11-15 International Business Machines Corporation Data processing system adapted for single instruction branching on multiple condition codes from plural processing elements
JP2000047998A (ja) * 1998-07-31 2000-02-18 Ricoh Co Ltd Ｓｉｍｄ方式の演算器及び演算処理装置
US20020083311A1 (en) * 2000-12-27 2002-06-27 Paver Nigel C. Method and computer program for single instruction multiple data management

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2768803B2 (ja) * 1990-04-26 1998-06-25 株式会社東芝 並列演算処理装置
JP2793357B2 (ja) * 1990-11-20 1998-09-03 株式会社東芝 並列演算装置
JP2793342B2 (ja) * 1990-08-09 1998-09-03 株式会社東芝 演算処理装置
JP3442225B2 (ja) * 1996-07-11 2003-09-02 株式会社日立製作所 演算処理装置
US5805875A (en) * 1996-09-13 1998-09-08 International Computer Science Institute Vector processing system with multi-operation, run-time configurable pipelines
GB2382886B (en) * 2001-10-31 2006-03-15 Alphamosaic Ltd Vector processing system
US6986023B2 (en) * 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags
JP3958662B2 (ja) * 2002-09-25 2007-08-15 松下電器産業株式会社 プロセッサ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0682309A2 (en) * 1994-04-28 1995-11-15 International Business Machines Corporation Data processing system adapted for single instruction branching on multiple condition codes from plural processing elements
JP2000047998A (ja) * 1998-07-31 2000-02-18 Ricoh Co Ltd Ｓｉｍｄ方式の演算器及び演算処理装置
US20020083311A1 (en) * 2000-12-27 2002-06-27 Paver Nigel C. Method and computer program for single instruction multiple data management

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, JP 2000-47 998 A
PATENT ABSTRACTS OF JAPAN; & JP 2000 047998 A *

Also Published As

Publication number Publication date
TWI297853B (en) 2008-06-11
GB0713878D0 (en) 2007-08-29
TW200636573A (en) 2006-10-16
CN100422979C (zh) 2008-10-01
GB2436499A (en) 2007-09-26
WO2006066262A2 (en) 2006-06-22
GB2436499B (en) 2009-07-22
JP2008524723A (ja) 2008-07-10
JP4901754B2 (ja) 2012-03-21
US20060149924A1 (en) 2006-07-06
WO2006066262A3 (en) 2006-12-14
US7219213B2 (en) 2007-05-15
CN1790310A (zh) 2006-06-21
DE112005003130T5 (de) 2007-11-22
KR20070089208A (ko) 2007-08-30
KR100958964B1 (ko) 2010-05-20

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R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee