JP2008524723A5 - - Google Patents

Download PDF

Info

Publication number
JP2008524723A5
JP2008524723A5 JP2007547041A JP2007547041A JP2008524723A5 JP 2008524723 A5 JP2008524723 A5 JP 2008524723A5 JP 2007547041 A JP2007547041 A JP 2007547041A JP 2007547041 A JP2007547041 A JP 2007547041A JP 2008524723 A5 JP2008524723 A5 JP 2008524723A5
Authority
JP
Japan
Prior art keywords
evaluation unit
output
bit
execution engine
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007547041A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008524723A (ja
JP4901754B2 (ja
Filing date
Publication date
Priority claimed from US11/015,778 external-priority patent/US7219213B2/en
Application filed filed Critical
Publication of JP2008524723A publication Critical patent/JP2008524723A/ja
Publication of JP2008524723A5 publication Critical patent/JP2008524723A5/ja
Application granted granted Critical
Publication of JP4901754B2 publication Critical patent/JP4901754B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2007547041A 2004-12-17 2005-12-15 単一命令複数データ実行エンジンのフラグレジスタのための評価ユニット Expired - Fee Related JP4901754B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/015,778 2004-12-17
US11/015,778 US7219213B2 (en) 2004-12-17 2004-12-17 Flag bits evaluation for multiple vector SIMD channels execution
PCT/US2005/046321 WO2006066262A2 (en) 2004-12-17 2005-12-15 Evalutation unit for single instruction, multiple data execution engine flag registers

Publications (3)

Publication Number Publication Date
JP2008524723A JP2008524723A (ja) 2008-07-10
JP2008524723A5 true JP2008524723A5 (enExample) 2011-11-24
JP4901754B2 JP4901754B2 (ja) 2012-03-21

Family

ID=36123387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007547041A Expired - Fee Related JP4901754B2 (ja) 2004-12-17 2005-12-15 単一命令複数データ実行エンジンのフラグレジスタのための評価ユニット

Country Status (8)

Country Link
US (1) US7219213B2 (enExample)
JP (1) JP4901754B2 (enExample)
KR (1) KR100958964B1 (enExample)
CN (1) CN100422979C (enExample)
DE (1) DE112005003130B4 (enExample)
GB (1) GB2436499B (enExample)
TW (1) TWI297853B (enExample)
WO (1) WO2006066262A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008071130A (ja) * 2006-09-14 2008-03-27 Ricoh Co Ltd Ｓｉｍｄ型マイクロプロセッサ
EP2478440A1 (en) * 2009-09-17 2012-07-25 Nokia Corp. Multi-channel cache memory
US8996845B2 (en) * 2009-12-22 2015-03-31 Intel Corporation Vector compare-and-exchange operation
US10318291B2 (en) 2011-11-30 2019-06-11 Intel Corporation Providing vector horizontal compare functionality within a vector register
WO2013081588A1 (en) 2011-11-30 2013-06-06 Intel Corporation Instruction and logic to provide vector horizontal compare functionality
US10255228B2 (en) * 2011-12-06 2019-04-09 Nvidia Corporation System and method for performing shaped memory access operations
US10042813B2 (en) * 2014-12-15 2018-08-07 Intel Corporation SIMD K-nearest-neighbors implementation
GB2536069B (en) * 2015-03-25 2017-08-30 Imagination Tech Ltd SIMD processing module
US20200341772A1 (en) * 2019-04-29 2020-10-29 DeGirum Corporation Efficient Architectures For Deep Learning Algorithms

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2768803B2 (ja) * 1990-04-26 1998-06-25 株式会社東芝 並列演算処理装置
JP2793357B2 (ja) * 1990-11-20 1998-09-03 株式会社東芝 並列演算装置
JP2793342B2 (ja) * 1990-08-09 1998-09-03 株式会社東芝 演算処理装置
US5659722A (en) 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
JP3442225B2 (ja) * 1996-07-11 2003-09-02 株式会社日立製作所 演算処理装置
US5805875A (en) * 1996-09-13 1998-09-08 International Computer Science Institute Vector processing system with multi-operation, run-time configurable pipelines
JP3652518B2 (ja) 1998-07-31 2005-05-25 株式会社リコー Ｓｉｍｄ方式の演算器及び演算処理装置
US20020083311A1 (en) * 2000-12-27 2002-06-27 Paver Nigel C. Method and computer program for single instruction multiple data management
GB2382886B (en) * 2001-10-31 2006-03-15 Alphamosaic Ltd Vector processing system
US6986023B2 (en) * 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags
JP3958662B2 (ja) * 2002-09-25 2007-08-15 松下電器産業株式会社 プロセッサ

Similar Documents

Publication Publication Date Title
KR100597930B1 (ko) 라운드 및 시프트를 갖는 ｓｉｍｄ 정수 곱셈 하이
US7490121B2 (en) Modular binary multiplier for signed and unsigned operands of variable widths
EP2284694B1 (en) A method, apparatus, and instruction for performing a sign operation that multiplies
JP6744913B2 (ja) 浮動小数点数の丸め処理
CN100470465C (zh) 用于单指令、多数据执行引擎的条件指令
US20020002666A1 (en) Conditional operand selection using mask operations
US9678716B2 (en) Apparatus and method for performing absolute difference operation
JPH07210369A (ja) 並列加算および平均演算を行うための回路およびその方法
JP2008524723A5 (enExample)
KR102121866B1 (ko) 와이드 데이터 엘리먼트들에 대한 레지스터 쌍을 사용하는 짝수-엘리먼트 및 홀수-엘리먼트 연산들을 가지는 혼합-폭 simd 연산들
TW200808065A (en) Video data compression system and method
US8346828B2 (en) System and method for storing numbers in first and second formats in a register file
US6499046B1 (en) Saturation detection apparatus and method therefor
JP4901754B2 (ja) 単一命令複数データ実行エンジンのフラグレジスタのための評価ユニット
EP1634163B1 (en) Result partitioning within simd data processing systems
US7647368B2 (en) Data processing apparatus and method for performing data processing operations on floating point data elements
TW200405176A (en) Method and apparatus for performing a pixel averaging instruction
JP5732139B2 (ja) データ要素の条件付き選択
US6539408B1 (en) Preconditioning of source data for packed min/max instructions
US6519620B1 (en) Saturation select apparatus and method therefor
CN100395700C (zh) 限制指令宽度处理器中增加寄存器寻址空间的系统与方法
KR20150062651A (ko) 명령어를 실행하는 방법 및 프로세서, 명령어를 부호화하는 방법 및 장치 및 기록매체
JP2003115992A5 (enExample)
US20050210086A1 (en) Data processing apparatus and method for computing an absolute difference between first and second data elements
US8395630B2 (en) Format conversion apparatus from band interleave format to band separate format