•1296438 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種形成半導體封裝基板的方法 ^-種使用_導孔（Via，Pad)製程之形成半= i基板的方法，該製程只需_次於雷 η ^ 鏔拟出逡雪八嵐s 人於电路板兩側全部表面電 鍵开/成—電i屬層，以及-次於球側選擇性 電金屬層’而可以減少電路板兩側表面導電金仏 亚可廣泛應用於微小錫球間距（finebaii奶⑻: 【先前技術】 隨著電子產品㈣則、化的發展趨勢，半導體晶導 體封裝基板（或稱1C載板）製造業者為了提高基板面積的 運用效率，提出了墊内導孔製程’以達到高密度連結的要 求0BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor package substrate, and a method for forming a half = i substrate using a via (Via, Pad) process. The process only needs to be _ times less than the η ^ 鏔 逡 逡 岚 岚 人 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于Conductive gold enamel on both sides of the board can be widely used in tiny solder ball pitch (finebaii milk (8): [Prior Art] With the development trend of electronic products (four), semiconductor crystal conductor package substrate (or 1C carrier board) In order to improve the efficiency of the use of the substrate area, the manufacturer has proposed a via-hole via process to achieve high-density bonding.
圖-A至圖-η係為-習知形成封裝基板之方法之示意 圖'在圖- Α中，首先提供一電路板咖，其兩側分別言^ 有銅荡105。接著’以機械穿鑿的方式定義出通孔 (through-h〇le) 110的位置，如圖一 B所示。在電路板 100之兩側表面以及通孔11()内電卿成—第—導電全屬 層 115 ’ 以形成電鑛導通孔（plated thr〇ugh_h〇ie，ρτΗ) m，如圖一 c所示。並且，在通孔11〇内填入樹脂材料 120，如圖一 D所示。接著，電鍍形成一第二導電金屬層 130 ’以覆盍§亥第-導電層115以及通孔11〇，如圖一£所 示。之後，以光學微影、蝕刻等方式在電路板1〇〇置晶侧 5 1296438 ” 1001與球側1002之銅箔1〇5、第一導電金屬層115與第二 /導電金屬層130内形成圖案化之線路層14〇，如圖_ F所 / 示。在圖一丨中，形成絕緣保護層150以覆蓋圖一 F之圖 . 案化之線路層140 ,並且以光學微影定義出複數個開口 151，曝露出該圖案化線路層140之部分以形成複數個金屬 連接墊141，其中，該球側10〇2之該複數個開口 151係對 • 應於該電鍍導通孔11〇之位置，以形成出複數個金屬連接 、 墊141。最後，在該複數個金屬連接墊141上形成阻障層 _ 180，以完成一封裝基板，如圖一 Η所示。 然而上述之方法的缺點在於必須進行兩次電鍵製程於 電路板兩側全部表面形成導電金屬層，一般均以鍍銅方式 • 形成，使付電路板兩側表面銅厚度過厚，無法滿足輕薄短 小之趨勢。Fig.-A to Fig.-n are schematic diagrams of a conventional method of forming a package substrate. In Fig. Α, a circuit board is first provided, and the sides thereof are respectively provided with a copper slab 105. Next, the position of the through-h〇le 110 is defined by mechanical punching, as shown in Fig. 1B. On both sides of the circuit board 100 and in the through hole 11 (), the first-conducting conductive layer 115' is formed to form an electric conductivity via (plated thr〇ugh_h〇ie, ρτΗ) m, as shown in Fig. 1c. Show. Further, a resin material 120 is filled in the through hole 11A as shown in Fig. 1D. Next, a second conductive metal layer 130' is formed by electroplating to cover the first conductive layer 115 and the via hole 11, as shown in FIG. Thereafter, optical chip, etching, or the like is formed on the circuit board 1 to form the crystal side 5 1296438 ” 1001 and the ball side 1002 of the copper foil 1〇5, the first conductive metal layer 115 and the second/conductive metal layer 130. The patterned circuit layer 14 is shown in Fig. _F. In Fig. 1 , an insulating protective layer 150 is formed to cover the pattern of Fig. F. The circuit layer 140 is patterned, and the complex number is defined by optical lithography. Opening 151, exposing a portion of the patterned wiring layer 140 to form a plurality of metal connection pads 141, wherein the plurality of openings 151 of the ball side 10〇2 are in the position of the plating via 11 To form a plurality of metal connections, pads 141. Finally, a barrier layer _ 180 is formed on the plurality of metal connection pads 141 to complete a package substrate, as shown in FIG. 1. However, the above method has the disadvantage that The conductive metal layer must be formed on the entire surface of both sides of the circuit board by two key processes, which are generally formed by copper plating. The copper thickness on both sides of the circuit board is too thick to meet the trend of lightness and thinness.
U 因此’亟需一種形成封裝基板之方法，其使用墊内導 孔（Via-in-Pad)製程，並且改良習知的電鍍製程，而可 以減少電路板兩側表面鋼之厚度，並可廣泛應用於微小錫 •球間距之設計。 【發明内容】 有4監於習知琴術之缺失，本發明之一主要目的在於提 仏種形成半V體封裝基板的方法，其使用墊内導孔 • (Via in Pad)製程’該製程只需一次於電路板兩側全部 .表面電㈣成導電㈣層，以及—次於_選擇性的電鍍 形成導電金屬層’並可廣泛應用於微小錫球間距之設計。 錢上述目的，轉日倾供成半賴封裝基板 6 1296438 • 的方法，包括以下步驟： 提供-已兀朗案化線路製程之電路板，該電路板之 • 置晶側與球側形成有圖案化線路層，其中，該圖案化線路 •層包括有至>、電錢導線’其延伸至電路板之邊緣，並作 為後續電鑛製程之導線’以及複數個電鑛導通孔貫穿該電 路板並導通電路板置晶側與球侧之圖案化線路層，、並各以 一絕緣保護層’形成於該電路板之置晶侧與球側表面；該 1絕緣保護詹形成複數個第1 口，曝露出該圖案化線靜 #之部分以形成複數個金屬連接塾，其中，該球側之該複& 個第一開口係對應於該電鍍導通孔之位置，其中，該置晶 侧與該球側之金屬連接墊係可電性導通； • 形成導電層，分別覆蓋該置晶側與該球側之表面； 形成阻層，覆蓋該置晶側與該球側之該導電層，並且 '在對應該球側絕緣保護層第一開口之位置上形成複數個第 二開口； 、—藉由該電鑛導線及導電層電鍍導電金屬層於該阻層之 複數個第二開口内：移除該阻層以及該阻層所覆蓋之^導 電層；以及 广以等 形成阻障層於該置晶側及球側之之金屬連接墊上。 本發明更提供一種形成半導體封裝基板的方法， 以下步驟：^ ^ ^ ^ ^ ^ ^ 匕枯 提供一已完成圖案化線路製程之電路板，該電路 - 置晶側與球側形成有圖案化線路層，其中，該圖索^之 層包括複數個電料通孔貫穿料路板並導通電略拓'= 側與球側之圖案化線路層，並各以―絕緣保護層，形成二 7 1296438 該電路板之置晶侧與球侧表面；該絕緣保護層形成複數個 第一開口，曝露出該圖案化線路層之部分以形成複數個金 • 屬連接墊，其中，該球側絕緣保護層之該複數個第一開口 係對應於該電鍍導通孔之位置，以形成出複數個金屬連接 墊，其中，該置晶侧與該球側之金屬連接墊係可電性導通； 形成第一導電層，分別覆蓋該置晶側與該球侧之表面; • 形成第一阻層，覆蓋該置晶侧與該球側之該第一導電 ^ 層，並且在對應該球侧絕緣保護層之第一開口之位置上形 • 成複數個第二開口； 電鍍導電金屬層於該阻層之複數個第二開口内，復形 成阻障層於該球側之金屬連接墊上； ，移除該第一阻層以及該第一阻層所覆蓋之該第一導電 層； 形成第二導電層於該球側之表面，以及形成第二阻層 於該第二導電層上； 形成阻障層於該置晶側之金屬連接墊上；以及 參 移除該第二阻層以及該第二阻層所覆蓋之該第二導電 層。 【實施方式】 為使貴審查委員能對本發明之特徵、目的及功能有 更進一步的認知與瞭解，兹配合圖式詳細說明如後。 圖二A至圖二K為本發明較佳具體實施例之形成半導 體封裝基板的方法之不意圖。 在圖二A中，首先提供一電路板200，其兩侧分別設 8 1296438 有銅箱205。接著，以機械穿馨的方式定義出通孔21〇的 位置，如圖二B所示。在銅箔205之兩侧以及通孔21〇内 形成第一導電金屬層215,以形成電鍍導通孔2η，如圖二 C所示。並且，在通孔210内填入樹脂材料mo，如圖二j) 所示。接著，以光學微影、蝕刻等方式在電路板2〇〇置晶 側2001與該球側2002之銅箔205與第一導電金屬層215 • 上形成圖案化之線路層240。其中，該圖案化線路層24〇 、 包括有至少一電鍍導線240，，其延伸至電路板200之邊 Φ 緣’並作為後縯電鍍製程之導線，如圖二Ε所示。在圖二 F中’形成絕緣保護層250以覆蓋圖二ε之圖案化之線路 層240，並且以光學微影定義出複數個第一開口 251，曝露 出該圖案化線路層240之部分以形成複數個置晶侧2001與 球側2002之金屬連接墊241，該置晶側2001與該球側2002 ‘ 之金屬連接墊241係可電性導通。其中，該球側2002之絕 緣保護層250之該複數個第一開口 251位於該電鍍導通孔 211之位置，以曝露出該球側2002之金屬連接墊241。在 籲 圖二G中，形成導電層265，以覆蓋圖案化之線路層240 以及複數個金屬連接墊241。在圖二Η中，形成阻層270 以覆蓋該導電層265,並且在對應該球側2002第一開口 251 之位置上形成複數個第二開口 261。接著，藉由該電鑛導 線240’及導電層265在該第二開口 261上電鍍形成第二 導電金屬層230，如圖二I所示。移除置晶側2001與球侧 2002上之阻層270與阻層270所覆蓋之導電層265，如圖 二J所示。最後，電鍍形成阻障層280於該置晶侧2001與 球側2002上之金屬連接墊241上，以完成一半導體封裝基 1296438 板，如圖二κ所示。 ' 在本具體實施例中，第一導電金屬層215及第二導電 金屬層230的材質最佳可為銅。 導電層265主要係包括錫（Sn)、銅（Cu)、鉻（Cr)、 鈀（Pd)、鎳（Ni)、錫/鉛（Sn/Pb)與其合金之一者，並 且以濺鍍、蒸鍍、無電電鍍及化學沈積之一者形成。或者， • 導電層265亦可包含導電高分子，而以旋轉塗佈（spin coating)、喷墨印刷（ink-jet printing)、網印（screen % _ printing)或壓印（imprinting)等方式形成。 此外，在本具體實施例中，該阻層270係為乾膜。 此外，在本具體實施例中，該阻障層280係可為鎳/ 金金屬層。 此外，在本具體實施例中，該第二開口 261係可大於、 等於或小於該第一開口 251者。 惟本發明並不以上述材質與手段為限，任何具有本技 術領域之一般技藝者當能構思出其他變化之材質與手段。 • 由以上所述，可知本發明所形成半導體封裝基板僅需 在該球側對應於電鍍導通孔之第二開口上電鍍形成導電金 屬層，較先前技術之進行兩次電鍍製程於電路板兩側全部 表面形成導電金屬層，本發明只需一次於電路板兩側全部 表面電鑛形成導電金屬層，以及一次於球側選擇性的電鍍 . 形成導電金屬層，因此可以減小電路板兩側表面導電金屬 層之厚度。 另外，本發明亦提供另一具體實施例之方法，如圖三A 至圖三N所示。 10 1296438 Λ 在圖三A中，首先提供一電路板300，其兩側表面分 ’ 別設有銅箱305。接著，以機械穿鑿的方式定義出通孔31〇 ' 的位置，如圖三B所示。在銅箔305之兩側以及通孔31〇 内形成第一導電金屬層315，以形成電鍍導通孔311，如圖 三C所示。並且，在通孔310内填入樹脂材料320，如圖 三D所示。接著，以光學微影、姓刻等方式在核心電路板 • 300置晶側3001與球側3〇〇2之銅箔305與第一導電金屬 層315内形成圖案化之線路層340。其中，該圖案化線路 • 層340不包括有任何電鍍導線，故須於後續製程形成導電 層作為電鍍置晶側金屬連接墊阻障層之導線，如圖三E所 示。在圖三F中，形成絕緣保護層350以覆蓋圖三E之圖 案化之線路層340，並且以光學微影定義出複數個第一開 口 351，曝露出該圖案化線路層340之部分以形成複數個 ' 置晶側3001與球側3002之金屬連接墊341，該置晶側3001 與該球側3002之金屬連接墊341係可電性導通，其中，該 球側3002絕緣保護層350之該複數個第一開口 351位於該 φ 電鍍導通孔311之位置，以曝露出該球側3002之金屬連接 塾341。在圖三G中’形成第一導電層365，以覆蓋圖案化 之線路層340以及複數個金屬連接墊341。在圖三Η中， 形成第一阻層370以覆蓋該導電層365，並且對應該球側 3002第一開口 351之位置上形成複數個第二開口 361。接 、 著，藉由該導電層365在該第二開口361上形成第二導電 / 金屬層330,如圖三I所示。形成一阻障層380於球侧3002 之金屬連接墊341上，如圖三j所示。移除置晶側3001與 球側3002上之第一阻層370與導電層365,如圖三Κ所示。 1296438 在球側3002上形成第二導電層385以及覆蓋該第二導電層 385之一第二阻層390，如圖三L所示。接著，形成一阻障 _ 層380於置晶侧3001之金屬連接墊341上。最後，移除球 侧3002上之第二導電層385以及覆蓋該第二導電層385之 該第二阻層390，以完成一半導體封裝基板，如圖三N所 示。 • 在本具體實施例中，第一導電金屬層315及第二導電 、 金屬層330的材質最佳可為銅。 • 第一導電層365主要係包括錫（Sn)、銅（Cu)、鉻（Cr)、 鈀（Pd)、鎳（Ni)、錫/鉛（Sn/Pb)與其合金之一者，並 且以濺鍍、蒸鍍、無電電鍍及化學沈積之一者形成。或者， 導電層330亦可包含導電高分子，而以旋轉塗佈（spin coating)、喷墨印刷（ink-jet printing)、網印（screen printing)或壓印（imprinting)等方式形成。 此外，在本具體實施例中，第二導電層385主要係包 括錫（Sn)、銅（Cu)、鉻（Cr)、I巴（Pd)、鎳（Ni)、錫/ φ 錯（Sn/Pb)與其合金之一者，並且以濺鑛形成。此外，在 本具體實施例中，該第一阻層370與第二阻層390係為乾 膜。 此外，在本具體實施例中，該阻障層380係可為電鍍 鎳/金金屬層。 ， 此外，在本具體實施例中，該第二開口 361係可大於、 / 等於或小於該第一開口 351者。 惟本發明並不以上述材質與手段為限，任何具有本技 術領域之一般技藝者當能構思出其他變化之材質與手段。 12 1296438 前技術之進二次:二形成半導體封裝基板較先 電金屬層’本發；!路板兩側全部表面形成導 成導電金屬層， ，上：可，電路板兩側表面導“ 二上所述，萄知本發明之形成封 又 墊内導孔製程，該製程只需―^·兩丄’其使用 電金屬声，Λ9、' 於球側選擇性的電錢形成導 声、，e 11以減少電路板兩側表面導電金屬層之厚 又’亚可廣泛應用於微小錫球間距 曰 ::功::發明，-富有•二== 專利申:付ί專利申請要件無疑，爰依法提請發明 德便。"丄"胃審查委員早日賜予本發明專利，實感 來限准定"^=者，僅為本發明之較佳實施例而已，並非用 發明貫施之範圍’即凡依本發明申請專利範圍所 Ϊ 造、特徵、精神及方法所為之均等變化與修 飾’均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 土圖-A至圖- Η係為-習知形成半導體封裝基板的方 法之示意圖； 娜圖二Α至圖二Κ係為本發明較佳具體實施例之形成半 ¥體封裝基板的方法之示意圖； 圖三A至圖三韻為本發明另—具體實施例之形成半 13 1296438 導體封裝基板的方法之示意圖。 ' 【主要元件符號說明】 100核心電路板 1001置晶侧 1002球侧 • 105銅箔 ^ 110通孔 • 111電鍍導通孔 115第一導電層 12 0樹脂材料 130第二導電層 140圖案化之線路層 141金屬連接墊 150絕緣保護層 151 開口 • 180阻障層 200核心電路板 2001置晶側 2002球侧 205銅箔 . 210通孔 ^ 211電鑛導通孔 215第一導電金羼層 2 2 0樹脂材料 14 1296438 230第二導電金屬層 : 240圖案化之線路層 240’ 電鍍導線 241金屬連接墊 250絕緣保護層 251第一開口 • 261第二開口 , 265導電層 鲁 270阻層 280阻障層 300核心電路板 3001置晶側 3002球侧 305銅箔 310通孔 311電鍍導通孔 • 315第一導電金屬層 320樹脂材料 330第二導電金屬層 340圖案化之線路層 341金屬連接墊 . 350絕緣保護層 ， 351第一開口 361第二開口 365第一導電層 1296438 370第一阻層 380阻障層 385第二導電層 390第二阻層U therefore, there is a need for a method of forming a package substrate which uses a Via-in-Pad process and improves the conventional plating process, thereby reducing the thickness of the steel on both sides of the board and can be widely used. Used in the design of tiny tin and ball pitch. SUMMARY OF THE INVENTION There is a lack of conventional music, one of the main purposes of the present invention is to improve the method of forming a semi-V body package substrate, which uses a Via in Pad process. Once on both sides of the board, the surface is electrically (four) conductive (four) layer, and - next to _ selective plating to form a conductive metal layer 'and can be widely used in the design of tiny solder ball pitch. For the above purpose, the method of diverting the supply to the packaging substrate 6 1296438 • includes the following steps: Providing a circuit board for the circuitized circuit process, wherein the patterned side and the ball side are patterned a circuit layer, wherein the patterned circuit layer includes a light source wire that extends to the edge of the circuit board and serves as a conductor for the subsequent electric ore process and a plurality of electrical ore vias through the circuit board And the patterned circuit layer on the crystal side and the ball side of the circuit board is turned on, and each of the insulating layer is formed on the crystal side and the ball side surface of the circuit board; the 1 insulation protection forms a plurality of first ports Exposing a portion of the patterned line static to form a plurality of metal connection ports, wherein the first opening of the ball side corresponds to a position of the plated via hole, wherein the crystal side is The metal connection pads on the ball side are electrically conductive; • a conductive layer is formed to cover the surface of the crystal side and the ball side respectively; a resist layer is formed to cover the conductive layer on the crystal side and the ball side, and 'In the opposite side of the ball Forming a plurality of second openings at a position of the first opening of the edge protection layer; - plating a conductive metal layer in the plurality of second openings of the resist layer by the electric ore wire and the conductive layer: removing the resist layer and the a conductive layer covered by the resist layer; and a barrier layer formed on the metal connection pads on the crystal side and the ball side. The present invention further provides a method of forming a semiconductor package substrate, the following steps: ^ ^ ^ ^ ^ ^ ^ provide a circuit board that has completed the patterned circuit process, the circuit - the patterned side and the ball side form a patterned circuit a layer, wherein the layer of the cable comprises a plurality of electrical material through holes extending through the material path plate and electrically conducting a slightly alternating '= side and ball side patterned circuit layers, and each having an "insulation protective layer" to form two 7 1296438 a plate side and a ball side surface of the circuit board; the insulating protection layer forms a plurality of first openings exposing portions of the patterned circuit layer to form a plurality of metal connection pads, wherein the ball side insulation layer The plurality of first openings are corresponding to the positions of the plating vias to form a plurality of metal connection pads, wherein the metal connection pads of the crystal side and the ball side are electrically conductive; forming a first conductive a layer covering the surface of the crystallizing side and the ball side respectively; • forming a first resist layer covering the first conductive layer of the crystallizing side and the ball side, and corresponding to the ball side insulating protective layer Shape of an opening Forming a plurality of second openings; plating a conductive metal layer in the plurality of second openings of the resist layer to form a barrier layer on the metal connection pad of the ball side; removing the first resist layer and the first resistor a first conductive layer covering the layer; forming a second conductive layer on the surface of the ball side, and forming a second resist layer on the second conductive layer; forming a barrier layer on the metal connection pad of the crystallizing side; And removing the second resist layer and the second conductive layer covered by the second resist layer. [Embodiment] In order to enable the reviewing committee to have a further understanding and understanding of the features, objects and functions of the present invention, the detailed description will be made in conjunction with the drawings. 2A through 2K are schematic views of a method of forming a semiconductor package substrate in accordance with a preferred embodiment of the present invention. In Fig. 2A, a circuit board 200 is first provided with 8 1296438 copper boxes 205 on both sides. Next, the position of the through hole 21〇 is defined in a mechanically permeable manner as shown in Fig. 2B. A first conductive metal layer 215 is formed on both sides of the copper foil 205 and in the through holes 21A to form a plating via 2n as shown in Fig. 2C. Further, a resin material mo is filled in the through hole 210 as shown in Fig. 2). Next, a patterned wiring layer 240 is formed on the crystal side 2001 of the circuit board 2 and the copper foil 205 and the first conductive metal layer 215 of the ball side 2002 by optical lithography, etching, or the like. The patterned circuit layer 24A includes at least one plated wire 240 extending to the edge Φ edge of the circuit board 200 and serving as a wire for the post-plating process, as shown in FIG. In FIG. 2F, 'the insulating protective layer 250 is formed to cover the patterned wiring layer 240 of FIG. 2, and a plurality of first openings 251 are defined by optical lithography to expose portions of the patterned wiring layer 240 to form The metal connection pads 241 of the plurality of crystallizing sides 2001 and the ball side 2002 are electrically conductively connected to the metal connection pads 241 of the ball side 2002'. The plurality of first openings 251 of the insulating protective layer 250 of the ball side 2002 are located at the position of the plating via 211 to expose the metal connection pads 241 of the ball side 2002. In FIG. 2G, a conductive layer 265 is formed to cover the patterned wiring layer 240 and a plurality of metal connection pads 241. In Fig. 2, a resist layer 270 is formed to cover the conductive layer 265, and a plurality of second openings 261 are formed at positions corresponding to the first opening 251 of the ball side 2002. Then, the second conductive metal layer 230 is formed on the second opening 261 by the electric ore wire 240' and the conductive layer 265, as shown in FIG. The conductive layer 265 covered by the resist layer 270 and the resist layer 270 on the crystal side 2001 and the ball side 2002 is removed as shown in FIG. Finally, a barrier layer 280 is formed on the metallization pad 241 on the crystallizing side 2001 and the ball side 2002 to complete a semiconductor package substrate 1296438, as shown in FIG. In the present embodiment, the material of the first conductive metal layer 215 and the second conductive metal layer 230 may preferably be copper. The conductive layer 265 mainly includes one of tin (Sn), copper (Cu), chromium (Cr), palladium (Pd), nickel (Ni), tin/lead (Sn/Pb) and its alloy, and is sputtered, One of vapor deposition, electroless plating, and chemical deposition is formed. Alternatively, the conductive layer 265 may also comprise a conductive polymer formed by spin coating, ink-jet printing, screen % _ printing or imprinting. . Moreover, in the specific embodiment, the resist layer 270 is a dry film. Moreover, in this embodiment, the barrier layer 280 can be a nickel/gold metal layer. Moreover, in the specific embodiment, the second opening 261 can be larger than, equal to, or smaller than the first opening 251. However, the present invention is not limited to the above materials and means, and any material and means that can be conceived by those skilled in the art can be conceived. From the above, it can be seen that the semiconductor package substrate formed by the present invention only needs to be plated to form a conductive metal layer on the second opening corresponding to the plated via hole on the ball side, and two electroplating processes are performed on both sides of the circuit board according to the prior art. The surface of the entire surface forms a conductive metal layer. The present invention only needs to form a conductive metal layer on all sides of the circuit board at one time and a selective plating on the ball side at one time. Forming a conductive metal layer, thereby reducing the surface of both sides of the circuit board. The thickness of the conductive metal layer. In addition, the present invention also provides a method of another embodiment, as shown in FIG. 3A to FIG. 10 1296438 Λ In Figure 3A, a circuit board 300 is first provided with a copper box 305 on both sides. Next, the position of the through hole 31 〇 ' is defined by mechanical drilling, as shown in FIG. 3B. A first conductive metal layer 315 is formed on both sides of the copper foil 305 and through holes 31A to form a plating via 311 as shown in FIG. Further, a resin material 320 is filled in the through hole 310 as shown in Fig. 3D. Next, a patterned wiring layer 340 is formed in the copper foil 305 of the core circuit board, the 300 crystal side 3001, and the ball side 3〇〇2, and the first conductive metal layer 315 by optical lithography, surname, or the like. Wherein, the patterned circuit layer 340 does not include any electroplated wires, so a conductive layer is formed in the subsequent process as a wire for plating the metal-side metal pad barrier layer, as shown in FIG. 3E. In FIG. 3F, an insulating protective layer 350 is formed to cover the patterned wiring layer 340 of FIG. 3E, and a plurality of first openings 351 are defined by optical lithography to expose portions of the patterned wiring layer 340 to form a plurality of metal connection pads 341 of the crystallizing side 3001 and the ball side 3002, wherein the crystallizing side 3001 and the metal connection pad 341 of the ball side 3002 are electrically conductive, wherein the ball side 3002 insulating protective layer 350 A plurality of first openings 351 are located at the φ plated vias 311 to expose the metal pads 341 of the ball side 3002. A first conductive layer 365 is formed in FIG. 3G to cover the patterned wiring layer 340 and a plurality of metal connection pads 341. In Fig. 3, a first resist layer 370 is formed to cover the conductive layer 365, and a plurality of second openings 361 are formed at positions corresponding to the first opening 351 of the ball side 3002. A second conductive/metal layer 330 is formed on the second opening 361 by the conductive layer 365, as shown in FIG. A barrier layer 380 is formed on the metal connection pad 341 of the ball side 3002 as shown in FIG. The first resist layer 370 and the conductive layer 365 on the crystal side 3001 and the ball side 3002 are removed, as shown in FIG. 1296438 forms a second conductive layer 385 on the ball side 3002 and a second resist layer 390 covering the second conductive layer 385, as shown in FIG. Next, a barrier layer 380 is formed on the metal connection pad 341 of the crystallographic side 3001. Finally, the second conductive layer 385 on the ball side 3002 and the second resist layer 390 covering the second conductive layer 385 are removed to complete a semiconductor package substrate, as shown in FIG. In the specific embodiment, the material of the first conductive metal layer 315 and the second conductive metal layer 330 may be copper. • The first conductive layer 365 mainly includes one of tin (Sn), copper (Cu), chromium (Cr), palladium (Pd), nickel (Ni), tin/lead (Sn/Pb) and its alloy, and One of sputtering, evaporation, electroless plating, and chemical deposition. Alternatively, the conductive layer 330 may also include a conductive polymer, and is formed by spin coating, ink-jet printing, screen printing, or imprinting. In addition, in the specific embodiment, the second conductive layer 385 mainly includes tin (Sn), copper (Cu), chromium (Cr), I bar (Pd), nickel (Ni), tin / φ (Sn / Pb) is one of its alloys and is formed by splashing. In addition, in the specific embodiment, the first resist layer 370 and the second resist layer 390 are dry films. Moreover, in this embodiment, the barrier layer 380 can be an electroplated nickel/gold metal layer. In addition, in the specific embodiment, the second opening 361 can be greater than, / equal to, or smaller than the first opening 351. However, the present invention is not limited to the above materials and means, and any material and means that can be conceived by those skilled in the art can be conceived. 12 1296438 The advancement of the former technology: two formation of the semiconductor package substrate than the first electrical metal layer 'this hair;! The entire surface of both sides of the road plate is formed into a conductive metal layer, upper: Yes, the surface of both sides of the circuit board guide "two As described above, it is known that the method for forming a via hole in the sealing and the pad of the present invention requires only "^·· two 丄', which uses an electric metal sound, and Λ9, 'a selective charge on the ball side to form a sound guide, e 11 to reduce the thickness of the conductive metal layer on both sides of the board and 'Asia can be widely used in tiny solder ball spacing ::: work:: invention, - rich • two == patent application: payment patent application requirements undoubtedly, 爰According to the law, the invention is in accordance with the law. The "sickness of the stomach" is given to the patent of the invention at an early date, and the actual sense is limited to the preferred embodiment of the present invention. Equivalent changes and modifications of the invention, the features, the spirit and the method are all included in the scope of the patent application of the present invention. [Simple Description] Soil Map-A to Figure-Η For the purpose of forming a semiconductor package substrate BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3A to FIG. 3 are schematic diagrams showing a method for forming a half-body package substrate according to a preferred embodiment of the present invention; FIG. Half 13 1296438 Schematic diagram of the method of conductor package substrate. ' [Main component symbol description] 100 core circuit board 1001 crystal side 1002 ball side • 105 copper foil ^ 110 through hole • 111 plating via 115 first conductive layer 12 0 resin Material 130 second conductive layer 140 patterned circuit layer 141 metal connection pad 150 insulation protection layer 151 opening • 180 barrier layer 200 core circuit board 2001 crystal side 2002 ball side 205 copper foil. 210 through hole ^ 211 electric mine conduction Hole 215 first conductive gold layer 2 2 0 resin material 14 1296438 230 second conductive metal layer: 240 patterned circuit layer 240' plating wire 241 metal connection pad 250 insulation protection layer 251 first opening • 261 second opening, 265 conductive layer Lu 270 resist layer 280 barrier layer 300 core circuit board 3001 crystal side 3002 ball side 305 copper foil 310 through hole 311 plating through hole • 315 first conductive metal layer 320 resin material 330 second conductive gold Layer 340 is patterned circuit layer 341 of the metal connection pads. Insulating protective layer 350, a first opening 361 the second opening 351 of the first conductive layer 365 of the first resist layer 380 1296438370 barrier layer 385 of the second conductive layer 390 of the second barrier layer