TWI288975B - A method and system for forming a feature in a high-k layer - Google Patents

A method and system for forming a feature in a high-k layer Download PDF

Info

Publication number
TWI288975B
TWI288975B TW094134227A TW94134227A TWI288975B TW I288975 B TWI288975 B TW I288975B TW 094134227 A TW094134227 A TW 094134227A TW 94134227 A TW94134227 A TW 94134227A TW I288975 B TWI288975 B TW I288975B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
dielectric constant
high dielectric
plasma
Prior art date
Application number
TW094134227A
Other languages
English (en)
Chinese (zh)
Other versions
TW200629542A (en
Inventor
Akiteru Ko
Annie Xia
Lee Chen
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200629542A publication Critical patent/TW200629542A/zh
Application granted granted Critical
Publication of TWI288975B publication Critical patent/TWI288975B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32697—Electrostatic control
    • H01J37/32706—Polarising the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H10P14/6532—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour by exposure to a plasma
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H10P50/285—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means of materials not containing Si, e.g. PZT or Al2O3
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW094134227A 2004-09-30 2005-09-30 A method and system for forming a feature in a high-k layer TWI288975B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/954,104 US7361608B2 (en) 2004-09-30 2004-09-30 Method and system for forming a feature in a high-k layer

Publications (2)

Publication Number Publication Date
TW200629542A TW200629542A (en) 2006-08-16
TWI288975B true TWI288975B (en) 2007-10-21

Family

ID=36098050

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094134227A TWI288975B (en) 2004-09-30 2005-09-30 A method and system for forming a feature in a high-k layer

Country Status (4)

Country Link
US (1) US7361608B2 (enExample)
JP (1) JP2008515220A (enExample)
TW (1) TWI288975B (enExample)
WO (1) WO2006038974A2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050101147A1 (en) * 2003-11-08 2005-05-12 Advanced Micro Devices, Inc. Method for integrating a high-k gate dielectric in a transistor fabrication process
US20060151846A1 (en) * 2005-01-13 2006-07-13 International Business Machines Corporation Method of forming HfSiN metal for n-FET applications
JP5280670B2 (ja) * 2007-12-07 2013-09-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7834387B2 (en) * 2008-04-10 2010-11-16 International Business Machines Corporation Metal gate compatible flash memory gate stack
JP2009295621A (ja) * 2008-06-02 2009-12-17 Panasonic Corp 半導体装置及びその製造方法
US8975706B2 (en) 2013-08-06 2015-03-10 Intermolecular, Inc. Gate stacks including TaXSiYO for MOSFETS
CN110993567B (zh) * 2019-12-09 2022-08-30 中国科学院微电子研究所 一种半导体结构及其形成方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6727148B1 (en) * 1998-06-30 2004-04-27 Lam Research Corporation ULSI MOS with high dielectric constant gate insulator
US6709715B1 (en) * 1999-06-17 2004-03-23 Applied Materials Inc. Plasma enhanced chemical vapor deposition of copolymer of parylene N and comonomers with various double bonds
US6348420B1 (en) * 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
US6492283B2 (en) * 2000-02-22 2002-12-10 Asm Microchemistry Oy Method of forming ultrathin oxide layer
EP1297565A2 (en) * 2000-06-26 2003-04-02 North Carolina State University Novel non-crystalline oxides for use in microelectronic, optical, and other applications
US6660660B2 (en) * 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
JP2002343790A (ja) * 2001-05-21 2002-11-29 Nec Corp 金属化合物薄膜の気相堆積方法及び半導体装置の製造方法
US6806095B2 (en) * 2002-03-06 2004-10-19 Padmapani C. Nallan Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers
CN100561684C (zh) * 2002-03-29 2009-11-18 东京毅力科创株式会社 基底绝缘膜的形成方法
US6787440B2 (en) * 2002-12-10 2004-09-07 Intel Corporation Method for making a semiconductor device having an ultra-thin high-k gate dielectric
US6750126B1 (en) * 2003-01-08 2004-06-15 Texas Instruments Incorporated Methods for sputter deposition of high-k dielectric films
WO2004066376A1 (ja) * 2003-01-17 2004-08-05 Fujitsu Limited 誘電体膜の形成方法
US6869542B2 (en) * 2003-03-12 2005-03-22 International Business Machines Corporation Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials
US6696327B1 (en) * 2003-03-18 2004-02-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
JP2005039015A (ja) * 2003-07-18 2005-02-10 Hitachi High-Technologies Corp プラズマ処理方法および装置
JP2007516599A (ja) * 2003-08-04 2007-06-21 エーエスエム アメリカ インコーポレイテッド ゲルマニウム上の堆積前の表面調製
US7303996B2 (en) * 2003-10-01 2007-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics
US7115530B2 (en) * 2003-12-03 2006-10-03 Texas Instruments Incorporated Top surface roughness reduction of high-k dielectric materials using plasma based processes
KR100568516B1 (ko) * 2004-02-24 2006-04-07 삼성전자주식회사 후처리 기술을 사용하여 아날로그 커패시터를 제조하는 방법
US20050205969A1 (en) * 2004-03-19 2005-09-22 Sharp Laboratories Of America, Inc. Charge trap non-volatile memory structure for 2 bits per transistor
JP4919586B2 (ja) * 2004-06-14 2012-04-18 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7323423B2 (en) * 2004-06-30 2008-01-29 Intel Corporation Forming high-k dielectric layers on smooth substrates
US7439113B2 (en) * 2004-07-12 2008-10-21 Intel Corporation Forming dual metal complementary metal oxide semiconductor integrated circuits

Also Published As

Publication number Publication date
US7361608B2 (en) 2008-04-22
WO2006038974A2 (en) 2006-04-13
US20060065938A1 (en) 2006-03-30
JP2008515220A (ja) 2008-05-08
TW200629542A (en) 2006-08-16
WO2006038974A3 (en) 2009-04-23

Similar Documents

Publication Publication Date Title
JP6334631B2 (ja) 金属インターコネクトのために絶縁積層体を選択的にエッチングする方法
JP5238704B2 (ja) ハフニウム含有材料を乾式エッチングする方法およびシステム
TWI364631B (en) Methods of removing photoresist from substrates
TW201034116A (en) Profile and CD uniformity control by plasma oxidation treatment
TW515034B (en) Semiconductor device adhesive layer structure and process for forming structure
TW201417181A (zh) 蝕刻及灰化期間低ｋ材料之側壁保護
TW201234474A (en) Plasma etching apparatus, plasma etching method, and semiconductor device manufacturing method
TW200836261A (en) Method for selective removal of damaged multi-stack bilayer films
TW201243905A (en) Method for forming a pattern and a semiconductor device manufacturing method
TW200913050A (en) In-situ photoresist strip during plasma etching of active hard mask
TW201342445A (zh) 用以形成半導體裝置之方法
TW200822199A (en) Method for producing bonded wafer
TWI323487B (en) Plasma etching method
TW201125071A (en) Process for manufacturing semiconductor device
TW201201257A (en) Differential metal gate etching process
TW201246363A (en) Method for patterning a full metal gate structure
TWI253691B (en) Plasma treatment and etching process for ultra-thin dielectric films
TWI259512B (en) Semiconductor device and method for forming the same
TW200926286A (en) Method for etching metal nitride with high selectivity to other materials
JP5633928B2 (ja) 深溝ライナ除去方法
TW201248719A (en) Substrate processing method and storage medium
TW201001535A (en) Method of semiconductor processing
TW399268B (en) Methods and compositions for post-etch layer stack treatment in semiconductor fabrication
TWI293649B (en) A method for processing a substrate
TW202322214A (zh) 金屬蝕刻方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees