TWI288437B - Method to define a pattern having shrunk critical dimension - Google Patents

Method to define a pattern having shrunk critical dimension Download PDF

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Publication number
TWI288437B
TWI288437B TW094147605A TW94147605A TWI288437B TW I288437 B TWI288437 B TW I288437B TW 094147605 A TW094147605 A TW 094147605A TW 94147605 A TW94147605 A TW 94147605A TW I288437 B TWI288437 B TW I288437B
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Taiwan
Prior art keywords
layer
critical dimension
trench
opening
amorphous
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Application number
TW094147605A
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English (en)
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TW200725713A (en
Inventor
Jar-Ming Ho
Shian-Jyh Lin
Yu-Pi Lee
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Nanya Technology Corp
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Priority to TW094147605A priority Critical patent/TWI288437B/zh
Priority to US11/456,207 priority patent/US20070155179A1/en
Publication of TW200725713A publication Critical patent/TW200725713A/zh
Application granted granted Critical
Publication of TWI288437B publication Critical patent/TWI288437B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench

Description

-1288437 九、發明說明： 【發明所屬之技術領域】 化非晶梦 本發明係與半導體製程有關，特別是有關於—種 硬遮罩製作較小關鍵尺寸溝渠的方法。 【先前技術】 由於元件設計的尺寸讀料，伴_電晶體_通道長产 •㈣如咖1 _h)的縮短所引發的短通道效應(short channel"又 effect)已成為半賴元件進—步提昇其積集度崎礙。過去雖已有 人提出-些方法，來避免短通道效應的發生，例如，減少閑極氧 化層的厚度或疋增加摻雜濃度等L這些方法卻可能同時造 成兀件可靠度的下降或是資料傳送速度變慢制題， 際應用在製程上。 口、 為解決這些問題，目前已發展出一種所謂的凹入式閘極 (recessed-gate)的MOS電晶體元件設計，藉以提昇如動態隨機存取 記憶體(Dynamic Random Access Memory ,簡稱為 DRAM)等積體 電路積集度的作法。相較於傳統水平置放式MOS電晶體的源極、 閘極與汲極，所謂的凹入式閘極MOS電晶體係將閘極與汲極、源 極製作於預先蝕刻在半導體基底中的閘極溝渠(gatetrench)中，並 且將閘極通道區域設置在閘極溝渠的底部，俾形成一凹入式通道 (recessed-channel)，藉此降低MOS電晶體的橫向面積，以提昇半 導體元件的積集度。 5 上288437 :’别噠作凹人相極(⑽essed_gate)Mos電晶體的方法 仍有諸多缺點，猷待進-步的改善與改進。舉例來說，凹入 極MOS電晶體的間極溝渠係利用乾敍刻製程形成在半導體基底f 中，而形成間極溝渠的乾_製程並無法確保每個間極溝準的深 海都完全可能造成每個電晶體的通道的長短並不一 致’並產生電晶體70件其臨界電塵(thresh〇Idv〇lta㈣之控制問題。 此外，P遺著閘極溝渠的縮小，電晶體通道的長度也逐漸不足， 如此一來，更可能導致短通道效應。 再者，g閘極溝渠的關鍵尺寸縮小至微米以下之尺寸時， 閘極溝渠的大小通常不到1F。若湘傳統的微影製絲製作這麼 小的閘極溝渠，則會遭遇到所謂的「線緣粗糙(Line Edge Roughness ’簡稱為LER)」效應以及輪廓控制上的問題 。由此可 知，要製作出具有高可靠度之凹入式閘極M〇s電晶體元件，首先 就必須先精確地控制閘極溝渠的尺寸及輪廓。 【發明内容】 本發明之主要目的即在提供一種利用氧化非晶矽硬遮罩製作 較小關鍵尺寸溝渠的方法，以解決上述習知技藝之問題。 根據本發明之較佳實施例，本發明提供一種以氧化非晶矽硬遮 •1288437 單製作較小關鍵尺寸溝渠的方法，包含有以下之步驟： 提供一半導體基底； 於該半導體基底上形成一氮化矽薄膜； 於該氮化矽薄膜上形成一非晶矽層； 於該非晶梦層上形成一光阻層； 進行一微影製程，於該光阻層中形成一第一開口，其中該第一 開口具有一顯影後關鍵尺寸； • 進行一第一乾蝕刻製程，利用該光阻層做為一蝕刻硬遮罩，經 由該第一開口蝕刻該非晶矽層，並停止於該氮化矽薄膜上，以於 該非晶矽層中形成一第二開口； 進行一氧化製程，將該非晶矽層全部氧化，以形成一矽氧遮罩 層’且該第二開口轉變成具有較小關鍵尺寸的第三開口；以及 進行第二乾餘刻製程，利用該矽氧遮罩層做為一蝕刻硬遮罩， 輕由該第三開口蝕刻該氮化矽層以及該半導體基底，以於該半導 鲁 體基底中形成一溝渠。 簡言之’本發明係提供一種以氧化非晶矽硬遮罩製作較小關鍵 尺寸溝渠的方法’利用非晶矽氧化成矽氧遮罩層後體積膨脹之特 性，可以縮小糊在轉體基底巾的溝__尺寸。本發明方 法不但可以應用在溝渠式動態隨機存⑽己憶體中用來製造凹入式 閘極電晶體，柯以朗在其它轉體製程步驟巾，例如，接觸 洞的製作。 7 1288437 為了使貴審查委員能更進一步了解本發明之特徵及技術内 容，請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與辅助說明用，並非用來對本發明加以限制者。 【實施方式】 請參閱第1圖至第4圖，其繪示的是本發明較佳實施例利用氧 化非晶矽硬遮罩製作較小關鍵尺寸溝渠的方法之剖面示意圖。如 φ 第1圖所示，首先，提供半導體基底1〇，例如矽基底。然後，依 序在半導體基底10上形成一氮化石夕(siliconnitride)襯塾薄膜12、 一非晶矽(amorphoussilicon)層14以及一底部抗反射(Bottom Anti_Reflecti〇n Coating，簡稱為 BARC)層 16。底部抗反射層 16 可以是氮氧化石夕(silicon oxy-nitride)層，但不限於此。 其中，根據本發明之較佳實施例，氮化矽襯墊薄膜12的厚度 車义佳介於30埃至100埃之間，而非晶石夕層14的厚度較佳介於1〇 _ 埃至50埃之間，但不限於此。 接著，進行一微影製程，在底部抗反射層16上形成一經圖案 化的光阻層18，其包含有複數個開口 2〇，暴露出部分的BARC層 16。開口 20 具有-顯影後關鍵尺寸(After-Devd〇pment_Inspecti〇n Critical Dimension，簡稱為 ADICD)1〇2。 本發明之優點在於該光阻層18之開口圖案僅要轉移到非晶矽 -1288437 層14中，而並不是一次直接轉移到下方的半導體基底1〇中。由 於非晶矽層14的厚度並不厚，故光阻層18的厚度也可以較習知 技藝減少或薄化，如此-來，即可以提昇此微影製程的曝光精碟 度，也可避免習知技藝中所謂的「線緣粗糙(LER)」效應以及溝渠 輪廓控制上的問題。 、接著’如第2圖所示’進行—乾_製程，糊光阻層18做 φ為—_硬遮罩，將光阻層18中_口2〇圖案轉移至非晶石夕層 14中’於非晶石夕層14中形成開口 22。隨後，去除光阻層18以及 底部抗反射層16。開口 22具有-_後關鍵尺寸 (After-Etch-Inspection Critical , AEICD)104 〇 # 據本發明之較佳實施例，蚀刻後關鍵尺寸_ c聊4約等於顯影 後關鍵尺寸(ADICD)102。 如第3圖所示，接著進行-氧化製程，將經過圖案化的非晶石夕 層14全部氧化成二氧化石夕，形成石夕氧遮罩層μ。 第3圖中的虛線部分所代表的就是氧化前的非晶石夕層μ位置 與大小’在經過氧化之後，由於非晶矽轰 乳化成一乳化石夕體積膨脹， 成開口 22縮小成開卩24 ’其中開口 24具有—小於關鍵尺 寸W4的關鍵尺寸1〇6。 在進行前叙氧赠崎，祕铸縣底丨㈣表面上仍覆 -1288437 蓋著氮化石夕襯墊薄臈12， 因此其並不會被氧化。 、第圖所7F接著進行一乾韻刻製程，利用石夕氧遮罩層15 =為-敍刻硬遮罩，餘刻未被石夕氧遮罩層15所覆蓋之氮化石夕觀墊 〉膜12以及轉縣底1G，形麟渠26，如此即完成本發明且 較小關鍵尺寸之溝渠的製作。 【圖式簡單說明】 第1圖至第4圖繪示的是本發明較佳實施例利用氣化 遮罩製作較小關鍵尺寸溝渠的方法之剖面示意圖。 日日
【主要元件符號說明】 10 半導體基底 14 非晶發層 16 底部抗反射層 20 開口 24 開口 102顯影後關鍵尺寸 106 關鍵尺寸 12 氮化矽襯墊薄膜 15 矽氧遮罩層 18 光阻層 22 開口 26 溝渠 104 蝕刻後關鍵尺寸

Claims (1)

1288437 5. 如申請專利範圍第1項所述之以氧化非晶矽硬遮罩製作一較小 .關鍵尺寸圖案的方法，其中該非晶矽層的厚度介於10埃至50埃 • 之間。 6. 如申請專利範圍第1項所述之以氧化非晶矽硬遮罩製作一較小 關鍵尺寸圖案的方法，其中該第二關鍵尺小於該第一關鍵尺寸。 十一、圖式：
12
TW094147605A 2005-12-30 2005-12-30 Method to define a pattern having shrunk critical dimension TWI288437B (en)

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TW094147605A TWI288437B (en) 2005-12-30 2005-12-30 Method to define a pattern having shrunk critical dimension
US11/456,207 US20070155179A1 (en) 2005-12-30 2006-07-09 Method to define a pattern having shrunk critical dimension

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TWI288437B true TWI288437B (en) 2007-10-11

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090004868A1 (en) * 2007-06-29 2009-01-01 Doyle Brian S Amorphous silicon oxidation patterning
US9847302B2 (en) * 2013-08-23 2017-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer surface conditioning for stability in fab environment
CN106601610A (zh) * 2015-10-14 2017-04-26 中国科学院微电子研究所 一种形成小间距鳍体的方法
US10020199B1 (en) * 2017-05-15 2018-07-10 International Business Machines Corporation Porous tin oxide films

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KR0158904B1 (ko) * 1994-12-02 1999-02-01 김주용 콘택마스크
US5872052A (en) * 1996-02-12 1999-02-16 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
KR100280106B1 (ko) * 1998-04-16 2001-03-02 윤종용 트렌치 격리 형성 방법
US6319821B1 (en) * 2000-04-24 2001-11-20 Taiwan Semiconductor Manufacturing Company Dual damascene approach for small geometry dimension
US6475867B1 (en) * 2001-04-02 2002-11-05 Advanced Micro Devices, Inc. Method of forming integrated circuit features by oxidation of titanium hard mask
US20030017710A1 (en) * 2001-07-19 2003-01-23 Chartered Semiconductor Manufacturing Ltd. Method to improve latchup by forming selective sloped staircase STI structure to use in the I/0 or latchup sensitive area

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