TWI285416B - Package structure of bipolar transient voltage suppressor - Google Patents

Abstract

A novel package structure of bipolar transient voltage suppressor (TVS) is proposed. The first embodiment is a series package structure. A first TVS chip, two rectifying diode chips in parallel and a second TVS chip of opposite polarity to the first TVS chip are bonded in cascaded manner between a positive lead frame and a negative lead frame. The second embodiment is a parallel package structure. A first TVS chip is bonded to a first rectifying diode chip in cascaded and a second TVS chip is bonded to a second rectifying diode chip in cascaded, then these two groups are bonded in parallel with opposite polarity between a positive lead frame and a negative lead frame. These package structures can suppress both positive and negative transient voltage.

Description

1285416 VII. Designated representative map: (1) The representative representative of the case is: ( ). (2) A brief description of the symbol of the representative figure:

8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention:

IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to a surge voltage suppressor technique. In particular, the present invention is related to a package structure for a bipolar surge voltage suppressor. [Prior Art] Various surges or fansient voltages are often generated on power line circuits. Such surges or transient voltages often cause electronic components to be destroyed. 'The calling subsystem cannot operate, sometimes The formation of catastrophic results, in order to protect electronic immunity, temporary, voltage damage, many previous technologies have proposed solutions. Most of the prior art is a single-edged component, i.e., the spur suppression is generally used to protect a positive or negative spur, as shown in Fig. 1 (1). In the power: circuit 1〇4, a surge suppressor 1〇6 is connected to suppress the dog wave. This prior art is found in U.S. Patent No. 4/6〇〇96〇, awarded to Clarke, a four-terminal surge is connected in series to two powers, two bipolar protections, and two opposite polarity surge suppressors are required. Connected between the signal circuits. This can be seen in Figure i (8). In the signal 112 and the electronic power: a surge suppressor 116 for protection and a surge suppressor for negative polarity protection are required. In this way, two surge suppressors need to be arranged on the peach board or integrated circuit. A prior art can be found in the United States 063, licensed from (嶋) and others, this patent (Metal 〇 Xide Semiconductor * MOS) GBT ^ i ^ θ ^ (InSUlBting Gate Bip〇lar T^nsistor, voltage Surge or side pressure. However, this component can only be used in the low-voltage energy package (4) ^ crying the shortcomings of the prior art, and propose a bipolar surge voltage suppression for the package structure 'to solve the problem.' [Summary of the invention] The purpose of the Zhuangli Benedict is to provide a bipolar surge suppressor that is capable of suppressing the positive and negative voltages of the '1285416 state' and reducing the circuit or circuit. A further object of the present invention is to provide a package structure of a bipolar surge voltage suppressor, which can be connected in series with a surge voltage & Reducing the capacitance of the suppressor. To achieve the above and other objects, the first aspect of the present invention teaches a tandem package structure of a dual white dog wave suppressor comprising two surge voltage suppressor (tvs) wafers and a rectification 'One pole Tablets, packaged in a positive electrode base pin (Frame)

The TVS surface has a positive electrode and the reverse side has a negative electrode; the second TVS wafer has a PN junction, a positive electrode on the front side, a negative electrode on the reverse side, a gold first tvs wafer, a back stack arrangement, and a TVS wafer. And a second TVS wafer. The electrode faces, the third rectifying one-pole wafer is soldered (die-b〇nd) between the first tvs wafer and the second tvs wafer, and the positive electrode is connected to the first TVS wafer two. One pole wafer is side by side, and is also soldered to the first TVS wafer and the first wafer, and the positive electrode is soldered to the negative electrode of the second TVS wafer and the negative electrode

ίί2tUh negative electrode; a positive pin base (lead f dirty), if θ, ΐ TVS 之 positive electrode; a negative pin pedestal, welded to the second day electrode, an epoxy tree An epoxy outer casing sealing the first TVS mechanical i tin sheet and the two health flow diode wafers for construction, teaching a parallel package structure of a two-way surge suppressor - a dog wave voltage The suppressor (Tvs) is packaged on the positive pin base (leari仏, 纽纽-位 basket day and month: Qiao i 2: PN junction, front has a positive electrode, reverse has - TV;刍;:: 7-pole wafer is die-bonded (die_bond) to the TVS day, the negative electrode is soldered to the first piece, has a PN junction, positive two = negative electrode of the diaphragm, and a TVS crystal second The rectifier diode has a negative electrode on the opposite side and the opposite side; the anode is connected to the second TVS wafer, the negative electrode is welded 1285416 to the negative electrode of the second TVS wafer, and the first TVS wafer is stacked and soldered. a first integral 'diode wafer and a second soldered second TVS wafer and a second rectified diode wafer are packaged on the positive electrode Between the pin base and the negative pin base, the first tvs chip, the positive electrode of the electrode and the second rectifying diode chip are soldered to the positive pin base and the positive electrode of the first rectifying diode chip and the first a positive electrode of the two TVS wafer is soldered to the negative t亟 pin base; an epoxy vinegar outer casing seals the first TVS wafer, the second TVS wafer and the two rectifying diode chips The above and other objects and advantages of the present invention will be more fully understood from the following description of the drawings and the description of the preferred <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The figure shows a schematic diagram of a conventional surge suppressor (TVS) wafer 200. In the germanium substrate 2〇4, a pn junction or NP junction 206 is formed by diffusion or ion implantation to form a PN junction, which is mixed. The concentration is collapsed by the surge suppressor, and a U-shaped trench (u-gr〇〇ve) 208 is formed to increase the reverse bias and collapse resistance. The positive electrode 21〇 and the negative electrode are formed on the front side and the back side, respectively. 212. ^ Referring to Figure 3, Figure 3 shows the invention in accordance with the present invention In one embodiment, the surge suppressor is connected in series with the package structure 300. The first TVS wafer 304 and the second TVS wafer 314 are arranged in a back-to-back stack. It is assumed that both wafers are PN junctions 307 and 313. The first TVS wafer 304 The second TVS wafer 314 is used to suppress the forward surge. Between the TVS wafers 304 and 314, the two rectifying diodes 308 and 310 are die-bonded side by side. The opposite polarity is soldered to the solder bumps 306 and 312 of the TVS wafers 304 and 314. A positive lead frame 302 is soldered to the positive solder bump 303 of the first TVS wafer 304, and a negative pin base 316 is soldered to the positive solder bump 315 of the second TVS wafer 314. After dare, the entire package is made of epoxy tree | (print (10)^) gig seal for mechanical and electrical protection.

Refer to Figure 4. Figure 4 shows a series connection of TVS 1285416 in accordance with an embodiment of the present invention. Figure 4 (A) shows the current at the time of the occurrence of a negative transient voltage surge. After being connected to a circuit (not shown), there is a negative transient state in the input county, and the dog wave 402 occurs. The first TVS is reverse biased until its breakdown voltage is thin and reverse biased. However, it does not collapse and is not turned on; the rectifying diode is turned on in the forward bias, and the rectifying diode 31 is used to reduce the capacitance of the suppressor, because the reverse bias capacitor and rectification of the first TVS 304 Two poles ^ 3i 〇 ^ forward bias capacitors in series. The second top 314 is also turned on for forward biasing. The temporary sad voltage surge 402 is suppressed by the current 404 passing through the first TVS class, the rectifying diode 3 TVS 314. Brother one

Refer to Figure 4 (B). Figure 4 (8) shows the current in the forward transient voltage spur. ^ After the TVS is connected to the circuit (not shown), if two positive transient voltage surges occur on the input side, the second TVS 314 is reverse biased to its breakdown voltage, and the rectifying diode 310 is also Reverse bias, but not collapsed and not turned on; rectifier diode 3G8 is forward biased and turned on, rectifying diode system is used to reduce the capacitance of suppressor, 300, due to the reverse bias of the second TVS 314 The capacitor is connected in series with the forward bias capacitor of the current diode. The first TVS Xie is also turned on for forward bias. Transient voltage surge 406 is suppressed by current 408 through second TVS 314, rectifying diode 308 and first TVS 304. Referring to Figure 5, Figure 5 shows a surge suppressor serial package structure 5 using two bipolar surge suppression wafers in accordance with one embodiment of the present invention. The first bipolar TVS wafer 504 and the second bipolar TVS wafer 514 are arranged in a back-to-back stack. Assume that both wafers are PN junctions 505, 507 and 511, 513. The junction 505 of the first bipolar TVS wafer 504 and the junction 511 of the second bipolar TVS wafer 514 are used to suppress the negative surge and the junction 5〇7 and the second bipolar TVS of the first bipolar TVS wafer 504. The junction 513 of the wafer 514 is used to suppress the forward glitch. Between the bipolar TVS wafers 504 and 514, the two rectifying diodes 5〇8 and 51〇 are die-bonded but opposite in polarity soldered to the bipolar TVS wafers 5〇4 and 514. Solder bumps 506 and 512. A positive lead tab 502 is soldered to the positive solder bump 503 of the first bipolar TVS wafer 504

1285416 514 ^ For mechanical and electrical protection.玎 糸 ep ep 518 518 518 518 518 518 518 518 518 518 518 518 518 518 518 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作;ΡΝ^φ 511 磬,,* - pole# Rin is on the 'positive pole 510, which is forward biased and turned on, body 510 is used to reduce the capacitance of the suppressor _, because of bipolar TVS, ^ The reverse bias capacitors of the lands 505 and 511 are connected in series with the 二 capacitor of the rectifier diode 51. Transient voltage surge 602 is suppressed by current 604 through first bipolar TVS diode 510 and second bipolar TVS 514. ^ 6 figure (β). Figure 6 (B) shows the current when a negative transient voltage spur occurs. After the TVS is connected to the circuit (not shown), if a forward transient voltage surge 606 occurs at the input end, the first bipolar TVS5〇42PN junction 5 stomach 7 and the second bipolar TVS 514 The PN junction 513 is reverse biased to its breakdown voltage 'PN, and the faces 505, 511 are turned on in a forward bias. The rectifying diode 51 is also in the reverse internal bias, but does not collapse and is not turned on; the rectifying diode 5 〇 8 is forward biased and turned on, and the rectifying diode 508 is used to reduce the suppressor 5 〇〇 The capacitance of the PN junctions 507, 513 of the first bipolar TVS 504, 514 is in series with the forward bias capacitance of the rectifier diode 508. Transient voltage surge 606 is suppressed by current 608 through second bipolar TVS 514, rectifying diode 508, and first bipolar TVS 514. Referring to Figure 7, Figure 7 shows a surge suppressor parallel package structure 5 using two bipolar surge suppression wafers in accordance with one embodiment of the present invention. Assume that both wafers are PN junctions. The negative solder bump 706 of the first TVS wafer 704 is soldered to the negative electrode of the first rectifying diode 708 by wafer soldering, and the 1285416 positive electrode of the first rectifying diode 708 is soldered to the negative pin base 7Q2. The first is soldered to the second of the second rectifying diode Zhao 718: Mou 2: No. 08 is soldered to the negative pin base 702. The second and second traits are extremely fine tin bumps 716 welded to the negative pin base S 702. Autumn U pole ^ base = 22, connected to the negative electrode 720 of the positive TV bump 703 18 of the first TVS crystal. Finally, the entire package is sealed with epoxy 酉 704 for mechanical and electrical protection. Rolling

# ΊΓνίΐϋί ° 8 shows a parallel bipolar current in accordance with an embodiment of the present invention. Figure 8 (Α) shows the PN to the first bipolar TVS7G4 at the input end if there is a negative $way (not shown) when the transient voltage surge occurs. The junction is reversed, "Zero 2: the rectifying diode 708 is in forward bias and is turned on, and is in reverse bias, but does not collapse and does not conduct; the rectifying diode 708 reduces the capacitance of the suppressor, Because the bipolar top grab bias capacitor is connected in series with the forward bias capacitor of the rectifier diode. Temporary === is passed through the first bipolar Qing 4 and the rectified poles. B) Figure 8 (B) shows that the forward transient voltage surge occurs after the TVS is connected to the circuit (not shown). If there is a „% voltage surge 826 at the input, the second bipolar TVS71 〇^pN junction is pressed to its bet, rectified diode Ή8 is tightly biased and turned on, = one pole 708 is also in reverse bias, but does not collapse without conduction; rectified two-pole 8 To reduce the capacitance of the suppressor 700, the PN reverse bias capacitance of the bipolar TVS 710 is in series with the forward bias capacitance of the rectifier diode 718. The sad voltage surge 826 is suppressed by the current 830 passing through the second bipolar TVS 710 and the rectifying diode 718. The detailed description of the preferred embodiments above is intended to provide a more detailed description of the features of the present invention and is not intended to limit the scope of the invention. On the contrary, the purpose is to cover various changes and phases.

Claims (1)

1285416 X. Patent application scope: 1. A two-way surge suppressor serial package structure, comprising two voltage suppression suppressor (TVS) chips and two rectifying diode chips, packaged on a positive pin base (lead frame) And the negative pin base between the at least: the brother-TVS chip has a PN junction and a negative electrode on the surface; the front has a positive electrode, a second TVS wafer, has a PN junction, and has a front surface The positive and the surface have a negative electrode arranged in a back-to-back arrangement with the first TVS wafer, the negative electrode of the first TVS chip and the second TVS wafer face each other; aa the first rectifier diode chip is soldered by the die (die-b〇nd) Between the first tvs wafer and the second TVS wafer, a positive electrode is soldered to the first Tvs wafer and a negative electrode is soldered to the negative electrode of the second TVS wafer; and a second rectifying diode wafer is first The rectifier diode chips are side by side, the wafer is soldered between the first TVS wafer and the second TVS wafer, and the negative electrode of the TVS wafer is soldered to the negative electrode of the first tvs wafer; the positive electrode pin base (lead fram) e) soldering to a negative pin base of the second tvs wafer, soldering to the positive electrode of the second Tvs wafer; an epoxy resin (printed OXy) outer casing, the first Tvs wafer, the = wafer, and the second flow The diode chip is sealed inside for mechanical and mechanical protection. 2. The serially packaged structure TVS wafer and the second TVS wafer as claimed in claim 1 are PN junction wafers. 3. The tandem packaged TVS wafer and the second TVS wafer are the Np junction wafer as claimed in the scope of claim j. In the first, wherein the dream is a tandem package structure according to the scope of the patent application, the TVS wafer is a PN junction wafer and the second TO wafer is an Np junction wafer. TVS曰Ltrt asks for a series of thief-packed structures in the patent series, in which the first TVS wafer is a bi-polari(R) TVS chip on the first day, and 13 1285416 has a PN connection on both the front and the back. surface. - 6. According to the tandem sealing structure of claim 1, the first TVS wafer and the second TVS wafer are bipolar (bi-directionanTVS crystal - both have an NP junction on both the front side and the back side). Aa * 7 · In the series connection package structure of claim 1, the first rectifying diode chip and the second rectifying diode chip in JL are spliced surface crystals/pieces. She surrounds the package structure of the first item, in which the first rectifying diode chip and the second rectifying diode chip are Νρ junction crystal/chip. β 9· a parallel package of bidirectional surge suppressors The structure comprises two surge voltage suppressor (TVS) chips and two rectifying diode chips, and is packaged between the positive lead frame and the negative pin base, and comprises at least: a first TVS chip having a PN junction having a positive electrode on the front side and a negative electrode on the reverse side; the first rectifying diode wafer is soldered to the first TVS wafer by wafer soldering on the first TVS wafer a negative electrode; a first TVS wafer having a PN junction and a front surface a positive electrode and a negative electrode on the reverse side; a second rectifying diode wafer, which is also soldered to the second TVS wafer, and a negative electrode is soldered to the negative electrode of the second TVS wafer; ##Stacked first TVS wafer and The first rectifying diode chip is stacked in parallel with the stacked second TVS chip and the second rectifying diode chip between the positive pin base and the negative pin base, and the positive electrode and the second rectifying electrode of the first TVS chip a positive electrode of the polar body wafer is soldered to the positive pin base, and a positive electrode of the first rectifying diode chip and a positive electrode of the second TVS chip are soldered to the negative pin base; an epoxy resin outer casing; The first TVS wafer, the second TVS wafer, and the two rectifying diode chips are sealed for mechanical and electrical protection. 10 · The parallel package structure of claim 9 The first TVS wafer and the second TVS wafer are pn junction wafers. 1285416 11. The parallel package structure of claim 9, wherein the first TVS wafer and the second TVS wafer are NP junction wafers. 12. The parallel package structure of claim 9 wherein the first TVS wafer is a PN junction wafer and the second TVS wafer is an NP junction wafer. 13. The parallel package structure of claim 9 wherein The first rectifying diode chip and the second rectifying diode chip are PN junction wafers. 14. The parallel package structure of claim 9, wherein the first rectifying diode chip and the second rectifying The diode wafer is a PN junction wafer. 15