CN210956661U

CN210956661U - Stacked chip structure

Info

Publication number: CN210956661U
Application number: CN201922377520.5U
Authority: CN
Inventors: 叶锋; 杨小军; 黄卫国; 虞麟
Original assignee: Littelfuse Semiconductor (Wuxi) Co Ltd
Current assignee: Littelfuse Semiconductor (Wuxi) Co Ltd
Priority date: 2019-12-25
Filing date: 2019-12-25
Publication date: 2020-07-07
Anticipated expiration: 2029-12-25

Abstract

A stacked chip structure is provided. The stacked chip structure includes: a lead frame; a first chip disposed on the lead frame in a vertical direction; a first solder material layer disposed between the lead frame and the first chip in the vertical direction for fixing and electrically connecting the first chip to the lead frame; a second chip disposed on the first chip in the vertical direction; a second solder material layer disposed between the first chip and the second chip along the vertical direction for fixing and electrically connecting the second chip to the first chip; the copper clip is arranged on the second chip along the vertical direction; and a third solder material layer disposed between the second chip and the copper clip along the vertical direction for fixing and electrically connecting the second chip to the copper clip, wherein only the second solder material layer is disposed between the first chip and the second chip along the vertical direction.

Description

Stacked chip structure

Technical Field

The embodiment of the utility model provides a relate to semiconductor device technical field, especially relate to a pile up chip structure.

Background

With the rapid development of semiconductor integrated circuits, it is a future development trend of integrated circuits to meet the requirements of customized functions. In order to achieve multi-functional output, the integrated interconnection of multiple types of chips is required, and meanwhile, the rigid requirements of small size and light weight of integrated circuits are gradually increased. In response to the above application requirements, stacked chip structures including multiple types of chips are gradually developed.

In the current stacked chip structure, it is generally necessary to provide a solder pad (solder wafer) between two stacked chips, to which the two chips are respectively soldered, in order to realize stacking of a plurality of chips. However, since the bonding pads are generally light, thin, and flexible, two chips can be bonded to the bonding pads, respectively, only by manual mounting. As a result, the current stacked chip structure cannot be applied to automated processing equipment, and is limited to manual processing, and the porosity ratio in the bonding layer between the two chips and the bonding pad is large, typically up to 15-30%, which may cause bonding failure.

Therefore, the existing stacked chip structure has certain defects, and further improvement is needed.

SUMMERY OF THE UTILITY MODEL

In order to solve at least one aspect of the above problems, the present invention provides a stacked chip structure.

In one aspect, there is provided a stacked chip structure, including:

a lead frame;

a first chip disposed on the lead frame in a vertical direction;

a first solder material layer disposed between the lead frame and the first chip in the vertical direction for fixing and electrically connecting the first chip to the lead frame;

a second chip disposed on the first chip in the vertical direction;

a second solder material layer disposed between the first chip and the second chip along the vertical direction for fixing and electrically connecting the second chip to the first chip;

the copper clip is arranged on the second chip along the vertical direction; and

a third solder material layer disposed between the second chip and the copper clip along the vertical direction for securing and electrically connecting the second chip to the copper clip,

wherein only the second solder material layer is provided between the first chip and the second chip in the vertical direction.

According to some exemplary embodiments, each of the first, second and third welding material layers has a porosity of less than 10%.

According to some exemplary embodiments, each of the first, second and third welding material layers has a porosity of less than 0.6%.

According to some exemplary embodiments, a distance between the first chip and the second chip in the vertical direction is less than or equal to a distance between the lead frame and the first chip in the vertical direction.

According to some exemplary embodiments, a distance between the first chip and the second chip along the vertical direction is less than or equal to a distance between the second chip and the copper clip along the vertical direction.

According to some exemplary embodiments, a projection of the second chip in the vertical direction overlaps with a projection of the first chip in the vertical direction.

According to some exemplary embodiments, each of the first, second and third soldering material layers includes a solder paste.

According to some exemplary embodiments, the copper clip is electrically connected to the lead frame by a lead.

According to some example embodiments, the first chip and the second chip are both transient voltage suppression semiconductor chips.

According to the utility model discloses it has less overall thickness to pile up chip structure to can be applicable to automatic processing equipment.

Drawings

Other objects and advantages of the present invention will become apparent from the following description of the invention, which is made with reference to the accompanying drawings, and can help to provide a thorough understanding of the present invention.

Fig. 1 is a side cross-sectional view of a stacked chip structure according to various embodiments of the present invention; and

fig. 2 is a schematic plan view of a solder material layer of a stacked chip structure according to an embodiment of the present invention.

It is noted that in the accompanying drawings used to describe embodiments of the invention, the dimensions of layers, structures or regions may be exaggerated or reduced for clarity, i.e., the drawings are not drawn to scale.

Detailed Description

The technical solution of the present invention is further specifically described below by way of examples and with reference to the accompanying drawings. In the specification, the same or similar reference numerals denote the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the general technical concept of the present invention and should not be construed as limiting the present invention.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details.

It should be noted that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below could be termed a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present invention.

It should also be noted that the terms "vertical direction," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the embodiments of the present invention and for simplicity in description, and do not indicate or imply that the device or element so indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention. Moreover, it will be understood that the orientation or positional relationship indicated by these terms may be changed accordingly when the orientation of the drawings is changed, for example, if the device in the drawings is turned upside down, elements described as "under" or "beneath" other elements or features will be oriented "on" or "above" the other elements or features.

Fig. 1 is a side cross-sectional view of a stacked chip structure 100 according to various embodiments of the present invention. The stacked chip structure 100 may include: a lead frame 1; a first chip 2 disposed on the lead frame 1 in a vertical direction (up-down direction in fig. 1); a first solder material layer 3 provided between the lead frame 1 and the first chip 2 in the vertical direction for fixing and electrically connecting the first chip 2 to the lead frame 1; a second chip 4 disposed on the first chip 2 in the vertical direction; a second solder material layer 5 disposed between the first chip 2 and the second chip 4 in the vertical direction for fixing and electrically connecting the second chip 4 to the first chip 2; a copper clip 6 disposed on the second chip 4 in the vertical direction; and a third solder material layer 7 disposed between the second chip 4 and the copper clip 6 in the vertical direction for fixing and electrically connecting the second chip 4 to the copper clip 6.

Referring to fig. 1, in an embodiment of the present invention, only the second solder material layer 5 is disposed between the first chip 2 and the second chip 4 along the vertical direction. That is, no other structure or layer, for example, no soldering tab (solder wafer), is provided between the first chip 2 and the second chip 4 in the vertical direction except for the second soldering material layer 5. With the help of the utility model discloses a pile up chip structure, owing to need not to set up the soldering lug for the welding, so, pile up chip structure and can be applicable to automatic processing equipment, promptly, can use full-automatic processing equipment to produce pile up chip structure. In particular, the soldering process may be performed in a vacuum oven (vacuum oven), thereby enabling a reduction of the porosity in the individual soldering material layers.

Fig. 2 is a schematic plan view of a solder material layer of a stacked chip structure according to an embodiment of the present invention. Note that the solder material layer shown in fig. 2 may be any one of the first solder material layer 3, the second solder material layer 5, and the third solder material layer 7. As shown in fig. 2, the welding material layer may include a welding material M and air holes or bubbles V (i.e., solder void) distributed in the welding material M. In the present context, the expression "porosity" is used to indicate the volume percentage of the porosity V to the solder material M, which is used to indicate the degree of densification of the solder material layer. For example, each of the first, second, and third soldering material layers 3, 5, and 7 may include a solder paste.

In the embodiment of the present invention, since the welding process can be performed in the vacuum furnace, the porosity of each of the first welding material layer 3, the second welding material layer 5, and the third welding material layer 7 can be effectively reduced. The porosity of each of the first, second and third solder material layers 3, 5, 7 may be up to 10% or less, even up to 0.6% or less, as determined by experimental analysis. Therefore, the welding performance of each welding material layer can be effectively improved, and the reliability of the stacked chip structure is improved.

Referring to fig. 1, a projection of the second chip 4 along the vertical direction overlaps a projection of the first chip 2 along the vertical direction, for example, the projection of the second chip 4 along the vertical direction may coincide with the projection of the first chip 2 along the vertical direction. Optionally, a projection of the second chip 4 along the vertical direction overlaps with a projection of the copper clip 6 along the vertical direction. In this way, a stacked structure of a plurality of chips is realized.

With continued reference to fig. 1, the distance between the lead frame 1 and the first chip 2 in the vertical direction is denoted as d1, the distance between the first chip 2 and the second chip 4 in the vertical direction is denoted as d2, and the distance between the second chip 4 and the copper clip 6 in the vertical direction is denoted as d 3. Since only the second solder material layer 5 is provided between the first chip 2 and the second chip 4 in the vertical direction without providing a solder tab (solderwafer), d2 may be set small, for example, d2 may be less than or equal to d1, or d2 may be less than or equal to d 3. In one exemplary embodiment, d1 ═ d2 ═ d 3. It can be seen that, in the embodiment of the present invention, since it is not necessary to provide a soldering tab (solder wafer), it is advantageous to reduce the overall thickness of the stacked chip structure.

For example, the first chip 2 and the second chip 4 may both be transient voltage suppression semiconductor chips, belonging to a power chip. The lower surface of the first chip 2 is electrically connected to the lead frame 1, and the first solder material layer 3 electrically connects the upper surface of the first chip 2 to the lower surface of the second chip 4.

In this document, the expression "transient voltage suppression semiconductor chip" may refer to a transient voltage suppression tube, which is an overvoltage protection device having a bidirectional voltage stabilization characteristic and a bidirectional negative resistance characteristic, similar to a varistor. It is used in various AC and DC power supply circuits to suppress instantaneous overvoltage. When surge pulse voltage appears in the protected circuit instantly, the two-way breakdown diode can break down Zener rapidly, and change from a high resistance state to a low resistance state to shunt and clamp the surge voltage, so that each element in the protection circuit is not damaged by the instant surge pulse voltage.

For example, the copper clip 6 may be electrically connected to the lead frame 1 by leads 8. For example, the lead 8 may be fixed and electrically connected to the lead frame 1 by solder paste. In this way, the upper mesa of the second chip 4 can be electrically connected to the copper clip 6 and thus to the lead frame 1 via the leads 8. For example, the copper Clip 6 and the lead 8 may be formed as a unitary structure, which may be referred to as a Clip (jumper).

For example, the lead frame 1 may be an integral frame made of conductive materials such as an alloy copper material, a pure copper material, an aluminum-plated copper material, a zinc-plated copper material, and a nickel-iron alloy material

It should be noted that, in the above embodiment, the stacked chip structure according to the embodiment of the present invention is described in detail by taking 2 chips as an example, however, the stacked chip structure improved by the embodiment of the present invention may also include more than 2 chips, in this case, only the welding material layer is provided between every two adjacent chips, and the welding pad for welding is not required to be provided.

It should be further noted that the chip may also have a flip chip structure, and the embodiments of the present disclosure are not particularly limited.

Although a few embodiments in accordance with the present general inventive concept have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A stacked chip structure, comprising:

a lead frame;

a first chip disposed on the lead frame in a vertical direction;

a second chip disposed on the first chip in the vertical direction;

a second solder material layer disposed between the first chip and the second chip along the vertical direction for fixing and electrically connecting the second chip to the first chip:

2. The stacked chip structure of claim 1, wherein each of the first, second, and third solder material layers has a porosity of less than 10%.

3. The stacked chip structure of claim 2, wherein each of the first, second, and third solder material layers has a porosity of less than 0.6%.

4. The stacked chip structure of any one of claims 1-3, wherein a distance between the first chip and the second chip in the vertical direction is less than or equal to a distance between the leadframe and the first chip in the vertical direction.

5. The stacked chip structure of claim 4, wherein a distance between the first chip and the second chip along the vertical direction is less than or equal to a distance between the second chip and the copper clip along the vertical direction.

6. The stacked chip structure of any one of claims 1-3, wherein a projection of said second chip in said vertical direction overlaps a projection of said first chip in said vertical direction.

7. The stacked chip structure of any one of claims 1-3 and 5, wherein each of the first, second and third solder material layers comprises solder paste.

8. The stacked chip structure of any one of claims 1-3 and 5, wherein said copper clip is electrically connected to said leadframe by a lead.

9. The stacked chip structure of any one of claims 1-3 and 5, wherein the first chip and the second chip are both transient voltage suppression semiconductor chips.