TWI280045B - Methods for adjusting the synchronization in digital display application - Google Patents

Abstract

The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. ""Horizontal synchronization vibration"" and ""Remapping"" are the two methods of the present invention.

Description

1280045 V. INSTRUCTIONS (1) " ---- [Technical Field] The present invention relates to a method for improving synchronization in a digital display, in particular, a horizontally synchronized oscillation of an index display and a last horizontal synchronization line = 0 [Prior Art] With the increasing popularity of flat panel displays, image zoom controllers are also increasingly inexpensive, and fully functional to handle different input timings in digital displays. Most scaler wafers use a linear buffer construction instead of a frame buffer construction because the line buffer saves memory and the wafer pin interface, so how to reduce the line buffer and ensure the quality of the zoom is the most important. Question. However, when the relative timing between the input image and the output image is not accurately processed, the smaller line buffer will generate too fast in the first in first out (FIFO, first-in first out) (under) -run) or the risk of being too slow (〇ver —run). Generally, for a given input image, the vertical input valid time (V-ip-Active time) should be equal to the vertical output effective time • V — op—Active time, in order to match the write speed and read speed of the line buffer. . However, the total number of horizontal output points (HS-op-Total-dots) calculated in this way are mostly not integers. In order to adjust HS-op-Total-dots to be an integer, the effective time of the input is not equal to the effective time of rotation. In the prior art, some use larger linear buffers to increase tolerance for FIFOs that are too fast or too slow, or to make advanced

1280045 V. INSTRUCTIONS (2) The first-out output cannot be processed in some input modes. Figure 1 shows that the line buffer is under-run or too slow (over·-r^in_, the daily sequence waveform, where VSi means "vertical sync input" 'riby non-level data start input", VSo means "vertical sync input", HDO means "horizontal data start output". When it is too fast, it is too fast 'when it is too slow' It is the HDE 〇 too deformed into the shadow. And after the output clock cycle and the horizontal sync (Hsync) cycle are fixed, the vertical total output line calculated by f (v_〇PT〇tal_lines) is not an integer. The last score line Some display noise will be formed at the top of the next facet. SUMMARY OF THE INVENTION The main purpose of the present invention is to propose two methods for improving the synchronization problem of a digital display. In a digital display, the vertical timing is divided into four segments: Vertical sync pulse Period (VSync - PulseTime), after the vertical sync pulse period (VSync - BackPorch), the vertical display valid period (V - Display - Active), and • Before the vertical sync pulse period (VSy nc__FrontPorch), during the vertical display validity, use a preset output clock (independent of the input clock) to calculate the ideal horizontal synchronization total dot ( (HSync output total dots, mostly a non-integer), and then Assigning its score points to some other lines. This will change the period of HSync (horizontal sync), sometimes longer and sometimes shorter.

Page 7 1280045 V. Description of invention (3) '~' 1~- But its average period is equal to the ideal HSync period. This method completely aligns the first-in-first-out % order, called "horizontal synchronous oscillation." > A method called "remote of horizontal sync lines". When the calculated vertical total output line (verHcai output total line) is not an integer, the last dot of the last sync line is assigned to the period before the = synchronous sync pulse (VSync - Fr〇) On the line of ntp〇rch), or assigned to the line that does not vertically display the valid period (v - Display - Active), _ easily solves the problem of short/long line. [Embodiment] Why change the synchronization timing? The digital display unit's scaler must support images of different resolutions and images from many different sources, such as ADC and DVI inputs. Images may be in XGA, SXGA, UXGA or other formats, each with a different vertical sync/horizontal sync frequency. Image input (eg ITU-R6 56, ITU-R6〇1, ,, etc.) may have different timing image inputs, such as NTSC, pAL, 〇TV, ,, etc. 'There must be reduced or enlarged to match the display panel Resolution. # Digital display devices, such as LCD panels, have a fixed effective display area (resolution) based on their physical materials, which can accommodate a wide range of vertical sync (VSync) and horizontal sync (HSync) cycles, and can accept a small number of timing changes. . However, if the HSync timing change is too large, for example, greater than 10% of the previous cycle, the display device may generate unnecessary images, such as white dot garbage, shortened/delayed image lines or flicker, etc., so try to maintain

Page 8 1280045 V. Description of the invention (4) The stability of the HSync cycle is very important. • For fine-grained images, the right output refresh rate (V S y n c frequency) is equal to , and the refresh rate is saved, which saves design cost. This is called “frame lock, 疋”. Three examples of implementing a scaler with a buffer are presented below. 1. Implementing a scaler with a frame buffer Some scalers are designed with a frame buffer in which DRAM or attached dram is embedded to avoid timing problems. However, the cost of such a system or wafer is too high.

2 · With a number of some punches, the distance between the dimensions is determined, that is, the ideal frame, so the line/long line) ► This non-picture and the first more lines of SRAM line type buffer implement the scaler scaler Designed with many linear buffers, it has an additional FI F0 warning zone (write index and readout indicator), so it is possible to track the frame lock in several frames without having to be in each picture. Frame lock is performed in the box, and the last score line of each f is accumulated and placed in some other frames. Each output frame has an integer HSync line (no short 'but some frames may have one more line or less). One line. ^The design of the lock will change the distance (time period) between the first write indicator reading indicator in each frame, so a type of buffer warning zone is needed. This solution is used on the wafer. The block 'generally makes the wafer size larger.

1280045 V. INSTRUCTIONS (5) Some of the scaler designs are based on the cost of the wafer. The range of the test is very limited, so there are usually buffers or possible buffer buffer lines or both. , & or short-line / linear buffer too fast / too slow problem When the linear buffer is very short, if it can not maintain the speed, it is easy to produce too fast or too slow problem β write and read "demonstration" The line buffer is too fast and too slow for timing waveforms," VS! does not "vertical sync input", HDE means "water" '''VSo means "vertical sync output", HDE〇; ^, wheel start output". When it is too fast, it is a job. Too fast, too, too slow, then:? Too slow, causing distortion of the image. Then HDE is in the input image. If the line buffer maintains the correct speed, the image will look the same as the input image, as shown in Figure 2. When J is out of the way, the zoomed image will copy some lines, and the helmet will not output the last input line. The output image is a bit like the one shown in Figure 3. When it's too slow, the zoomed image will lose some lines, and the last input line will be copied. The output image looks a bit like the one shown in Figure 4. However, in addition to carefully calculating the round-up HSync cycle, if the HSync cycle is allowed to adjust during the active line (active 1 ine), it is possible to fully match the buffer speed, thus saving wafer cost. In the ideal case ‘If you select a valid image range to scale, say enter a valid image, the following expression must be true: V_ip_Active time = V_〇p^Active time ;

1280045

Or express it in another precise way: V_ip_Active (line#) x HS_ip_Period (time) = v_〇P_Active (line#) x HS_〇p-peri〇d (time); and HS_op-Period (time) -CLK^〇p_Period (time/dot) χ HS_op_Total (dots); therefore HS — 0p — Total (dots) = (V—ip_Active (Une#) x HS_ip—Period (time) / V—〇p—Active (line #)) / CLK_op_period (time/dot); but the calculated HS-〇P-Total (dots) 99% is not an integer, so the fractional part of the parent output line HS_op-Total (dots) will be in the entire output V-ορ Accumulates into a large number of points in an Active period, possibly exceeding a line buffer, causing problems that are too fast or too slow. Therefore, the fractional part of HS-op-Total (dots) is allocated to some other lines to form HSync Vibration. HSync Vibration The present invention is referred to as "HSync Vibration" and is implemented in the following procedure: 鲁让HS-op-Total (dots)_Base = Integer (HS-op-Total) (dots)); and HS_op-Total (dots)-Fract ion =HS-op-Total (dots) - HS-op-Total (dots)-Base; Each time the next output line is displayed, the calculation: HS_op_Total (dots)—Vary : = Fraction (HS—op—Total

Page 11 1280045 V. Invention Description α) (dots)—Vary) + HS_op—Total (dots) —Fraction; If (HS_op_Total (dots)_Vary <1 ), then HS-op-Total in the next output line Dots) = HS—op_Total (dots)—Base; If (HS—op—Total (dots)_Vary >=1), HS_op—Total (dots) = HS—op—Total (dots) in the next output line -Base + 1 ° This allows you to adjust yourself to change. This is shown in Figure 5. HS - op - Total (dots) will increase "1" after three "HS_op - Total (dots) - Base" lines. For some high-speed panels with dual-channel output, the above formula can be slightly modified as follows: Let HS_op—Total (dots)—Base = Integer (HS—op—Total (dots)/2) x 2; and HS_op_Total (dots)_Fraction =(HS—op—Total (dots) - HS—op_Total (dots) _Base) / 2; Each time the next output line is displayed, calculate: • S—op—Total (dots)—Vary : = Fraction (HS — Op —Total (dots)_Vary) + HS—op—Total (dots)—Fraction; If (HS — op—Total (dots)—Vary <1 ), HS_op_Total (dots) in the next output line = HS_op_Total (dots)—Base; If (HS-op-Total (dots)-Vary >=1), HS_op-Total (dots) = HS-op_Total (dots)-Base + in the next output line

Page 12 1280045 V. Invention Description (8) The last horizontal sync line is digested for a frame locked zoom system ' input frame time = output frame time input frame time = V—ip—Total (line#) x Hjp— Total (dots) x Clock—ip—Period (time/dot); output frame time = V—op—Total (line#) x H~op—Total (dots) x Clock—op—Period (time/dot); For a given Clock —op_Period (time/dot) and H~〇p—Total (dots) (or adjusted), calculate V — op — Total (line#) = (V—ip—Total (line# x H—ip—Total (dots) x Clock—ip—Period (time/dot)) / (H—op—Total (dots) x Clock—op—Period (time/dot)). But unfortunately the calculated V—〇p—Total (line#) 99% is a non-integer. ^ Some panels cannot accept that the length of the last score line is less than 90% of the length of the previous line, so the current solution is to remove the HSync pulse of the last line/line and remove the last line; or try the second clock. Or output the HS ync cycle. σ ι drama The invention divides the last score line into other exit lines, so some output HSync lines may have more points, and the /effect of the HSync tolerance (usually 1% of the range of variation) is still Figure 6 is about short/long line problems and wood after digestion. At last

Page 13 1280045 V. Description of invention (9): 1 The score line is short-term. When the next VSo arrives, HSO will be delayed for a short time', thus causing problems. If the HS of the last score line is omitted, # , / σ = long line 'Ting may make the digital panel unable to track the output HS week 1 and can generate unwanted images, such as white point garbage, shortened/delayed image lines or flickering. ··Wait. The present invention proposes a method of arranging the number of points of the last score line == a few lines. 'The first few lines are in the period of the vertical sync pulse (js_ync-FrontPorch), as shown in Fig. 6. Shown. ® #,母Γ, extra points of the digestive line = an integer of [(the last line of the " number of digestive lines)]. Taking an integer means omitting the score and adding "整数" to the integer part. On the eve, in order to assign the number of points in the last score line, it is best to have two lines of Φ t. If there is no linear buffer too fast / too slow, it can be the whole two 1' or use non-active lines, or only use vertical The line of the heartbeat during the sync pulse. The spirit and scope of the present invention is determined by the following patent application and is also limited to the above embodiments. One

1280045 Simple description of the diagram [Simple description of the diagram] Figure 1 is a schematic diagram of the timing waveform when the line buffer is too fast and too slow. Figure 2 shows a normal enlarged image. Figure 3 shows an image of the line buffer too fast. Figure 4 shows an image where the line buffer is too slow. Figure 5 is a schematic diagram of the output horizontal synchronous oscillation of the present invention. Figure 6 is a schematic diagram of digestion of the last line of the present invention. [Main component symbol description] VSi vertical synchronization into HDEi horizontal data start input VSo vertical synchronization out HDEo horizontal data start output HSi level into HSo level

Claims (1)

L28〇〇45 II. Application for patent range Adjustment number Vertical timing Vertical synchronization Vertical synchronization Vertical display Vertical synchronization In the vertical display, the horizontal synchronization total type buffer is accumulated, and the synchronous round-out total point is) t. The level of the fractional partial punch designed to be the general number of rounds is the same as 3 · One adjustment number, vertical timing • Vertical synchronous vertical synchronous vertical display Vertical synchronization in which a pre-out one vertical round is used The method of synchronizing in a rice display is divided into four segments in a digital display: pulse period (VSync - PulseTime), after pulse period (VSync_BackPorch), valid period (V_Display - Active), and before pulse period (VSync - FrontPorch); During the period, a preset output clock is used to calculate the number of points, and the integer part of the total number of points is regarded as a general output level synchronous output total number of points, and the fractional part of the total number of points is up to 1, the next output line type is made. The number of levels of the buffer is increased by one. In the range of the first item of the adjusted digital display in the digital display, the integer part of the total number of points is synchronously outputted as the total number of points of the type buffer, and the total point is accumulated until 2 o'clock. Let the next output line type slow down and add 2 points. The method of synchronizing in a bit display is divided into four segments in a digital display: during the pulse period (VSync-PulseTime), after the pulse period (VSync-BackPorch), during the valid period (V_Display_Active), and before the pulse period (VSync-FrontPorch); The round-out clock and the total number of horizontal synchronization output points calculate the number of buses, and the integer part of the number of buses is regarded as the general vertical page 1680045. 6. The number of direct output buses of the patent application range, and the fractional part of the bus number is horizontally synchronized. The total number of points is output to calculate the number of points of the last score line, and then the number of points of the last line > number line is digested into the previous output line type buffer. 4. A method of synchronizing in a digital display, as in claim 3, wherein the last fractional line is digested to a segment before the vertical sync pulse or other non-vertical display valid period. 5. As in the method of adjusting the digital display in the third aspect of the patent application, the extra points of each digestive line buffer are the integers of [(the last fractional line of points) / (the number of digestive lines)] , taking the integer • means to omit the fractional part and add 1 to the integer part. Page 17