TWI273639B - Etchant and method for forming bumps - Google Patents

Etchant and method for forming bumps Download PDF

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Publication number
TWI273639B
TWI273639B TW094135717A TW94135717A TWI273639B TW I273639 B TWI273639 B TW I273639B TW 094135717 A TW094135717 A TW 094135717A TW 94135717 A TW94135717 A TW 94135717A TW I273639 B TWI273639 B TW I273639B
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TW
Taiwan
Prior art keywords
etchant
layer
substrate
solder
acid
Prior art date
Application number
TW094135717A
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English (en)
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TW200715370A (en
Inventor
En-Chieh Wu
Hiew Watt Ng
Hui-Hung Chen
Chi-Long Tsai
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Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094135717A priority Critical patent/TWI273639B/zh
Priority to US11/462,720 priority patent/US7402510B2/en
Application granted granted Critical
Publication of TWI273639B publication Critical patent/TWI273639B/zh
Publication of TW200715370A publication Critical patent/TW200715370A/zh

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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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Description

1273639 九、發明說明: 【發明所屬之技術領域】 本發明係提供-種形成銲接凸塊的方法。 【先前技術】 . 覆晶接合(flip-chiP)技術是目前廣為利用的電子構裝技 •術。不同於傳統封農技術的是,在覆晶接合技術中,晶粒 φ (die)不再疋將銲塾經由打金線(wire bonding)的方式來電性 連接到-封裝基板上,而是將其反轉過來透過鲜接凸塊 ㈣如bUmP)來電性連接並裝著(mount)到封裝基板上。由 於覆晶接合技術不需要金線的連接,故能大幅縮小封裝體 的尺寸錢增加晶粒與縣基板間電路傳遞的速度。 請參考第1圖至第6圖,第1圖至第6圖為習知形成銲 接凸塊10的方法示意圖。如第1圖所示,首紐供一基底 # 12,例如一已完成内部元件及線路設置之晶圓。基底12之 表面上匕含有圖案化之保護層14 (passivation layer),且 保護層14係暴露出複數個銲墊16。其中銲墊16可由銅或 銘所構成,藉以電性連接形成於基底12巾之内部線路(圖 中未顯示)與封裝基板上之外部線路(圖中未顯示)。 ,如第2圖所示’接著利用濺鍍、沉積與蝕刻等製程形成 數層食$之凸塊下金屬層18(under bump metallurgy 1273639 layer),並覆蓋於每一銲墊16及保護層14。其中,凸塊下 金屬層18通常由一黏著層(adhesion layer)ll、一阻障層 (barrier layer)13、以及一潤濕層15所組成。黏著層11係 用以提供銲墊16及圖案化保護層14良好的黏著性,其材 質可為 %;_銶2 鉻二 ^ ^ ^ ^ ^ ^ ^ •與銲墊之金屬互相擴散,其材質可為鎳釩、鎳等。而潤濕 • 層15則係提供凸塊下金屬層18與銲球之間良好之沾附 —................... 性,其材質可為銅、鉬、鉑等。 .·* «r.*--·.' ··1 ...... v W.〜 丨 ’Pf '"»'»! »' ^^1,,,1)1,^,, 如第3圖所示,然後於整個基底12表面形成一光阻層 2〇,覆蓋於保護層14與凸塊下金屬層18上方。其中光阻 層20的材料可為乾膜光阻或液態光阻。接著如第4圖所 示’進行一曝光與顯影製程將光阻層20圖案化,以於光阻 層20形成複數個開口 22,並相對應地暴露出各銲墊“上 方之凸塊下金屬層18。然後利用電鐘的方式將一銲料24 鲁填佈於各開口 22中,其中銲料24可為錫或銅等材料。 在剝除光阻層20之後,如第5圖所示,接著進行一蝕 =製程,利用銲料24當作遮罩,並使用一由硝酸、醋酸、 礤酉欠雙氧水、鹽酸以及硫酸等混和溶液所組成之蝕刻劑 來姓刻錢於保護層14上之部分凸塊下金屬層18。如第6 圖所不,取後進行_回銲(refl〇w)製辛呈,以使鮮料以受熱 形成稷數個銲接凸塊1G於各相對應之料Μ上方,完成 1273639 習知形成銲接凸塊ίο的方法。 然而,由於受到利用硝酸、醋酸、磷酸、雙氧水、鹽酸 以及硫酸等混合溶液所組成的蝕刻劑之蝕刻選擇比的影 響,着知在蝕刻部分凸塊下金屬層18時,將會無可避免的 ......................... ....---------------- 侵蝕由錫所構成之銲料24,並同時侵蝕凸塊下金屬層18 _ —-··,—— ........................- 底部之黏著層11,造成底切現象,形成大小程度不同之底 切孔26。因此當後續進行回銲製程時,填入於開口 22内 之銲料24將會因底切孔26以及蝕刻劑侵蝕的緣故形成大 小不一的銲接凸塊10或是造成銲接凸塊10的位移 (composition shift),進而影響整個製程的良率與穩定性。 因此 何有效改善蝕刻劑於蝕刻製程時造成底切現象以 及侵蝕由錫所組成之銲料即為當前重要的課題之>。^ 【發明内容】 本發明之主要目的在於提供一種形成銲接凸塊的方 法,來解決上述習知之問題。 根據本發明之申請專利範圍,係揭露一種形成銲接凸塊 的方法。首先提供一基底,且該基底表面形成有一黏著層 (adhesion layer)、一 阻障層(barrier layer)與一濕潤層。然後 形成一圖案化光阻層於該潤濕層表面,且該圖案化光阻層 包含有至少一開口,用以暴露部分該濕潤層。接著填入一 1273639 銲料於該開口中,並進行一光阻剝離步驟,以移卜上 化光阻層。隨後進行第一蝕刻製程步驟,利用讀案 遮罩,以一第一蝕刻劑來蝕刻部分該濕潤層與部:料田: 層,其中該第一蝕刻劑係選自於由硫酸、磷峻:::該阻障 過硫酸銨、以及過硫酸氩鉀所組成的群組。接著氣化鐵、 二蝕刻劑進行第二蝕刻製程步驟,以蝕刻部分=利用一第 最後進行一回銲(reflow)製程以形成該銲接凸塊。黏著層, 由於本發明係填入銲料並剝除光阻層後,先利 酸、碟酸、氣化鐵、過硫酸銨、以及過硫酸氣卸^由石瓜 第-蝕刻劑來蝕刻凸塊下金屬層之部分濕潤層與成: 層’然後制用-由硫酸與去離子水所組成之第-刀阻, 來餘刻部分黏著層,因此可均勻_形成凸塊下劑 黏著層、阻障層以及潤濕層,進而避免習知利^酸= 酸、礙酸、雙氧水、鹽酸以及硫酸所組成之餘刻劑來㈣ 凸塊下金屬層時,過度紐黏著層而造成底切現象的發生^ 【實施方式】 請參照第7圖至第η圖,第7圖至第12圖為本發明形 成銲接凸塊4 8之-較佳實施例的方法示意圖。如第7圖所 示’首先提供-基底3〇,例如一已完成内部元件及線路設 置之晶圓’且基底3G表面形成有複數個導體結構,例如鲜 替32,其材質通常為銅或!g ’藉以電性連接形成於基底% 1273639 中之内部線路(圖中未顯示)與封裝基板上之外部線路(圖中 未顯不)。然後形成-圖案化保護層34覆蓋於基底3〇表面 、刀別暴硌各銲墊32之部分表面,用以保護基底3〇中之 内部線路(圖_未顯示)。 如第8圖所示,接著進行一濺鍍製程(spmtering)、沉積 與蝕刻等製程,以形成複數層堆疊之凸塊下金屬層36並覆 _ 蓋於邛为暴露出之銲墊32與圖案化保護層34表面。其中, 凸塊下金屬層36通常由一黏著層38、一阻障層40、以及 /閏濕層42所組成。黏著層38係用以提供銲墊32及圖案 化保護層34良好的黏著性,其材質可為鋁、鈦、鉻、鎢化 鈦等。阻障層40係用以防止銲球與銲墊之金屬互相擴散, 其材質可為鎳鈒、鎳等。而潤濕層42則係提供凸塊下金屬 層36與銲球之間良好之沾附性,其材質可為銅、鉬、鉑等。 • 如第9圖所示,隨後形成一圖案化遮罩,例如先於凸塊 下金屬層36表面形成一光阻層44,而光阻層44可選用液 態光阻或乾膜光阻。如第1〇圖所示,然後進行一曝光顯影 製程’以相對應地暴露出各銲墊32上方之凸塊下金屬層 36,同時形成後續銲接凸塊的開口 45。換言之,此開口 45 即為後續填入之銲料與凸塊下金屬層36之結合區,故其厚 度係與後續將形成之銲接凸塊的高度相關 0此外 > 在本較 佳實施例中’開口 45係位於銲墊32之正上方,然而不侷 1273639 限於本實施例,開口 45 乂、 下金屬層36上,以配合咖也·成於鄰近於銲墊32之凸塊 需要而需變更接點的位置;.—疼皇中因接點配置設計上的 如第11圖所示,接薯推r _ ,甘^ 進仃一電鍍製程以填入一銲料46 於開口 45卜其中銲料46可為锡或銅等材料。隨後進行 -光阻剝離步驟’以移除光阻層44。
製程,利用銲料46當作遮罩 、丁弟 』 下金屬層36之部分濕潤層42_f—㈣劑來触刻凸塊 / 』層42與部分阻障層4〇。其中,該 第一蝕刻劑係選自由硫酸、磷酸、 %鲛虱化鐵、過硫酸銨、以 及過硫酸氫觸喊的群組。最後再仙U刻劑進 行第二似程步驟,叫卿分㈣層%,其中該第二 蚀刻劑包含有硫酸與去離子水之組成。 值得注意的是,由於本發明係先利用—由硫酸、填酸、 氯化鐵、過硫酸銨、以及過硫酸氫钾所組成的第一触刻劑 來蚀刻凸塊下金屬層之部分濕潤層42與 4〇, 然後再個4魏料離子水賴成之第二㈣劑來餘 刻部分黏著層38’因此可均勻#刻形成凸塊下金屬層% 之黏著層38、阻障層40 α及潤濕層42,進而避免習知利 .用硝酸、醋酸、_、雙氧水、贿以及硫酸所組成之钱 刻劑來蝕刻凸塊下金屬層36時,過度侵蝕黏著層38而造 成底切的現象。除此之外,當填入開口 45之銲料46係由 1273639 錫所組成時,利用本發明之第一蝕刻劑與第二蝕刻劑之組 成成分來進行蚀刻製程時,又可同時避免習知之蝕刻劑因 侵蝕由錫所組成之銲料而造成後續銲接凸塊位移以及大小 不均的現象發生。 最後如第12圖所示,再對銲料46進行一回銲(reflow) 製程,使銲料46受熱並因表面張力而變成球狀,以形成一 銲接凸塊48於所對應之銲墊32與凸塊下金屬層36上。 此外,根據上述較佳實施例之第一蝕刻劑與第二蝕刻 劑,本發明另揭露一種應用於銲接凸塊製程之蝕刻劑配 方,該#刻劑包含有硫酸、鱗酸、氯化鐵、過硫酸銨、過 硫酸氳鉀、鹽酸、銅安定劑、氯安定劑以及去離子水所組 成的群組。其中,該硫酸之體積百分比濃度係介於30〜35% 之間、該磷酸之體積百分比濃度係介於5〜8%之間、該過 φ 硫酸銨之體積百分比濃度係介於8〜11%之間、該氯化鐵之 體積百分比濃度係介於2〜10%之間、該鹽酸之體積百分比 濃度係小於5%、該銅安定劑之體積百分比濃度係為0.5%、 該氯安定劑之體積百分比濃度係介於1〜2%之間、該去離 子水之體積百分比濃度係介於35〜55%之間以及該過硫酸 氫鉀之體積百分比濃度係介於8〜11%之間。 綜上所述,相較於習知製作銲接凸塊的方法,本發明係 12 1273639 ,入銲料並剝除光阻廣後,先利用_由硫酸、_、氯化 、载、過硫酸銨、以及過硫酸氣卸所組成的第一姓刻劑來兹 ㈣束下金屬層之部分濕潤層與部分阻障層,然後再利用 I由硫酸與絲子水所組叙第二偏㈣來關部分黏著 胃’因此可以適當之_選擇比來分別均勾祕刻形成凸 塊下金屬層之黏著層、阻障層以及潤濕層,進而避免習知 利用硝酸、醋酸、磷酸、雙氧水、鹽酸以及硫酸所組成之 •料劑來姓刻凸塊下金屬層時,發生過度侵姓黏著層 而造 成底切現象。 以上所述僅為本發明之較佳實施例,凡依本發明申請專 利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 籲=目至第6圖為習知形成銲接凸塊的方法示意圖。 7圖至第為本發明形成銲接凸塊之-較佳實施例的 方法不意圖。 【主要元件符說說明】 10 杯接凸塊 11 黏著層 12 基底 13 14 保護層 阻障層 15 潤濕層 13 1273639 16 銲墊 18 凸塊下金屬層 20 光阻層 22 開口 24 銲料 26 底切孔 30 基底 32 銲墊 34 圖案化保護層 36 凸塊下金屬層 38 黏著層 40 阻障層 42 潤濕層 44 光阻層 45 開口 46 銲料 48 銲接凸塊 14

Claims (1)

1273639 十、申請專利範圍: 1. 一種形成銲接凸塊的方法,該方法包含有: 提供一基底,且該基底表面形成有一黏著層(adhesion layer)、一 阻障層(barrier layer)與一濕潤層; 形成一圖案化光阻層於該潤濕層表面,且該圖案化光阻 層包含有至少一開口 ^用以暴露部分該濕潤層; 填入一銲料於該開口中; 進行一光阻剝離步驟,以移除該圖案化光阻層; 利用一第一蝕刻劑進行第一蝕刻製程,利用該銲料當作 遮罩以ϋ刻部分該濕潤層與部分該阻障層,其中該第一餘 刻劑係選自於由硫酸、磷酸、氯化鐵、過硫酸銨、以及過 硫酸氫鉀所組成的群組; 利用一第二蝕刻劑進行第二蝕刻製程,以蝕刻部分該黏 著層;以及 進行一回銲(reflow)製程以形成該鮮接凸塊。 2. 如申請專利範圍第1項所述之方法,其中該基底係為一 晶圓。 3. 如申請專利範圍第1項所述之方法,其中該基底與該凸 塊下金屬層之間另包含有: 至少一銲墊,電連接設於該基底中的電路;以及 15 1273639 一圖案化保護層,覆蓋於該基底表面並暴露部分該銲 墊。 4. 如申請專利範圍第3項所述之方法,其中該開口係位於 該銲墊上方。 5. 如申請專利範圍第1項所述之方法,其中該黏著層係包 含有銘、鈦、鉻、或鎢化鈦之組成。 6. 如申請專利範圍第1項所述之方法,其中該阻障層係包 含有鎳或鎳釩之組成。 7. 如申請專利範圍第1項所述之方法,其中該濕潤層係包 含有銅、鉬、或鉑之組成。 8. 如申請專利範圍第1項所述之方法,其中該第二蝕刻劑 係包含有硫酸與去離子水之組成。 9. 一種應用於銲接凸塊製程之蝕刻劑,該蝕刻劑包含有硫 酸、攝酸、氯化鐵。 10. 如申請專利範圍第9項所述之蝕刻劑,其中該蝕刻劑另 包含有過硫酸銨。 16 1273639 11. 如申請專利範圍第9項所述之蝕刻劑,其中該蝕刻劑另 包含有過硫酸氫鉀。 12. 如申請專利範圍第9項所述之蝕刻劑,其中該硫酸之體 積百分比濃度係介於30〜35%之間。 13. 如申請專利範圍第9項所述之蝕刻劑,其中該磷酸之體 積百分比濃度係介於5〜8%之間。 • 14. 如申請專利範圍第10項所述之蝕刻劑,其中該過硫酸 銨之體積百分比濃度係介於8〜11%之間。 15. 如申請專利範圍第9項所述之蝕刻劑,其中該氯化鐵之 體積百分比濃度係介於2〜10%之間。 16. 如申請專利範圍第9項所述之蝕刻劑,其中該蝕刻劑另 包含有鹽酸、銅安定劑、氯安定劑、以及去離子水。 17. 如申請專利範圍第16項所述之蝕刻劑,其中該鹽酸之 體積百分比濃度係小於5%。 18. 如申請專利範圍第16項所述之蝕刻劑,其中該銅安定 劑之體積百分比濃度係為0.5%。 17 1273639 19. 如申請專利範圍第16項所述之蝕刻劑,其中該氯安定 劑之體積百分比濃度係介於1〜2%之間。 20. 如申請專利範圍第16項所述之蝕刻劑,其中該去離子 水之體積百分比濃度係介於35〜55%之間。 21. 如申請專利範圍第11項所述之蝕刻劑,其中該過硫酸 氫鉀之體積百分比濃度係介於8〜11%之間。 十一、圖式: 18
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401775B (zh) * 2008-07-24 2013-07-11 Chipmos Technologies Inc 具基板支柱之封裝結構及其封裝方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
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US20120009777A1 (en) * 2010-07-07 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. UBM Etching Methods
US9484259B2 (en) * 2011-09-21 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US9082832B2 (en) 2011-09-21 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US9029268B2 (en) * 2012-11-21 2015-05-12 Dynaloy, Llc Process for etching metals
US10522501B2 (en) 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
CN110233115B (zh) * 2019-05-29 2020-09-08 宁波芯健半导体有限公司 一种晶圆级芯片封装方法及封装结构

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TWI239578B (en) * 2002-02-21 2005-09-11 Advanced Semiconductor Eng Manufacturing process of bump
US6780751B2 (en) * 2002-10-09 2004-08-24 Freescale Semiconductor, Inc. Method for eliminating voiding in plated solder

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