TWI271842B - Array circuit substrate - Google Patents
Array circuit substrate Download PDFInfo
- Publication number
- TWI271842B TWI271842B TW095100316A TW95100316A TWI271842B TW I271842 B TWI271842 B TW I271842B TW 095100316 A TW095100316 A TW 095100316A TW 95100316 A TW95100316 A TW 95100316A TW I271842 B TWI271842 B TW I271842B
- Authority
- TW
- Taiwan
- Prior art keywords
- test
- wire
- circuit substrate
- line
- wires
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000005520 cutting process Methods 0.000 claims description 18
- 238000007747 plating Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims 1
- 238000001259 photo etching Methods 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract 3
- 235000012431 wafers Nutrition 0.000 description 19
- 238000003466 welding Methods 0.000 description 17
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005491 wire drawing Methods 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
12 7184^twf.d〇c/r 九、發明說明·· 【發明所屬之技術領域】 -種於—辩列線路基板,且特別是有關於 rl重不黏測試的陣列線路基板。 【先丽技術】 的H版產業中,積體電路(integrateddrcuits,ic)
d ., 可刀為二個階段··積體電路的設計(IC !:SJ process) ^ PaC啡。在積體電路的製作中,晶片(di )是 ,晶圓製作、形成積體電路以及切‘圓= 7寻步驟而完成。晶圓具有一主動面(active m晶圓之具有主動元件(―㈣的 =。“®之频電路完叙後,㈣之 :!f^T;b:d:ngpad) 的曰曰片,可經由這些銲墊而向外電性連接於 (^) 〇 (leadframe) (mpchipbonding) ^^4;" 、上,使得晶片之這些輝墊可分別電性連接 多個接點,以構成一晶片封裝體。 就打線接合技術(wireb〇ndingtechn〇1〇gy)而+,米 晶片以-膠層(epoxy)黏著於封裝基板上後,接^用: 壓合(thermal compression)銲接或超音波銲接的方 =、 各個銲線(bonding wire )的兩端分別連接至晶片與^壯1 12 7 1 板上,以使得晶片與封裝基板彼此 ㈣的兩端是否良好地銲接於晶== 封I基板之接點上,關係著晶月 二之1于墊和 這” If鮮不黏測試—爾“的目= -1 ® ^ ^ f〇^;f f ^ ^平夕】綠路基板100包括多數個基板單 二一 έ弟一電鑛線120與多數個切割窗13 僅 =,片)配置於基板單元110上,並藉由^ 鄰的打線接合墊112電性連接。其中,相 =之間係以方格狀之第一電麟⑽ =4:: 10内具有多數個第二電鍍線114, 112 I便成N式訊唬可經由第一電鍍線丨 122到達第二電鑛線114,再由第二電鑛線114傳導= 接之_合墊112與晶片1〇上的=泉114傳衫相連 怂所迹’當藉由此測試訊號回報銲不黏測試系统之 統可判斷銲線12是否鐸接於晶片10之銲墊1 = 甚至1所不,當切割窗13。將第二電鑛線114切斷:、 士入=一電鑛線120也切斷時,將使得銲不黏測試機制 至:ι"ί成測試訊號無法經由完整的第一電鍍線⑶ 122 °若以人工目視的方式取代測執系統 ::二’:’以發現是否有銲不黏的現象發生時,由於人卫 ―,阳 > 確性較低且必須在打線接合製程完成後才可進 此白知目測銲不黏技術的準確性不佳且無法及時發 現銲不黏的問題。 【發明内容】 本%明之目的b蔣 黏測試的準雜且在^種陣列線路基板,以提高鮮不 為達上述或是心、、泉衣程中及時發現銲不黎的問題。 板,其包括多數提出一種陣列線路基 數個切割窗。這料、多數條銲不黏測試線路與多 及多數個電鑛線,^ 分別具有多數個打線接合墊以 合墊之-,其中這此電=鑛線之一對應連接這些打線接 黏測試線路分別配之為測試線。這些銲不 這些 之外的這些電鍍線,且未切斷 _窗分別切斷除了測_ 二基板早兀中 這些銲不黏測試線路。 wire bonder)將 之一上。 -第3:'之一實施例中,-打線機 弟鋅線之弟一端銲接於一曰片夕夕虹乂 一在本發明之-實施例中,:打線 :端銲接於-晶片之多數個銲墊之—上二一銲線之第 上。以―一接於與職線電性連接之打線接合墊 之—實施射,上述這些切割窗可 以光钱刻 在本發明 所形成。 刻或實珊,上物靖可以赚 在本發明之-實施例中,上述這些切割窗可大致上平 1271842twf*doc/r 打於相鄰之這些銲不黏測試線路。 ⑽〜之—實施例巾,上述這些切贿寬度大約為 絲實施例巾,上述這些切㈣與相鄰之銲 不站測试線路相隔約50微米。 utt4’由於本發明之_線路基板可提供作為銲 =ί:測試電流流動的媒介,因此本發明之陣列線路 i=r:不黏測試的準確性提高。此外,由於本發明之 本發明之ϋΐ在打線接合時立即進行銲不黏測試,因此 合_銲不可及時發現打線接 易僅為和其他目的、特徵和優雜更明顯 明如下 ^貫施例,並配合所附圖式,作詳細說 【實施方式】 基板二2圖其:;本發明-實施例之-種陣列線路 數個基板單元Γο、多線路基板200包括多 塾3以單元210分別具有多數個打線接合 上212以及多數個醜線別,且這些電 二 之-對應連接這些打線接合墊212的其中:久二 板單元210的這些電錢線214中£ ㈣口個基 稱測試線陶不被切割窗230切斷下 相鄰之銲不黏測試線路22〇。 "此包性連接至 8 12 718碎这twf.d〇c/r ^所二4線路22G與電鍍線214為習知電鍍製 二之;央二因此在_製程之後,利用電鍍製程所 佈¥、、泉來作為鋒不黏測試線路22〇及測試線2Ha,則 線路基板2〇0上配線。其中,銲不黏測試 ..泉路22W別配置於相鄰二基板單元21〇《間,並連接測 试線f4a至一測試接點τ,以形成一完整的測試線路。值 付Ϊ意的fi在麵製程讀,赌每—絲料210中 的14些切割窗23〇分別切斷除了測試線施之外的這些電 鑛線別,且—未切斷這些鋒不黏測試線路,。在本實施例 可以絲刻、濕式钱刻或乾式钱刻的 方式而形U以使得除了測試線214a之外此 線2M與這些銲不黏測試線路22〇之間形成斷路。二1
就位置而言丄在本實施例中,這些切割窗23〇可大致 上平打於相鄰之这些鋒不黏測試線路22〇,且這些 230與相鄰之銲不黏測試線路22〇相隔約5〇微米:餅型 而言,在本實施例中’這些切割窗23〇的寬度%大約 100〜200微米。由於這些切割窗23〇用以使得除 2i4a之外的這些電鑛線2M與這些銲不黏測試線路-之 間形成斷路,因此在不影響上述功能下,這些 的位置與外柯依照設計者的需求而有所改變 僅用以舉例而非限定本發明。 J 以下就使用本實施例之㈣線路基板·* 進行打線接合製程與録不黏測試作一說明。&來 其繪示使用圖2之陣列線路基板而與晶片進=線=製 1271842twf*d〇c^ 私以及鲊不黏測試的示意圖 示意地緣示一個晶片20 ,為了以下說明方便僅 一上。在本實施例中,打後些基板單元21〇的其中之 一打線機30將一第一銲線妾5 ‘程包括下列步驟。首先, 之多數個銲墊22的其中之」〇之第一端42銲接於晶片20 4〇接觸晶片20的周邊區域,接者’為了不使第一銲線 -銲線4G之第二端44銲^ ^線機3G拉出—線弧且將第 線接合墊212a上。接菩4、〃測試線214a電性連接之打 一具有探針議% t性連接於 性連接,因此經由上述打線拉幻與測試接點T相電 銲線50若銲接狀況良好;Π-銲線4〇與第二 試線細、魏 ^1πςρΗ -., 、打、、泉枝30將形成一閉合電路 第二Γ線:S’ α此時二若有一電流由打線機30而流向 地,若I,/1測試器60可接收到此電流訊號。相反 於-預言二,:Ϊ不f電流訊號或所接收的電流訊號小 狀況不π」表不第一銲線40或第二銲線50的銲接 f L行後續打線接合製程。請參考圖4,其繪示 二對^ L列泉路基板與晶片進行後續打線接合製程以及銲 測試的示意圖。打線機3〇將第二銲線5〇之第二端54 1271842twfd〇c/r =於基板單元2H)之剩餘這些打線接合墊犯的呈中之 料且切斷第二節G之第二端54與打線機%的連接 H’!1行銲不黏職。由於打線機3G與第二_ L:么’因此上述的閉合電路觸 4,:試器6。無法接收到此電流訊號。相 15ΐΓΓ收到電流訊號,則表示第二焊線%的第 Μ 之間的連接並未完全切斷,而且第二 的姉進而==未完全切斷而遭受打線機3。 22金=輩重2行上述步驟,直到晶片2G的這些銲墊 :土板早TC21G的14些打線接合墊212的打線接人 牛" 接合結構經由後續的封膠、植 同型態的晶片封裝體,在此不再詳述。 路可提供作為 測試線路被切割窗切斷而造成;不: -)由於本發明之㈣線路基板可在打線接合後立 1271841 twf.doc/r 即進行銲不黏测試 =陣列線路基板使得銲;相較’本 後的銲不黏問題。 J及~發現打線接合 本發明已以較佳實施例揭露如上,m 和範圍内,當可作也許不脫離本發明之精神 【圖式簡單說明】 示】:之一種陣列線路基板的俯視示意圖。 示意圖。、曰不本务明一實施例之一種陣列線路基板的俯視 圖3緣示使用圖2之陣列 接合製程以及鋒不_試的示意圖。板而”曰曰片進订打線 人制線路基板與晶片進行後續打線接 口衣轾以及鋅不姑測試的示意圖。 【主要元件符號說明】 10、20 :晶片 22 :銲墊 30 :打線機 40 :第一銲線 42 :第一銲線的第一端 44 :第一銲線的第二端 50 :第二銲線 52 :第二銲線的第一端 12 12 了 1 ^ly8p^twf.doc/r 54 :第二銲線的第二端 60 :測試器 62 :探針 100、200 :陣列線路基板 110、210 :基板單元 112、212、212a :打線接合墊 114 :第二電鍍線 120 :第一電鍍線 130、230 :切割窗 220 :銲不黏測試線路 214 :電鍍線 214a :測試線 T:測試接點 W :切割窗的寬度 13
Claims (1)
1271 十、申請專利範圍: 一種陣列線路基板, 多數個基板單亓,八, 數個電鍵線,且該此具有多數個打線接合墊以及多 之―,其中該也電一對應連接該些打線接合墊 多盤伙锻、、泉至少一為測試、線; 之間,If、^ 機線路,分別配置於相鄰二基板單元 之間^連接測試線至一測試接點;以及 扳早凡 別切ΐ除了固之ί於f些基板單元中,該些切割窗分 黏测試線路。1 ❸雜電鍍線,且未切斷該些銲不 墊之上。、干線之弟一端銲接於一晶片之多數個銲 % i如申請專利範圍第2項所述之陣列線路基板,並中 兮士 4·如申明專利範圍第1項所述之陣列線路基板,其中 〜二切割窗以光蝕刻所形成。 /、 5·如申請專利範圍第i項所述之陣列線路基板,其 切割窗以濕式蝕刻或乾式蝕刻所形成。 二6·如申請專利範圍第1項所述之陣列線路基板,其中 名些切割g大致上平行於婦之該些銲不侧試線路。 ^ 7·如申請專利範圍第1項所述之陣列線路基板,其中 該些切割窗寬度大約為100〜2〇〇微米。 /、 ^ 8·如申請專利範圍第1項所述之陣列線路基板,其中 該些切割窗與相鄰之銲不黏測試線路相隔5〇微米。 14
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095100316A TWI271842B (en) | 2006-01-04 | 2006-01-04 | Array circuit substrate |
US11/309,680 US20070152348A1 (en) | 2006-01-04 | 2006-09-11 | Array circuit substrate and wire bonding process using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095100316A TWI271842B (en) | 2006-01-04 | 2006-01-04 | Array circuit substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI271842B true TWI271842B (en) | 2007-01-21 |
TW200727435A TW200727435A (en) | 2007-07-16 |
Family
ID=38223528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095100316A TWI271842B (en) | 2006-01-04 | 2006-01-04 | Array circuit substrate |
Country Status (2)
Country | Link |
---|---|
US (1) | US20070152348A1 (zh) |
TW (1) | TWI271842B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113161251A (zh) * | 2020-01-22 | 2021-07-23 | 复格企业股份有限公司 | 芯片封装的工艺内测试方法及装置 |
-
2006
- 2006-01-04 TW TW095100316A patent/TWI271842B/zh active
- 2006-09-11 US US11/309,680 patent/US20070152348A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TW200727435A (en) | 2007-07-16 |
US20070152348A1 (en) | 2007-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9406628B2 (en) | Semiconductor device and method of manufacturing the same | |
TW201003877A (en) | Bond pad structure of integrated circuit | |
TWI278073B (en) | Semiconductor device | |
JP6033011B2 (ja) | 電力用半導体装置および電力用半導体装置の製造方法 | |
JP2011071317A (ja) | 半導体装置 | |
JP2003174120A (ja) | 半導体装置およびその製造方法 | |
TW200919693A (en) | Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same | |
TW201530758A (zh) | 半導體裝置及半導體裝置之製造方法 | |
TW588445B (en) | Bumpless chip package | |
JP4635202B2 (ja) | 両面電極パッケージの製造方法 | |
TWI550740B (zh) | 半導體裝置及其製造方法 | |
TWI278110B (en) | Test circuit under pad | |
JP7334435B2 (ja) | 半導体装置および半導体装置の検査方法 | |
TWI316741B (en) | Method for forming an integrated cricuit, method for forming a bonding pad in an integrated circuit and an integrated circuit structure | |
TWI271842B (en) | Array circuit substrate | |
US20040245651A1 (en) | Semiconductor device and method for fabricating the same | |
US9410987B2 (en) | Probe card | |
CN208045486U (zh) | 晶圆级芯片封装结构 | |
JP2007214238A (ja) | 半導体装置およびその製造方法 | |
US8614514B1 (en) | Micro-spring chip attachment using ribbon bonds | |
US8519547B2 (en) | Chip arrangement and method for producing a chip arrangement | |
TWI358337B (en) | Method and device of continuously wire-bonding bet | |
JP2007258381A (ja) | 半導体装置及びその製造方法 | |
US20110241026A1 (en) | Light-emitting diode chip and package structure thereof | |
WO2009030078A1 (en) | Inner lead structure of semiconductor device |