1269264 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種薄膜電晶體液晶顯示器面板，特別 是關於一種薄膜電晶體液晶顯示器面板閘極驅動電路的 電源電路。 【先前技術】 φ 在薄膜電晶體(TFT)液晶顯示器（Lcd)面板系統中，為 了使晝面在開機時即呈現最佳的晝面品質，而設計一控制 電路控制開機程序，使電源信號經過一延遲後輸出給閘極 驅動1c，以得到最佳的畫面品質。圖1係習知TFT LCD 面板閘極驅動電路的電源電路100的示意圖，一低壓邏輯 電路I60連接一電源信號VIN，根據一由時脈控制1C產 的時脈信號VFLK產生一控制信號CRL給控制電路15〇 以控制電源電路100的輸出，一由VIN產生的電源信號 • VGH連接一電容108後輸入至電源電路100，經控制電路 150後產生-輸出信號VGHM給TFT LCD的閘極驅動電 路124。低壓邏輯電路160包括一延遲電路丨丨❹與vin連 •接以產生-延遲信號，舰遲信號與观作為或閘ιΐ2的 —輸人’該延遲信號與WLK作為反及閘m的輸入，或閉 112與反及閘114的輸出作為及％ 116的輸入以產生 CRL。控制電路150包括開關118與12〇以及一與開關12〇 連接的電阻122，藉由CRL控制開關U8及12〇的開啟或 關閉，進而控制電源電路100的輸出。圖2係圖ι的時序 1269264 圖200 ’同時參考圖1及圖2，當電源開啟VIN由低準位 上升至咼準位時’ VGH開始由低準位上升至高準位，藉由 CRL控制開關118及120的開啟或關閉，使VGH經控制 電路150後產生一與VIN相差一延遲時間210的VGHM 給TFT LCD的閘極驅動1C 124，以使晝面在一開機即呈 • 現农佳的晝面品質’延遲時間210隨面板廠商的不同而不 同，大約介於20ms至100ms之間，此時若VFLK為高準 φ 位，則及閘H6的輸出為低準位，開關118及120分別為 開啟狀態及關閉狀態，VGHM等於VGH，若VFLK為低 準位時’則及閘Π6的輸出為高準位，開關η8及丨2〇分 別為關閉狀態及開啟狀態，VGHM經由電阻122對地放電 產生削角240，經由改變電阻122的大小可調整削角24〇 的下降時間以改善TFT LCD面板晝面閃動（flicker)的情 开>，提昇TFT LCD面板的晝面品質。但當電源關閉時， VGHM在彳艮短的時間内便由高準位下降至低準位，如區域 春22G所示，使得TFT在執行關機時仍有電荷殘留其中導致 影像殘留在面板上產生殘影現象，此殘影現象可經由使 V GHΜ在執行關機時緩慢地由高準下降至低準位，如區域 230 1示，以使TFT中的電荷完全釋放而解決。 習知使VGHM在執行關機時緩慢地由高準下降至低 準位的方法有在印刷電路板(PCB)上增加所㈣元件或在 VGHM與閘極驅動IC之間增加一大電容二種。在印刷電 路板上增加元件的好處在於可藉由調整呢腿的削角改 。旦的’其缺點在於增加的元件導致製造成本的增 6 1269264 加。在VGHM與閘極驅動1C之間增加一大電容的好處在 於不會增加製造成本，其缺點在於無法藉由調整VGHM的 削角改善畫面的品質。 因此，一種不會增加製造成本且可調整削角與消除殘 影的TFT LCD面板閘極驅動電路的電源電路，乃為所冀。 【發明内容】 0 本發明的目的，在於提供一種可調整削角且可消除殘 影現象的TFT LCD面板閘極驅動電路的電源電路。 根據本發明，一種TFT LCD面板的閘極驅動電路的 電源電路包括一低壓邏輯電路連接一第一電源信號，並根 據一電壓信號產生一控制信號，一關機電路連接該第一電 源信號及一第二電源信號，藉以判斷該電源電路的狀態產 生一關機信號，以及一控制電路根據該控制信號及該關機 信號控制該電源電路的輸出，其中，該第二電源信號由該 • 第一電源信號產生。 本發明利用二電源信號使TFT LCD面板閘極驅動電 路的電源電路在正常工作及執行關機時均有信號使該電 ‘ 源電路中的控制電路正確作動，使得在執行關機時該電源 ^ 電路的輸出信號由高準位缓慢下降至低準位，解決習知單 一電源信號在執行關機時無法使該控制電路正確作動，導 致該電源電路的輸出信號由高準位迅速下降至低準位所 產生的殘影現象。 7 !269264 【實施方式】 ^圖3係本發明之TFT LCD面板閘極驅動電路的電源 電路300的示意圖，電源電路300包括一低壓邏輯電路310 j接主電源信號VIN卜根據一電壓信號VFLK(例如一由 寸脈抆制1C產的時脈信號)產生一控制信號CRL1，一關 •機電路320連接VIN1及一由v而產生的電源信號 • VIN2，並根據·1及VIN2判斷電源電路300的狀態產 •生一關機信號Pwr〇ff，一控制電路330根據CRL1及 PwrOff控制電源電路3〇〇的輸出，使一輸入信號v⑽(例 如一由VIN1產生電源信號）經控制電路33〇後產生輸出信 旒V(3HM給TFT LCD的閘極驅動電路。控制電路mo包 括一準位位移電路340根據CRL1及PwrOff產生控制信號 CRL2及CRL3 ’ 一驅動單元35〇根據crl2及CRL3控制 開關360及370的開啟或關閉以產生VGHM，當開關36〇 開啟時，VGHM充電至VGH，當開關37〇開啟時，vghm ❿經由一電阻380對地放電。 圖4係圖3中關機控制電路32()的示意圖，參照圖3 •及圖4 ’偵測單元322及324分別偵測VIN1及VIN2的準 =產生㈣PG1及PG2給狀態判斷單元326，當vim為 同準位日寸PG1為邏輯”Γ，，反之則為邏輯，，〇，，，同樣地，當 1別\為南準位時PG2為邏輯”1”，反之則為邏輯”〇,，狀 326 PG1> PG2 t ^ 300 、田PG1為远輯1而PG2為邏輯，，〇，，時，電源電路goo 為執行開機狀態，當PG1及PG2均為邏輯” i，，時，電源電 1269264 , 路300為正常工作狀態，當pgi為邏輯，，〇，，而pG2為邏 輯1時，電源電路300為執行關機狀態，當pm及pG2 均為邏輯”0”時，電源電路300為已關機狀態，關機邏輯 328在狀態判斷單元326判斷電源電路3〇〇為執行關機狀 態時，產生關機信號PwrOff。 - 圖5係本發明之TFT LCD面板閘極驅動電路的電源 電路3⑼的一實施例，一低壓邏輯電路31〇包括一延遲器 φ 540、一或閘56〇以及一反及閘550,延遲器540連接VIN1 以產生一延遲信號，該延遲信號與VIN1作為或閘56〇的 輸入，該延遲信號與VFLK作為反及閘55〇的輸入，一關 機電路320連接乂腿及乂1犯，根據乂腿與乂腿的準 ；位產生Pwr〇ff’一控制電路330包括一準位位移與驅動單 •元510、開關360與370以及連接在開關370與接地端之 間的電阻380 ’或閘560與反及閘550的輸出以及pwr〇ff 作為準位位移與驅動單元sl〇的輸入，以產生控制信號控 •制開關36〇及370的開啟或關閉，VGH連接一電容52〇 經控制電路330後產生VGHM給閘極驅動電路57〇。在此 實2例中，開關360及370分別為閘極連接準位位移與驅 動單元510輸出端的PM0S電晶體及NM〇s電晶體。 11 6係圖5的時序圖參照圖5及圖6，當電源 開啟時’ vmi由低準位上升至高準位產生—開機信號 PG，電源電路300進入執行開機狀態61〇，隨後vin2盥 VGH因應PG由低準位逐漸上升至高準位，電源電路獨 進入正常工作狀態62〇，pG經延遲器54〇輸出一與相 12692641269264 IX. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor liquid crystal display panel, and more particularly to a power supply circuit for a gate driving circuit of a thin film transistor liquid crystal display panel. [Prior Art] φ In the thin film transistor (LCD) liquid crystal display (Lcd) panel system, in order to make the kneading surface exhibit the best kneading quality at the time of booting, a control circuit is controlled to control the booting process, so that the power signal passes. After a delay, it is output to the gate driver 1c for the best picture quality. 1 is a schematic diagram of a power supply circuit 100 of a conventional TFT LCD panel gate driving circuit. A low voltage logic circuit I60 is connected to a power supply signal VIN, and a control signal CRL is generated according to a clock signal VFLK generated by the clock control 1C. The circuit 15 is configured to control the output of the power supply circuit 100, a power supply signal generated by the VIN, VGH is connected to a capacitor 108, and then input to the power supply circuit 100. After the control circuit 150, the output signal VGHM is generated to the gate driving circuit 124 of the TFT LCD. . The low voltage logic circuit 160 includes a delay circuit 丨丨❹ connected to vin to generate a delay signal, a ship delay signal and an input of the delay signal and WLK as an input of the inverse gate m, or The output of the closed 112 and the inverse gate 114 acts as an input to % 116 to generate the CRL. The control circuit 150 includes switches 118 and 12A and a resistor 122 connected to the switch 12A. The CRL controls the opening or closing of the switches U8 and 12A to control the output of the power supply circuit 100. Figure 2 is the timing of 1 ι264. Figure 200 'At the same time, referring to Figure 1 and Figure 2, when the power-on VIN rises from the low level to the 咼 level, the VGH starts to rise from the low level to the high level, and the switch is controlled by the CRL. The opening or closing of 118 and 120 causes the VGH to generate a VGHM which is delayed by a delay time 210 from the VIN via the control circuit 150 to the gate driving 1C 124 of the TFT LCD, so that the surface of the TFT is turned on at the start of the operation. The surface quality 'delay time 210' varies with panel manufacturers, which is between 20ms and 100ms. If VFLK is high-precision φ, then the output of gate H6 is low, and switches 118 and 120 respectively VGHM is equal to VGH for the on state and the off state. If the VFLK is at the low level, then the output of the gate 6 is at the high level, the switches η8 and 丨2〇 are respectively the off state and the on state, and the VGHM is grounded via the resistor 122. The discharge produces a chamfer 240. By changing the size of the resistor 122, the fall time of the chamfer 24 可 can be adjusted to improve the flicker of the TFT LCD panel, and the surface quality of the TFT LCD panel is improved. However, when the power is turned off, the VGHM drops from the high level to the low level in a short period of time. As shown in the area 22G, the TFT still has charge remaining during the shutdown, which causes the image to remain on the panel. The image sticking phenomenon, which can be solved by causing V GH 缓慢 to slowly drop from high level to low level when performing shutdown, as indicated by region 230 1 , to completely release the charge in the TFT. Conventional methods that allow the VGHM to slowly drop from high to low when performing a shutdown have either added (4) components to the printed circuit board (PCB) or added a large capacitance between the VGHM and the gate drive IC. The added benefit of adding components to a printed circuit board is that it can be modified by adjusting the chamfering of the leg. The shortcoming of 'the increase is that the added components lead to an increase in manufacturing costs of 6 1269264 plus. The advantage of adding a large capacitance between the VGHM and the gate drive 1C is that it does not increase the manufacturing cost. The disadvantage is that the quality of the picture cannot be improved by adjusting the chamfer of the VGHM. Therefore, a power supply circuit for a TFT LCD panel gate driving circuit which does not increase the manufacturing cost and can adjust the chamfering and erasing the residual image is a problem. SUMMARY OF THE INVENTION [0] It is an object of the present invention to provide a power supply circuit for a TFT LCD panel gate driving circuit which can correct chamfering and eliminate image sticking. According to the present invention, a power supply circuit of a gate driving circuit of a TFT LCD panel includes a low voltage logic circuit for connecting a first power signal, and generating a control signal according to a voltage signal, a shutdown circuit connecting the first power signal and a first a power signal to determine a state of the power circuit to generate a shutdown signal, and a control circuit to control an output of the power circuit according to the control signal and the shutdown signal, wherein the second power signal is generated by the first power signal . The invention utilizes two power signals to make the power circuit of the gate driving circuit of the TFT LCD panel have a signal during normal operation and shutdown, so that the control circuit in the electric source circuit is correctly operated, so that the power supply circuit is executed when the shutdown is performed. The output signal is slowly lowered from the high level to the low level, which solves the problem that the conventional single power signal cannot make the control circuit operate correctly when the shutdown is performed, and the output signal of the power circuit is rapidly lowered from the high level to the low level. The phenomenon of afterimage. 7:269264 [Embodiment] FIG. 3 is a schematic diagram of a power supply circuit 300 of a TFT LCD panel gate driving circuit of the present invention. The power supply circuit 300 includes a low voltage logic circuit 310j connected to a main power signal VIN according to a voltage signal VFLK ( For example, a clock signal generated by the 1C pulse generator generates a control signal CRL1, a power supply circuit 320 connects VIN1 and a power signal VIN2 generated by v, and determines the power supply circuit 300 according to ·1 and VIN2. The state of production generates a shutdown signal Pwr〇ff, a control circuit 330 controls the output of the power supply circuit 3〇〇 according to CRL1 and PwrOff, so that an input signal v(10) (for example, a power supply signal generated by VIN1) is generated by the control circuit 33. The output signal V (3HM is supplied to the gate driving circuit of the TFT LCD. The control circuit mo includes a level shifting circuit 340 for generating control signals CRL2 and CRL3 according to CRL1 and PwrOff. A driving unit 35 controls the switches 360 and 370 according to crl2 and CRL3. Turning on or off to generate VGHM, when switch 36 is turned on, VGHM is charged to VGH, and when switch 37 is turned on, vghm is discharged to ground via a resistor 380. Figure 4 is the shutdown control of Figure 3. Referring to FIG. 3 and FIG. 4 'detecting units 322 and 324 respectively detect VIN1 and VIN2 quasi = generate (4) PG1 and PG2 to state judging unit 326, when vim is the same level day PG1 is Logic "Γ,, conversely, logic, 〇,,,, similarly, PG2 is logic "1" when 1 is \ south level, and logic "〇", otherwise 326 PG1 > PG2 t ^ 300 PG1 is far-range 1 and PG2 is logic. When 〇, ,, the power circuit goo is in the power-on state. When PG1 and PG2 are both logic "i,", the power supply is 1269264, and the road 300 is in the normal working state. When pgi is logic, 〇, and pG2 is logic 1, the power circuit 300 is in the shutdown state. When pm and pG2 are both logic "0", the power circuit 300 is in the off state, and the shutdown logic 328 is in the state. The unit 326 determines that the power-off circuit 3 is in the shutdown state, and generates the shutdown signal PwrOff. - Figure 5 is an embodiment of the power supply circuit 3 (9) of the TFT LCD panel gate drive circuit of the present invention, and a low-voltage logic circuit 31 includes a Delayer φ 540, one or gate 56〇, and a reverse gate 550, delay The 540 is connected to the VIN1 to generate a delay signal, and the delay signal is used as the input of the OR gate 56〇, the delay signal and the VFLK are used as the input of the anti-gate 55〇, and the shutdown circuit 320 is connected to the kick leg and the 乂1, according to The leg and the leg are aligned; the bit generation Pwr〇ff' control circuit 330 includes a level displacement and drive unit 510, switches 360 and 370, and a resistor 380' or gate connected between the switch 370 and the ground. The output of 560 and anti-gate 550 and pwr ff are used as the input of the displacement and drive unit sl , to generate the control signal control switches 36 〇 and 370 to open or close, VGH is connected to a capacitor 52 控制 via the control circuit After 330, VGHM is generated to the gate drive circuit 57. In the two examples, the switches 360 and 370 are the PMOS transistor and the NM 〇s transistor of the gate connection level displacement and the output of the driving unit 510, respectively. 11 6 is the timing diagram of FIG. 5 with reference to FIG. 5 and FIG. 6. When the power is turned on, 'vmi is raised from the low level to the high level. - the power-on signal PG, the power circuit 300 enters the power-on state 61〇, and then the vin2盥VGH responds. The PG gradually rises from the low level to the high level, the power circuit enters the normal working state 62〇, and the pG outputs the phase 1269264 via the delay unit 54〇.
差一延遲時間650的延遲信號PGD，使VGHM在電源穩 定後才產生，以使晝面在一開始開機即具有最佳的晝面品 質，延遲時間650大約介於20ms至100ms之間，此時才突 制電路330根據或閘560與反及閘550的輸出控制開關36〇 及370 ’在VFLK為南準位時’準位位移與驅動早元51Q • 的輸出為低準位，開關360及370分別為開啟狀態及關閉 狀態，VGHM等於VGH，在VFLK為低準時，準位位移 _ 與驅動單元510的輸出為高準位，開關360及370分別為 關閉狀態及開啟狀態，VGHM經由電阻380對地放電產生 削角660，經由改變電阻380的大小可調整削角660的下 降時間以改善TFT LCD面板晝面閃動（flicker)的情形，提 昇TFT LCD面板的晝面品質。當電源關閉時，VIN1由高 準位下降至低準位結束PG，電源電路300進入執行關機 狀悲630 ’ VIN2與VGH因應PG的結束由高準位逐漸下 降至低準位，此時低壓邏輯電路31Ό關閉，關機電路32〇 • 產生PwrOff，控制電路330根據PwrOff使開關360及37〇 分別維持在開啟狀態及關閉狀態，使VGHM與VGH的準 位相同，逐漸由高準位下降至低準位，以釋放殘留在τρτ 中的電荷消除殘影現象，當VIN1及VIN2均為低準位時， ' 電源電路300為已關機狀態640。 圖7係圖5中準位位移與驅動單元510的電路圖，準 位位移與驅動單元510包括準位位移電路710與驅動單元 750 ’準位位移電路γιο包括緩衝單元714與718以及位 移單元712與716,驅動單元750包括準位在VGH與VIN2 1269264 * 之間的反閘752以及準位在VIN2與接地端之間的反閘 754,位移單元712連接在緩衝單元714與反閘752之間， 位移單元716連接在緩衝單元718與反閘754之間，緩衝 單元714由數個準位在VIN1與接地端之間的反閘720構 成，緩衝單元718由數個準位在VIN1與接地端之間的反 . 閘722構成，位移單元712與716由數個PMOS jNMOS 電晶體構成。低壓邏輯電路的輸出CRL1經缓衝單元714 φ 及718後分別進入位移單元712及716，關機邏輯328包 括一電阻762連接在VIN2與開關764之間，關機邏輯328 根據狀悲判斷單元326的輸出產生PwrOff，PwrOff直接 輸入位移單元712及716。在本實施例中，開關764為一 閘極連接狀態判斷單元326輸出端的NMOS電晶體。在正 常工作狀態時，VIN1與VIN2均為高準位，位移單元Μ] 根據CRL1產生準位在VGH與VIN2之間的控制信號 CRL2給反閘752以控制開關360的開啟或關閉，位移單 鲁元716根據CRL1產生準位在VIN2與接地端之間的控制 b號CRL3給反閘754以控制開關370的開啟或關閉。在 執行關機狀態時，VIN1為低準位而VIN2為高準位，關機 邏輯328產生的PwrOff為高準位，位移單元712根據 ' Pwr0ff產生CRL2給反閘752強制開關360開啟，位移單 元716根據pwr0ff產生CRL3給反閘754強制開關2 關閉，使VGHM與VGH具有相同的準位。The delay signal PGD of the delay time 650 causes the VGHM to be generated after the power supply is stabilized, so that the face has the best face quality at the beginning of the start, and the delay time 650 is between 20ms and 100ms. The tapping circuit 330 controls the switches 36A and 370' according to the output of the OR gate 560 and the NAND gate 550. When the VFLK is at the south level, the output of the level shift and the driving early element 51Q are at a low level, and the switch 360 and 370 is open state and closed state respectively, VGHM is equal to VGH. When VFLK is low level, the level displacement _ and the output of the driving unit 510 are at a high level, the switches 360 and 370 are respectively in a closed state and an open state, and the VGHM is via the resistor 380. The ground discharge generates a chamfer 660. By changing the size of the resistor 380, the falling time of the chamfering angle 660 can be adjusted to improve the flicker of the TFT LCD panel, and the surface quality of the TFT LCD panel is improved. When the power is turned off, VIN1 is lowered from the high level to the low level to end PG, and the power circuit 300 enters the execution shutdown state 630 'VIN2 and VGH are gradually lowered from the high level to the low level due to the end of the PG, at this time the low voltage logic The circuit 31 is turned off, the shutdown circuit 32 〇 • generates PwrOff, and the control circuit 330 maintains the switches 360 and 37 在 in the on state and the off state according to PwrOff, so that the VGHM and the VGH are the same, and gradually decrease from the high level to the low level. Bit, in order to release the residual charge residual phenomenon in τρτ, when VIN1 and VIN2 are both low level, 'power circuit 300 is off state 640. 7 is a circuit diagram of the level shifting and driving unit 510 of FIG. 5. The level shifting and driving unit 510 includes a level shifting circuit 710 and a driving unit 750, the level shifting circuit γιο includes buffering units 714 and 718, and a displacement unit 712. 716. The driving unit 750 includes a reverse gate 752 between VGH and VIN2 1269264* and a reverse gate 754 between the VIN2 and the ground. The displacement unit 712 is connected between the buffer unit 714 and the reverse gate 752. The displacement unit 716 is connected between the buffer unit 718 and the reverse gate 754. The buffer unit 714 is composed of a plurality of reverse gates 720 between VIN1 and the ground. The buffer unit 718 is provided by a plurality of levels at VIN1 and the ground. The opposite gate 722 is formed, and the displacement units 712 and 716 are composed of a plurality of PMOS jNMOS transistors. The output CRL1 of the low voltage logic circuit enters the shift units 712 and 716 respectively after the buffer units 714 φ and 718, and the shutdown logic 328 includes a resistor 762 connected between the VIN 2 and the switch 764, and the shutdown logic 328 outputs the output according to the condition determination unit 326. PwrOff is generated, and PwrOff is directly input to the shift units 712 and 716. In the present embodiment, the switch 764 is an NMOS transistor at the output of the gate connection state determining unit 326. In the normal working state, VIN1 and VIN2 are both high level, the displacement unit Μ] according to CRL1 generates a control signal CRL2 between VGH and VIN2 to the reverse gate 752 to control the opening or closing of the switch 360, the displacement of the single Element 716 generates a control b-number CRL3 between VIN2 and ground according to CRL1 to reverse gate 754 to control the opening or closing of switch 370. When the shutdown state is performed, VIN1 is at a low level and VIN2 is at a high level, PwrOff generated by shutdown logic 328 is at a high level, and displacement unit 712 generates CRL2 according to 'Pwr0ff to force switch 752 to open switch 360, and displacement unit 716 is Pwr0ff generates CRL3 for the reverse gate 754 to force the switch 2 to close, so that VGHM has the same level as VGH.
II 1269264 【圖式簡單說明】 圖1係習知TFT LCD面板閘極驅動電路的電源電路 的不意圖， 圖2係圖1的時序圖， 圖3係本發明乏TFT LCD面板問極驅動電路的電源 電路的示意圖； 圖4係圖3中關機控制電路的示意圖； 圖5係本發明的一個實施例的示意圖； 圖6係圖5的時序圖；以及 圖7係圖5中準位位移與驅動單元的電路圖。 【主要元件符號說明】 100 電源電路 108 電容 110 延遲電路 112 或閘 114 反及閘 116 及閘 118 開關 120 開關 122 電阻 124 閘極驅動電路 150 控制電路 200 時序圖 12 1269264 210 延遲時間 220 區域 230 區域 240 削角 300 電源電路 310 低壓邏輯電路 320 關機電路BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a power supply circuit of a conventional TFT LCD panel gate driving circuit, FIG. 2 is a timing chart of FIG. 1, and FIG. 3 is a schematic diagram of a gate driving circuit of a spent TFT LCD panel of the present invention. Figure 4 is a schematic diagram of a shutdown control circuit of Figure 3; Figure 5 is a schematic diagram of one embodiment of the present invention; Figure 6 is a timing diagram of Figure 5; and Figure 7 is a level shift and drive of Figure 5. The circuit diagram of the unit. [Main component symbol description] 100 power supply circuit 108 capacitor 110 delay circuit 112 or gate 114 reverse gate 116 and gate 118 switch 120 switch 122 resistor 124 gate drive circuit 150 control circuit 200 timing diagram 12 1269264 210 delay time 220 area 230 area 240 chamfer 300 power circuit 310 low voltage logic circuit 320 shutdown circuit
322 偵測單元 324 偵測單元 326 狀態判斷單元 328 關機邏輯 330 控制電路 340 準位位移電路 350 驅動單元 360 開關 370 開關 380 電阻 510 準位位移與驅動單元 520 電容 540 延遲器 550 反及閘 560 或閘 570 間極驅動電路 600 時序圖 1269264322 detection unit 324 detection unit 326 state determination unit 328 shutdown logic 330 control circuit 340 level shift circuit 350 drive unit 360 switch 370 switch 380 resistor 510 level displacement and drive unit 520 capacitor 540 delay 550 reverse gate 560 or Gate 570 interpole drive circuit 600 timing diagram 1269264
610 執行關機狀態 620 正常工作狀態 630 執行關機狀態 640 已關機狀態 650 延遲時間 660 削角 710 準位位移電路 712 位移單元 714 緩衝單元 716 位移單元 718 緩衝單元 720 反閘 722 反閘 750 驅動單元 752 反閘 754 反閘 762 電阻 764 開關610 Execution Shutdown State 620 Normal Operation State 630 Execution Shutdown State 640 Shutdown State 650 Delay Time 660 Shaping Angle 710 Position Displacement Circuit 712 Displacement Unit 714 Buffer Unit 716 Displacement Unit 718 Buffer Unit 720 Reverse Gate 722 Reverse Gate 750 Drive Unit 752 Gate 754 reverse gate 762 resistor 764 switch