0610067ITW 20914twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種驅動裝置，立特別是有關於一種 可以解決顯示面板之潮汐現象的驅動裝置。 【先前技術】 當使用者在關閉電腦主機瞬間若不將顯示面板之背 光光源關閉而僅關閉信號及信號的電源’則顯示面板上的 顯示畫面會以很慢的速度散去。反之’在關機瞬間若同時 關閉背光光源、信號以及信號的電源，此時仍會發現顯示 面板上隱約出現如潮汐般的光影變化，這是由於顯示面板 中薄膜電晶體成膜時因膜厚不均，導致各畫素電晶體放電 速度不同而產生的潮沙現象(Fan_out)。更詳細的說，當關 上電源瞬間’因薄膜電晶體膜厚不同造成電容不同，所需 的放電時間也不相同，因此液晶旋轉回復的時間亦不同， 故在面板上出現如海潮退潮般殘影晝面。 因此’為了解決上述的潮汐現象，有些顯示面板的設 計廠商便針對此問題提供了一些解決方案，如圖1與圖2 所不。圖1為習知之閘極驅動器的架構方塊圖，圖2為習 知之閘極ϋ動ϋ的信號時序圖。請依照說明之需要而參照 圖1與圖2。 先請參照圖1。圖1中包含輸入緩衝器101、移位 暫存器1G2:位準移位器1G3、輸出緩衝器1G4、重置電路 105。輸入緩衝器1〇1用以缓衝時脈信號cpv、啟始信號 STV、輸出致能信號OE、以及全輸出魏信M；Xon。移位 0610067ITW 20914twf.doc/n 0610067ITW 20914twf.doc/n 暫存器102 移位信號，BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device, and more particularly to a driving device capable of solving the tidal phenomenon of a display panel. [Prior Art] When the user turns off the host computer and turns off the power of the signal and signal only if the backlight of the display panel is turned off, the display on the display panel will be dissipated at a very slow speed. Conversely, if the backlight source, signal, and signal power are turned off at the same time, the light and shadow changes such as tidal light will appear on the display panel. This is due to the film thickness of the thin film transistor in the display panel. Both of them cause the tidal sand phenomenon (Fan_out) caused by the different discharge speeds of the respective pixel transistors. In more detail, when the power is turned off instantaneously, the capacitance varies depending on the film thickness of the thin film transistor, and the required discharge time is also different. Therefore, the time for the liquid crystal to rotate and revert is different, so that the image appears on the panel like the tide of the tide. Picture. Therefore, in order to solve the above-mentioned tidal phenomenon, some display panel manufacturers have provided some solutions to this problem, as shown in Figure 1 and Figure 2. 1 is an architectural block diagram of a conventional gate driver, and FIG. 2 is a signal timing diagram of a conventional gate ϋ. Please refer to Figure 1 and Figure 2 as required. Please refer to Figure 1 first. 1 includes an input buffer 101, a shift register 1G2: a level shifter 1G3, an output buffer 1G4, and a reset circuit 105. The input buffer 101 is used to buffer the clock signal cpv, the start signal STV, the output enable signal OE, and the full output Weixin M; Xon. Shift 0610067ITW 20914twf.doc/n 0610067ITW 20914twf.doc/n register 102 shift signal,
< ζυι所不）而使n個輸出信號同時被產生， 镜Χοη(如圖2 ，進一步地使 閘極驅動器同時輸出Ν個輸出信號〇ut1〜〇utn]、〇utn (如圖2之202所示），以同時驅動顯示面板之間極線 G1〜GN。如此-來’便可解決_示面板中的各晝素電晶 體放電速度不同而產生的潮汐現象。 然而，由於全輸出致能信號χ〇η必須仰賴顯示面板之 印刷電路板(Printed Circuit Board，簡稱pCB)上的重置電路 105所控制，而重置電路105為採用現成的重置晶片（Reset 1C)。因此，若採取圖1所示的習知架構來解決潮汐現象， 不僅得額外採用重置晶片於印刷電路板上，造成製造成本 的負擔，且也必須針對此重置晶片而進行額外的印刷電路 板佈線，使得設計與製造顯示面板顯得耗時費工，這對於 所有欲降低製造成本進而提高產品獲利的顯示面板廠商來 說，是相當不利的。 【發明内容】 1351661 0610067ITW 20914twf.doc/n —本發明的目的就是提供—種驅動裝置，其不 示面板之印刷電路板上採用重置晶片便可解決顯板之 潮汐現象。 田珉之 基於上述及其他目的’本發明提出一種驅 用於驅動包含多條_線之顯示面板，此 動單元與電壓偵測單元。其中驅動單元用以產;= U ’以豬由上述輸出信號驅動上述閘極線。電壓 連Ϊ至驅動單元，並依據驅動單元之邏輯驅動電屢 信號。_偵測單元輸出控制信號至驅 ’以使驅動單元依據控制信號而同時產生上述輸出 位暫:t本發:Λ—气施例所述，上述之驅動單元包括移 輸出致^$4暫存單痛以接岐始信號、時脈信號、 ίί 、以及控制信號。移位暫存單元依據啟始信 出^2 Li生多個移位信號’並依據輸出致能信號輸 形成上述輸出信號。移位暫存單元亦 依據控制信號而同時產生上述輸出信號。 括銘ΓΓί發明的一實施例所述’上述之移位暫存單元包 啟與邏輯控制電路。其中移位暫存器用以接收 號及時脈信號，並據以產生上述之多個移位信 =，田二制電路電性連接至移位暫存器與電塵镇測單 制n以接收輪出致能信號、上述多個移位信號、以及控 遗。邏輯控制電路依據輸出致能信號輸出上述之多個 1351661 • 0610067ITW 209l4twf.doc/n 移位k號’以形成上述輸出信號’且邏輯控制電路亦依據 控制k號而同時產生上述輸出信號。 依照本發明的一實施例所述，上述之電壓偵測單元包 括比較電路與選擇電路。其中比較電路電性連接至驅動單 元之邏輯驅動電壓與參考電壓，用以比較上述邏輯驅動電 壓與參考電壓之值，並據以輸出比較信號。選擇電路電性 連接於驅動單元之邏輯驅動電壓與接地電壓之間，用以依 據比較號而決定輸出驅動單元之邏輯驅動電壓與接地電 壓其中之一。 依照本發明的一實施例所述，上述之選擇電路包括第 一電晶體與第二電晶體，其中第一電晶體為PM〇S電晶體 (P-type metal-oxide-semiconductor transistor)，第二電晶體 為 NMOS 電晶體（N-type metal-oxide-semiconductor ' transistor)。而上述之比較電路包括比較器，比較器具有正 輸入端、負輸入端、以及輸出端。其中，第一電晶體之間 極接收比較倌號，而第一電晶體之其中一源/及極電性連接 • 至驅動單元之邏輯驅動電壓。第二電晶體之閘極亦接收比 較信號，而第二電晶體之其中一源/汲極電性連接至第一電 晶體之另一源/没極，第二電晶體之另一源/没極電性連接 至接地電壓。而比較器之負輸入端電性連接至驅動單元之 邏輯驅動電壓，比較器之正輸入端電性連接至參考電壓， 而比較器之輸出端電性連接至第一電晶體與第二電晶體之 閘極。 g 0610067ITW 20914twf.doc/n 依照本發明的一實施例所述’上述之邏輯控制電路包 括多個及閘與多個或閘。其中每一及閘之其中一輸入端接 收輸出致能信號之反相信號’每一及閘之另一輸入端對應 地接收上述之多個移位信號其中之一，而每一或閘之其中 一輸入端接收控制信號之反相信號，每一或閘之另一輸入 端對應地接收上述及閘其中之一的輸出端，而上述或閘之 輸出端輸出上述之輸出信號。 本發明因在驅動裝置中採用電壓偵測單元，並利用電 壓偵測單元比較預設的參考電塵與驅動單元之邏輯驅動電 壓的值而產生控制信號，且在關機時使電壓偵測單元輸出 控制信號至驅動裝置中的移位暫存單元，使移位暫存單元 同時輸出多個輸出信號，進而同時驅動顯示面板之閘極 線，以解決因顯示面板中的各晝素電晶體放電速度不同而 產生的潮汐現象。 因此，本發明不僅不需要額外採用重置晶片於印刷電 路板上，減少製造成本的負擔，且也不必針對重置晶片而 填行額外的印刷電路板佈線，簡化t設計與製造顯示面板 的流程。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易僅，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖3為依照本發明一實施例之驅動裝置的架構方塊 圖。請參照圖3。圖3所示之驅動裝置包括驅動單元3〇1 1351661 〇610067ITW 20914twf.doc/n 與電壓偵測單元302。在此實施例中，驅動單元3〇1接收 外來的電壓，以作為驅動單元301之邏輯驅動電虔 VDDD。上述的驅動單元3〇1用以產生N個輸出信號，分 • 別為〇UT1〜0UTN，以藉由上述輸出信號OUT1〜OUTN驅 動顯示面板的閘極線G1〜GN(圖中未顯示）。 電壓偵測單元302電性連接至驅動單元3〇1，並依據 驅動單元301之邏輯驅動電壓vddD的位準而產生控制信 φ 號CS ’且電壓偵測單元302輸出控制信號cs至驅動單元< ζυι does not) and so that n output signals are simultaneously generated, mirror Χ η (Figure 2, further enable the gate driver to simultaneously output one output signal 〇ut1 ~ 〇utn], 〇utn (Figure 2 202 (shown)) to drive the polar lines G1 GN between the display panels at the same time. This can solve the tidal phenomenon caused by the different discharge speeds of the individual halogen transistors in the panel. However, due to the full output enable The signal χ〇η must be controlled by the reset circuit 105 on the Printed Circuit Board (pCB) of the display panel, and the reset circuit 105 is a ready-made reset chip (Reset 1C). The conventional architecture shown in FIG. 1 solves the tidal phenomenon, which not only requires additional resetting of the wafer on the printed circuit board, but also imposes a manufacturing cost burden, and additional printed circuit board wiring must be performed for the reset wafer. Designing and manufacturing display panels is time consuming and labor intensive, which is quite disadvantageous for all display panel manufacturers who want to reduce manufacturing costs and thereby increase product profitability. [Summary of the Invention] 1351661 06100 67ITW 20914twf.doc/n - The object of the present invention is to provide a driving device which can solve the tidal phenomenon of the display panel by using a reset wafer on a printed circuit board of a panel. The field is based on the above and other purposes. The invention provides a display panel for driving a display panel comprising a plurality of _ lines, the dynamic unit and the voltage detecting unit, wherein the driving unit is configured to produce; = U ' to drive the gate line by the pig output signal. To the driving unit, and according to the logic of the driving unit, the electric signal is driven. The detecting unit outputs a control signal to the drive to enable the driving unit to simultaneously generate the output bit according to the control signal: t: Λ—Gas As described above, the driving unit includes a shift output to generate a temporary pain to connect the start signal, the clock signal, the ίί, and the control signal. The shift register unit generates a plurality of shift signals according to the start signal. And forming the output signal according to the output enable signal. The shift register unit also generates the output signal according to the control signal. The invention is described in an embodiment of the invention. The shift register unit is started with a logic control circuit, wherein the shift register is configured to receive the number and time pulse signals, and accordingly generate the plurality of shift signals=, and the second circuit is electrically connected to the shift register. And the electric dust metering system n to receive the wheeling enable signal, the plurality of shift signals, and the control. The logic control circuit outputs the plurality of 1351661 • 0610067ITW 209l4twf.doc/n according to the output enable signal The voltage detection unit includes a comparison circuit and a selection circuit according to an embodiment of the invention. The comparison circuit is electrically connected to the logic driving voltage of the driving unit and the reference voltage for comparing the values of the logic driving voltage and the reference voltage, and outputting the comparison signal accordingly. The selection circuit is electrically connected between the logic driving voltage of the driving unit and the ground voltage, and is used for determining one of the logic driving voltage and the ground voltage of the output driving unit according to the comparison number. According to an embodiment of the invention, the selection circuit includes a first transistor and a second transistor, wherein the first transistor is a P-type metal-oxide-semiconductor transistor, and the second The transistor is an N-type metal-oxide-semiconductor ' transistor. The comparison circuit described above includes a comparator having a positive input, a negative input, and an output. Wherein, the first transistor receives a comparative nickname, and one of the first transistor is electrically connected to the logic driving voltage of the driving unit. The gate of the second transistor also receives the comparison signal, and one of the source/drain of the second transistor is electrically connected to the other source/nopole of the first transistor, and the other source of the second transistor is Very electrically connected to the ground voltage. The negative input terminal of the comparator is electrically connected to the logic driving voltage of the driving unit, the positive input end of the comparator is electrically connected to the reference voltage, and the output end of the comparator is electrically connected to the first transistor and the second transistor. The gate. g 0610067ITW 20914twf.doc/n In accordance with an embodiment of the invention, the logic control circuit described above includes a plurality of gates and a plurality of gates. One of the input terminals of each of the gates receives an inverted signal of the output enable signal 'each of the other input terminals of the gate correspondingly receives one of the plurality of shift signals, and each of the gates An input terminal receives the inverted signal of the control signal, and the other input terminal of each OR gate correspondingly receives the output end of one of the gates, and the output terminal of the OR gate outputs the output signal. The invention adopts a voltage detecting unit in the driving device, and uses the voltage detecting unit to compare the preset reference electric dust with the value of the logic driving voltage of the driving unit to generate a control signal, and causes the voltage detecting unit to output when the power is turned off. The control signal is sent to the shift temporary storage unit in the driving device, so that the shift temporary storage unit simultaneously outputs a plurality of output signals, thereby simultaneously driving the gate line of the display panel to solve the discharge speed of each halogen crystal in the display panel Different tides. Therefore, the present invention not only does not require additional resetting of the wafer on the printed circuit board, but also reduces the burden of manufacturing costs, and does not have to fill in additional printed circuit board wiring for resetting the wafer, simplifying the process of designing and manufacturing the display panel. . The above and other objects, features, and advantages of the present invention will be apparent from the description of the appended claims. [Embodiment] FIG. 3 is a block diagram showing the architecture of a driving apparatus according to an embodiment of the present invention. Please refer to Figure 3. The driving device shown in FIG. 3 includes a driving unit 3〇1 1351661 〇610067ITW 20914twf.doc/n and a voltage detecting unit 302. In this embodiment, the driving unit 301 receives an external voltage as the logic driving power VDDD of the driving unit 301. The driving unit 〇1 is configured to generate N output signals, which are 〇UT1 〜OUTN, to drive the gate lines G1 GN (not shown) of the display panel by the output signals OUT1 OUTOUTN. The voltage detecting unit 302 is electrically connected to the driving unit 〇1, and generates a control signal φ number CS ’ according to the level of the logic driving voltage vddD of the driving unit 301, and the voltage detecting unit 302 outputs the control signal cs to the driving unit.
301，以使驅動單元301依據控制信號cs而同時產生輸出 信號OUT1〜OUTN。當驅動單元3〇1同時產生輸出信號 OUT1〜OUTN，進而同時驅動顯示面板的閘極線G1~GN 時，便可解決因顯示面板中的各晝素電晶體放電速度不同 而產生的潮汐現象。 在此實施例中，驅動單元3〇1包括輸入緩衝器3〇3、 移位暫存單元304、位準移位器3〇5、以及輸出緩衝器3〇6。 然而，由於各廠商對於驅動單元3〇1的設計並無一定，故 ♦上述之驅動單元301中所包括的各元件不應侷限於此實施 例。輸入緩衝器303電性連接至移位暫存單元3〇4，用以 接收並緩衝啟始信號STV、時脈信號CPV、以及輸出致能 信號OE。移位暫存單元304用以接收透過輸入緩衝器3〇3 做信號緩衝的啟始信號STV、時脈信號CPV、以及輸出致 能信號OE，並且移位暫存單元3〇4亦接收電壓偵 302所產生的控制信號CS» ' 1351661 0610067ITW 20914twf.d〇c/n 元3〇4依據時脈信號CPV與啟始信號 產生N個移位信號’然後再依據輸出致能信號沉 ^上述之N個移位信號，以形❹個輸出信號。位 位器305接收並位移上述N個輸出信號之信號位準， =透過輸出缓衝器306將上述位移過信號位準之N個輸出 信號做信賴衝而輸出，分職⑽卜^㈣，以依 ，顯示面板之閘極線⑴〜⑽(圖中未顯示）。Μ，移位暫 綱亦依據控制信號^而同時產生上述之Ν個輸 移位暫存單it 3〇4包括移位暫存器3〇7與邏輯控 路308。移位暫存器3〇7用以接收啟始信號聊以及時脈 ί產生上述ί多個移健號。邏輯控制電 連接至移位暫存器307與電壓偵測單元3〇2， =，出致能信號0Ε、上述之Ν個移位信號、以及 f制k就cs。邏輯控制電路308依據輸出致能信號〇ε輸 上述之Ν個移位信號，以形成上述個輸出信號。邏 輯控制電路308亦用以依據控制信號cs 之N個輸出信號。 座生上边 圖4為依照本發明一實施例之電壓偵測單元的電路 圖。請參照圖4。圖4所示即為圖3之電壓_單元3〇2 的内部電路’其包括比較電路4G1與選擇電路4G2。其中 比較電路401電性連接至驅動單元之邏輯驅動電墨vddd 與參考電壓VTH，用以比較上述邏輯驅動電麗Vddd與 參考電壓VTH之值，並據以輸出比較信號ps。選擇電^ 1351661 0610067ITW 20914twf.doc/n 402電性連接於驅動單元3〇1之邏輯驅動電壓VDDD與接 地電壓GND之間，用以依據比較信號PS而決定輸出驅動 單元之邏輯驅動電壓VDDD與接地電壓GND其中之一。 在此實施例中，比較電路401以比較器403來實現， 而選擇電路402以電晶體404與電晶體405來實現，其中 電晶體404為PMOS電晶體，而電晶體405為NMOS電 晶體。 比較器403具有正輸入端、負輸入端、以及輸出端。 比較器403之負輸入端電性連接驅動單元之邏輯驅動電壓 VDDD ’比較器403之正輸入端電性連接參考電壓vth， 而比較器之輸出端電性連接電晶體404與電晶體405之閘 極。電晶體404之閘極接收比較信號ps，而電晶體404之 源極電性連接驅動單元之邏輯驅動電壓VDDD。電晶體 405之閘極接收比較信號PS，電晶體4〇5之汲極電性連接 電晶體404之>及極，而電晶體405之源極電性連接接地電 廢 GND。 然而，使用者當可依照實際上之需要而變更比較電路 401及/或選擇電路402内部的設計，上述所列舉的實現方 式並非用以限定比較電路401與選擇電路402内部的設計 方式。 當比較器403所接收的邏輯驅動電壓VDDD小於參考 電壓VTH時’比較器403所輪出之比較信號ps為高邏輯， 使得電晶體404截止、電晶體405導通，因此電壓偵測單 元302所輸出的控制信號cs為接地電壓GND(亦即低邏 12 1351661 0610067ITW 20914twf.doc/n 輯）。當比較裔403所接收的邏輯驅動電壓vddd大於灸 考電壓VTH時’比較器403所輪出之比較信號ps為低^ 輯，使得電晶體404導通、電晶體4〇5截止，因此電壓= 測單元302所輸出的控制信號cS為邏輯驅動電壓 VDDD(亦即高邏輯）。因此，電壓偵測單元3〇2是以比 邏輯驅動電壓VDDD與參考電壓VTH之值來決定控制^ 號CS為高邏輯或是低邏輯，使得圖3所示之驅動單元 可以依據控制信號CS之信號狀態而同時產生輸出信號 OUT1 〜OUTN。 。~ 請依照說明之需要而參照圖3與圖5。圖5為依照本 發明一實施例之驅動裝置的内部電路圖。請參照圖5，圖5 所示之輸入緩衝器501、移位暫存器502、邏輯控制電路 503、以及電壓偵測單元505即分別為圖3所示之輸入緩衝 器303、移位暫存器307、邏輯控制電路3〇8、以及電壓债 測單元302，而圖5所示之位準移位器與輸出緩衝器5〇4 即為圖3所示之位準移位器305與輸出緩衝器306之結合。 圖5所示之電壓债測早元505為採用圖4所示之電壓 偵測單元的設計方式，而圖5之邏輯控制電路503所示即 為圖3之邏輯控制電路308之内部電路的實際設計方式。 其中邏輯控制電路503包括Ν個及閘507、Ν個或閘508、 反相器509與510。每一及閘507之其申一輸入端接收輸 出致能信號ΟΕ之反相信號/〇Ε，每一及閘507之另一輸入 端對應地接收移位信號Q1〜QN其中之一。而每一或閘508 之其中一輸入端接收控制信號CS之反相信號/CS，每一或 13 0610067ITW 20914twf.doc/n 閘508之另一輸入端對應地接收該些及閘5〇7其中之一的 輸出端，該些或閘508之輸出端輸出信號ρι〜ΡΝ。 然而在圖5所示之實施例中，電壓偵測單元5〇5並非 限於採用圖4所示之電壓偵測單元的設計方式。另外，在 一般的驅動裝置中皆會設計邏輯控制電路，以進行驅動裝 置中之信號的邏輯運算，然而由於各廠商對於邏輯控制電 路的設計方式也不一樣，因此圖5之邏輯控制電路5〇3所 示之電路架構亦並非用以限定邏輯控制電路之内部電路的 設計方式。 請依照說明之需要而參照圖4與圖5。請先參照圖4。 當顯示面板於正常操作時，此時邏輯驅動電壓VDDD大於 參考電壓VTH，因此控制信號CS為高邏輯。請參照圖5。 在上述之情況下，電壓偵測單元5 05所輸出之控制信號C S 經過反相器510反相成其反相信號/cs(即低邏輯），因此邏 輯控制電路503中之N個或閘508便依據N個及閘507 所輸出之彳吕號K1〜KN而操作，進而使驅動裝置正常地依 序輸出輸出信號OUT1〜OUTN，以依序驅動顯示面板之閘 極線G1〜GN(圖中未顯示）。 請再參照圖4。當顯示面板於關機瞬間時，電壓偵測 單疋505會去偵測邏輯驅動電壓VDDD，當邏輯驅動電壓 VDDD小於參考電壓vTH，其控制信號cS為低邏輯。圖 6為依照本發明一實施例之驅動裝置之部分内部信號的時 序圖。請參照圖5與圖6。在上述之情況下，圖5之電壓 價測單元505所輪出之控制信號CS(為低邏輯，如圖6之 1351661 〇610067ITW20914twf.doc/n 6。01所示)經過反相器51〇反相成其反相信號/cs(即高邏 輯，如圖6之602所示），因此邏輯控制電路5〇3中之n ，或閘508便依據高邏輯之反相信號/cs而同時輸出高邏 輯的輸出信號P1〜PN，如圖6中之603所列舉的pi與p2 ，示，其中圖6之P1與P2為對應於圖5之ρι與p2的信 號狀態 圖5之位準移位器與輸出缓衝器504中的位準移位器 用以接收並位移上述N個輸出信號ρι〜ρΝ之信號位準°， 然後再透過位準移位器與輸出緩衝器5〇4中的輸出緩衝 ，上,移過信號位準之之N個輸出信號做信號緩衝而輸 蚩Μ日未 來，便可解決因顯示面板中 的各晝^晶體放電速度㈣而產生的·現象。 一 提的是’雖然在上述實施例中已經對電壓伽 路之内部電路的設計方式崎出了二 單元盘邏^=知此技術者應知，各廠商對於電壓偵測 庳用二2控制電路的設計方式都不一樣，因此本發明之 於此種可能的型態。換言之，只要是利用預 :生控制信與元:邏輯驅賴的值相互比較而 而同時驅動^^使_裝置同時產生所有的輸出信號 精神所在 面板之閉極線，就已經是符合了本發明的 15 1351661 0610067ITW 20914twf.doc/n 元 综上所述’本發明因在_裝置情用電壓偵 ’並利用電壓_單元比較預設的參考電壓與驅動 ^邏^驅動電壓的值而產生控制信號，且在_時使電壓 偵測早元輸出控制信號至驅動裝置中的移位 移位暫存單元同時輸衫赌出信號，進而同時 面板之閘極線’崎決因顯示面板t的各晝素電晶體放電 速度不同而產生的潮汐現象。301, so that the driving unit 301 simultaneously generates the output signals OUT1 to OUTN according to the control signal cs. When the driving unit 3〇1 simultaneously generates the output signals OUT1 to OUTN and simultaneously drives the gate lines G1 to GN of the display panel, the tidal phenomenon caused by the different discharge speeds of the respective pixel transistors in the display panel can be solved. In this embodiment, the drive unit 〇1 includes an input buffer 〇3, a shift register unit 304, a level shifter 〇5, and an output buffer 〇6. However, since each manufacturer does not have a certain design for the driving unit 313, the components included in the above-described driving unit 301 should not be limited to this embodiment. The input buffer 303 is electrically coupled to the shift register unit 〇4 for receiving and buffering the start signal STV, the clock signal CPV, and the output enable signal OE. The shift register unit 304 is configured to receive the start signal STV, the clock signal CPV, and the output enable signal OE that are buffered by the input buffer 3〇3, and the shift register unit 3〇4 also receives the voltage detect 302 generated control signal CS» ' 1351661 0610067ITW 20914twf.d〇c / n element 3 〇 4 according to the clock signal CPV and the start signal to generate N shift signals 'and then according to the output enable signal sink ^ N above Shift signals to shape an output signal. The positioner 305 receives and shifts the signal level of the N output signals, and outputs the N output signals of the above-mentioned shifted signal level through the output buffer 306, and divides the output by (10) bu (4). According to the display panel, the gate lines (1) ~ (10) (not shown). In other words, the shifting program also generates the above-mentioned one of the shifts according to the control signal ^, and the shift register 3 〇4 includes the shift register 3〇7 and the logic control 308. The shift register 3〇7 is configured to receive the start signal chat and the clock to generate the above plurality of health care numbers. The logic control is electrically connected to the shift register 307 and the voltage detecting unit 3〇2, =, the enable signal 0Ε, the above-mentioned one shift signal, and the f system k to cs. The logic control circuit 308 inputs the above ones of the shift signals according to the output enable signal 〇 ε to form the above-mentioned output signals. The logic control circuit 308 is also operative to rely on the N output signals of the control signal cs. Figure 4 is a circuit diagram of a voltage detecting unit in accordance with an embodiment of the present invention. Please refer to Figure 4. Fig. 4 shows an internal circuit of the voltage_unit 3〇2 of Fig. 3, which includes a comparison circuit 4G1 and a selection circuit 4G2. The comparison circuit 401 is electrically connected to the logic driving ink vddd of the driving unit and the reference voltage VTH for comparing the values of the logic driving voltage Vddd and the reference voltage VTH, and outputting the comparison signal ps accordingly. Selecting a voltage ^ 1351661 0610067ITW 20914twf.doc / n 402 is electrically connected between the logic driving voltage VDDD of the driving unit 3〇1 and the ground voltage GND for determining the logic driving voltage VDDD of the output driving unit and the ground according to the comparison signal PS One of the voltages GND. In this embodiment, the comparison circuit 401 is implemented as a comparator 403, and the selection circuit 402 is implemented as a transistor 404 and a transistor 405, wherein the transistor 404 is a PMOS transistor and the transistor 405 is an NMOS transistor. Comparator 403 has a positive input, a negative input, and an output. The negative input terminal of the comparator 403 is electrically connected to the logic driving voltage VDDD of the driving unit. The positive input terminal of the comparator 403 is electrically connected to the reference voltage vth, and the output terminal of the comparator is electrically connected to the gate of the transistor 404 and the transistor 405. pole. The gate of the transistor 404 receives the comparison signal ps, and the source of the transistor 404 is electrically coupled to the logic driving voltage VDDD of the driving unit. The gate of the transistor 405 receives the comparison signal PS, the gate of the transistor 4〇5 is electrically connected to the > and the pole of the transistor 404, and the source of the transistor 405 is electrically connected to the grounding capacitor GND. However, the user may change the design of the internals of the comparison circuit 401 and/or the selection circuit 402 as needed, and the above-described implementations are not intended to define the design of the internals of the comparison circuit 401 and the selection circuit 402. When the logic driving voltage VDDD received by the comparator 403 is less than the reference voltage VTH, the comparison signal ps rotated by the comparator 403 is high logic, so that the transistor 404 is turned off and the transistor 405 is turned on, so the voltage detecting unit 302 outputs The control signal cs is the ground voltage GND (ie, low logic 12 1351661 0610067ITW 20914twf.doc/n series). When the logical driving voltage vddd received by the comparator 403 is greater than the moxibustion voltage VTH, the comparison signal ps rotated by the comparator 403 is low, so that the transistor 404 is turned on and the transistor 4〇5 is turned off, so the voltage = measured The control signal cS output by unit 302 is a logic drive voltage VDDD (ie, high logic). Therefore, the voltage detecting unit 3〇2 determines whether the control unit CS is high logic or low logic by the ratio of the logic driving voltage VDDD and the reference voltage VTH, so that the driving unit shown in FIG. 3 can be based on the control signal CS. The signal state simultaneously produces output signals OUT1 to OUTN. . ~ Please refer to Figure 3 and Figure 5 as required. Fig. 5 is an internal circuit diagram of a driving device in accordance with an embodiment of the present invention. Referring to FIG. 5, the input buffer 501, the shift register 502, the logic control circuit 503, and the voltage detecting unit 505 shown in FIG. 5 are respectively the input buffer 303 and the shift register shown in FIG. The controller 307, the logic control circuit 3〇8, and the voltage debt measuring unit 302, and the level shifter and output buffer 5〇4 shown in FIG. 5 are the level shifter 305 and output shown in FIG. A combination of buffers 306. The voltage debt measurement early element 505 shown in FIG. 5 is designed using the voltage detecting unit shown in FIG. 4, and the logic control circuit 503 of FIG. 5 is the actual internal circuit of the logic control circuit 308 of FIG. Design method. The logic control circuit 503 includes a plurality of gates 507, a gate or gate 508, and inverters 509 and 510. Each of the input terminals of each gate 507 receives an inverted signal /〇Ε of the output enable signal, and the other input of each gate 507 receives one of the shift signals Q1 QQN correspondingly. And one of the inputs of each of the OR gates 508 receives the inverted signal /CS of the control signal CS, and the other input of each of the 16 0610067ITW 20914twf.doc/n gates 508 correspondingly receives the gates 5〇7 At one of the outputs, the outputs of the OR gates 508 output signals ρι~ΡΝ. However, in the embodiment shown in FIG. 5, the voltage detecting unit 5〇5 is not limited to the design of the voltage detecting unit shown in FIG. In addition, in a general driving device, a logic control circuit is designed to perform a logic operation of a signal in the driving device. However, since each manufacturer designs a logic control circuit differently, the logic control circuit of FIG. 5〇 The circuit architecture shown in Figure 3 is also not intended to define the internal circuitry of the logic control circuit. Please refer to FIG. 4 and FIG. 5 as needed for the description. Please refer to Figure 4 first. When the display panel is in normal operation, the logic driving voltage VDDD is greater than the reference voltage VTH at this time, and thus the control signal CS is high logic. Please refer to Figure 5. In the above case, the control signal CS outputted by the voltage detecting unit 505 is inverted by the inverter 510 to its inverted signal /cs (ie, low logic), so N or gates 508 in the logic control circuit 503. Then, according to the N and K1 to KN outputted by the gate 507, the driving device normally outputs the output signals OUT1 to OUTN in order to sequentially drive the gate lines G1 to GN of the display panel (in the figure). Not shown). Please refer to Figure 4 again. When the display panel is turned off, the voltage detection unit 505 will detect the logic driving voltage VDDD. When the logic driving voltage VDDD is smaller than the reference voltage vTH, the control signal cS is low logic. Figure 6 is a timing diagram of a portion of internal signals of a drive device in accordance with an embodiment of the present invention. Please refer to FIG. 5 and FIG. 6. In the above case, the control signal CS (which is low logic, as shown in FIG. 6 of 13561671 〇610067ITW20914twf.doc/n 6.01) rotated by the voltage price measuring unit 505 of FIG. 5 is inverted by the inverter 51. Forming its inverted signal /cs (ie high logic, as shown in 602 of Figure 6), so the n of the logic control circuit 5〇3, or the gate 508 is simultaneously output high according to the high logic inverted signal /cs The logical output signals P1 PN PN are shown as pi and p2 listed in 603 of FIG. 6 , wherein P1 and P2 of FIG. 6 are signal states corresponding to ρι and p2 of FIG. 5 and the level shifter of FIG. And a level shifter in the output buffer 504 for receiving and shifting the signal level of the N output signals ρι~ρΝ, and then passing the output buffer in the level shifter and the output buffer 5〇4 The N output signals shifted over the signal level are used as signal buffers for future transmission, and the phenomenon caused by the discharge speed (4) of each crystal in the display panel can be solved. It is mentioned that although the design method of the internal circuit of the voltage gamma has been found in the above embodiment, the two-unit disk logic is known. It is known to those skilled in the art that each manufacturer uses the two-control circuit for voltage detection. The design is different, so the present invention is in this possible form. In other words, as long as the front-end control line and the element: the value of the logical drive are compared with each other while driving the device to simultaneously generate the closed-circuit line of all the output signal spirits, it is in accordance with the present invention. 15 1351661 0610067ITW 20914twf.doc/n In summary, the present invention generates a control signal by comparing the preset reference voltage with the value of the driving voltage of the driving voltage by using the voltage_cell to compare the preset reference voltage with the voltage_unit. And at the time of _, the voltage detection early output control signal is sent to the shift shift temporary storage unit in the driving device to simultaneously sing the gambling signal, and at the same time, the gate line of the panel is determined by the display panel t. The tidal phenomenon caused by the different discharge speed of the crystal.
因此，本發明不僅不需要額外採用重置晶片於印刷電 路板上，減少製造成本的負擔，且也不必針對重置晶片而 進行額外的印難路㈣線，簡化了設計與製造顯示面板 的流程。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在*麟本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】Therefore, the present invention not only does not require additional resetting of the wafer on the printed circuit board, but also reduces the burden of manufacturing costs, and does not require additional printing (four) lines for resetting the wafer, simplifying the process of designing and manufacturing the display panel. . Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and it is obvious to those skilled in the art that the present invention can be modified and retouched within the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. [Simple description of the map]
圖1為習知之閘極驅動器的架構方塊圖。 圖2為習知之閘極驅動器的信號時序圖。 圖3為依照本發明一實施例之驅動裝置的架構方塊 圖。 圖4為依照本發明一實施例之電壓偵測單元的 圖。 圖5為依照本發明一實施例之驅動裝置的内部電路 圖0 16 1351661 0610067ITW 20914twf.doc/n 圖6為依照本發明一實施例之驅動裝置之部分内部信 號的時序圖。 【主要元件符號說明】 101、303、501 :輸入緩衝器 102 :移位暫存器 103、 305 :位準移位器 104、 306 :輸出緩衝器 105 :重置電路 201、202、601、602、603 :信號之狀態 301 :驅動單元 302、505 :電壓偵測單元 304 :移位暫存單元 307、 502 :移位暫存器 308、 503 :邏輯控制電路 401 ： 比較電路 402 ： 選擇電路 403 ： 比較器 404、 405 :電晶體 504 : 位準移位器與輸出緩衝器 507 ： 及閘 508 ： 或閘 509、 510 :反相器 CPV :時脈信號 CS :控制信號 17 1351661 0610067ITW 20914twf.doc/n GND :接地電壓 K1〜KN :及閘之輸出信號 0E :輸出致能信號 0UT1〜OUTN-卜OUTN :輸出信號 PS :比較信號 P1〜PN :或閘之輸出信號 Q1〜QN :移位信號 STV :啟始信號 VDDD :邏輯驅動電壓 VTH :參考電壓 Χοη :全輸出致能信號 /CS :控制信號之反相信號 /ΟΕ :輸出致能信號之反相信號1 is a block diagram of the architecture of a conventional gate driver. 2 is a signal timing diagram of a conventional gate driver. Fig. 3 is a block diagram showing the architecture of a driving apparatus in accordance with an embodiment of the present invention. 4 is a diagram of a voltage detecting unit in accordance with an embodiment of the present invention. Figure 5 is a diagram showing the internal circuit of a driving device in accordance with an embodiment of the present invention. Figure 16 is a timing diagram of a portion of internal signals of a driving device in accordance with an embodiment of the present invention. [Main component symbol description] 101, 303, 501: input buffer 102: shift register 103, 305: level shifter 104, 306: output buffer 105: reset circuit 201, 202, 601, 602 603: Signal state 301: drive unit 302, 505: voltage detecting unit 304: shift register unit 307, 502: shift register 308, 503: logic control circuit 401: comparison circuit 402: selection circuit 403 : Comparator 404, 405: Transistor 504: Level shifter and output buffer 507: AND gate 508: or gate 509, 510: Inverter CPV: Clock signal CS: Control signal 17 1351661 0610067ITW 20914twf.doc /n GND : Ground voltage K1 ~ KN : and gate output signal 0E : Output enable signal OUT1 ~ OUTN - BU OUTN : Output signal PS : Comparison signal P1 ~ PN : or gate output signal Q1 ~ QN : Shift signal STV: Start signal VDDD: Logic drive voltage VTH: Reference voltage Χοη: Full output enable signal /CS: Inverted signal of control signal / ΟΕ : Inverted signal of output enable signal