TW200822011A - Driving apparatus - Google Patents

Abstract

A driving apparatus suitable for drives a display panel which includes a plurality of gate lines is provided. The driving apparatus includes a driving unit and a voltage detecting unit. Wherein the driving unit is used to generate a plurality of output signal, so as to drives those gate lines. The voltage detecting unit is coupled to the driving unit, and the voltage detecting unit generates a controlling signal according to a logic driving voltage of the driving unit. The voltage detecting unit outputs the controlling signal to the driving unit, so as to make the driving unit generates the plurality of output signal simultaneously according to the controlling signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device, and more particularly to a driving device that can solve the tidal phenomenon of a display panel. [Prior Art] ί When the user turns off the host computer and turns off the power of the signal and signal without turning off the backlight of the display panel, the display surface on the display panel will be dissipated at a very slow speed. Conversely, if the moonlight source, 彳§, and signal power are turned off at the same time, the glare-like light and shadow changes will still appear on the display panel due to the thin film formation in the display panel. Uneven film thickness, resulting in different speeds of the book body, resulting in a more detailed body of the tide "on the power supply due to different film thickness (10) film thickness caused by different capacitance, the required ^ discharge time is also the same as the 'directory crystal rotation recovery The time is also different. On the panel, there is a shadow like the tide of the tide. The factory ^ this 'in order to solve the above-mentioned age phenomenon, some display panel settings are shown [more for this problem - some solutions, as shown 1 and Figure 2: 2Γ1 is the block diagram of the well-known gate driver, and Figure 2 is the signal timing of the diagram i. Please refer to the temporary reference table for the need of the training. 1G shifting 105 into the comprehensive = normal shifter 103, the wheeling buffer 104, the reset circuit stv2屮1〇1 for buffering the clock signal CPV, the starting signal is the month ^ OE, and all rounds The enable signal χ〇η〇 shift 5

200822011 0610067ITW 20914twf.doc/n The register 102 generates N shift signals according to the clock signal cpv and the start shift signal, _ ship flip ^ ° ^ #uSTV to form N round-out letters; 1 04 Bu ^ ^ No., then output through the output buffer, divided into two =: =, do signal buffer line G1 ~ GN (® towel not shown). Ride the panel as the gate. Figure 2° When the user _ when the shift register 102 t turns out the full output enable signal Xon (Figure 2

= 〇 1 (10) causes N output signals to be generated, and the gate drive (four) whistle $ N wall A recorded gut ~ gutn small (10) N 2 202 as shown) to simultaneously drive the polar lines between the display panels In the first place, it is possible to solve the tidal phenomenon caused by the difference in the discharge speed of each of the halogen crystals of the display panel. ...,:, because the full output enable signal x〇n must be controlled by the reset circuit 1〇5 on the Printed Circuit Board (pCB) of the display panel, and the reset circuit 105 is ready-made. Reset 1C. If the conventional architecture shown in Figure 来 is used to solve the tidal phenomenon, it is not only necessary to reset the crystal on the printed circuit board, which causes a burden on the manufacturing cost and must also be The placement of the wafer for additional printed circuit board routing makes the design and manufacture of the display panel time consuming and labor intensive, which is quite disadvantageous for display panel manufacturers who want to reduce manufacturing costs and thereby increase product profitability. SUMMARY OF THE INVENTION 6 200822011 0610067ITW 20914twf.doc/n - It is an object of the present invention to provide a driving apparatus that does not require the use of a reset wafer on a printed circuit board of a display panel to solve the tidal phenomenon of the display panel. Based on the above and other objects, the present invention provides a driving apparatus for driving a display panel including a plurality of gate lines, the driving unit and the unit. The driving unit is driven by the above-mentioned wheel ##. The electric dust detection is electrically connected to the driving unit, and according to the logic driving the driving unit, the control is generated. The side unit outputs a control signal to the drive=兀n axis unit domain (4) (4). The above iS 5 tiger 0 bit temporarily 3 according to an embodiment of the present invention, the above-mentioned driving unit includes shifting out = two, shifting temporary storage unit 70 In order to receive the start signal, the clock signal, 'to the abdomen signal. The shift register unit generates a plurality of shift signals according to the start signal, and outputs 四(4)=遽' according to the output enable signal to form the output signal. The shift register unit also simultaneously generates the above output signal according to the control signal. Included in the embodiment, the shift register unit logic control circuit described above. The shift register is configured to receive the 控制= control circuit electrically connected to the shift register and the electric (four) test single-energy signal 'the plurality of shift signals, and the control domain. The fine control circuit outputs the plurality of 200822011 0610067ITW 20914twf.doc/n shift signals according to the output enable signals to form the output signals, and the logic control circuit simultaneously generates the output signals according to the control signals. According to an embodiment of the invention, the voltage detecting unit comprises a comparison circuit and a selection circuit. The comparison circuit is electrically connected to the logic driving voltage of the driving unit and the reference voltage for comparing the values of the logic driving voltage and the reference voltage, and outputting the comparison signal accordingly. The selection circuit is electrically connected between the logic driving voltage of the driving unit and the ground voltage, and is used for determining one of the logic driving voltage and the ground voltage of the output driving unit according to the comparison signal. According to an embodiment of the invention, the selection circuit includes a first transistor and a second transistor, wherein the first transistor is a PMOS transistor (P-type metal_oxide_semiconductor transistor), and the second transistor is a NMOS transistor (N-type metal-oxide_semiconductor transistor). The comparison circuit described above includes a comparator having a positive input, a negative input, and an output. The gate of the first transistor receives the comparison signal, and one of the source/drain of the first transistor is electrically connected to the logic driving voltage of the driving unit. The gate of the second transistor also receives the comparison signal, and one of the source/drain of the second transistor is electrically connected to another source/drain of the first transistor, and another source of the second transistor Very electrically connected to the ground voltage. The negative input terminal of the comparator is electrically connected to the logic driving voltage of the driving unit, the positive input end of the comparator is electrically connected to the reference voltage, and the output end of the comparator is electrically connected to the first transistor and the second transistor. The gate. 200822011 〇610067ITW20914twf.doc/n In accordance with an embodiment of the invention, the logic control circuit described above includes a plurality of gates and a plurality of gates. One of the input terminals of each of the gates receives an inverted signal of the output enable signal, and the other input of each of the gates correspondingly receives one of the plurality of shift signals, and each of the gates The input end receives the inverted signal of the control signal, and the other input end of each OR gate correspondingly receives the output end of one of the gates, and the output end of the OR gate outputs the output signal. The invention adopts a voltage detecting unit in the driving device, and uses the voltage detecting unit to compare the preset reference voltage with the value of the logic driving voltage of the driving unit to generate a control signal, and causes the voltage detecting unit to output the control when the power is turned off.彳§号 to the shift register unit in the driving device, so that the shift register unit simultaneously outputs a plurality of output signals, thereby simultaneously driving the gate line of the display panel to solve the discharge of each halogen crystal in the display panel Tidal phenomena caused by different speeds. Therefore, the present invention not only does not require additional resetting of the wafer on the printed circuit board, but also reduces the burden of manufacturing costs, and does not have to be directed to resetting the wafer. $Line of additional printed circuit board layouts simplifies the process of designing and manufacturing display panels. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. 3 is an architectural block diagram of a driving device according to an embodiment of the present invention. Please refer to FIG. 3. The driving device shown in FIG. 3 includes a driving unit 3〇1 9 200822011 0610067ITW 20914twf.doc/n and The voltage detecting unit 302. In this embodiment, the driving unit 〇1 receives an external voltage as the logic driving voltage VDDD of the driving unit 〇1. The driving unit 〇1 is used to generate the output signals. The gate lines G1 GN (not shown) of the display panel are driven by the output signals 〇 UT1 〇 UTN, respectively. The voltage detecting unit 302 is electrically connected to the driving unit 3〇1, The control signal f) is generated according to the level of the logic driving voltage VDDD of the driving unit 301, and the voltage detecting unit 302 outputs the control signal cs to the driving unit 301, so that the driving unit 301 simultaneously generates an output according to the control signal cS. Signals OUT1~OUTN. Output signals are generated when the drive unit 3〇1 @

When OUT1 to OUTN' drive the gate lines G1 to GN of the violent page display panel at the same time, it is possible to solve the tidal phenomenon caused by the difference in discharge speed of each of the halogen crystals in the display panel. In this embodiment, the driving unit 〇1 includes an input buffer 〇3, a private temporary storage unit 3G4, a level shift-3()5, and an output buffer 〇6. However, since each manufacturer does not have a certain design for the driving unit 313, the components included in the driving unit 3G1 described herein should not be limited to this embodiment. The input buffer 303 is electrically connected to the shift register unit 〇4 for owing and buffering the start money STV, the Wei signal cpv, and the output enable 仏. The shift register unit 3. 4 is configured to receive the # signal STV, the clock signal cpv, and the output to the moon OE ′ through the input buffer 303, and the shift register unit 〇4 also receives the voltage debt detecting unit 302. The generated control signal cs. 200822011 0610067ITW 20914twf.doc/n The private temporary storage list 3G4 generates N shift signals according to the clock signal cpv and the start signal =, and then according to the output enable signal ^ 'out the above N shift money, N output signals are formed. The level shifting benefit 3〇5 receives and shifts the above-mentioned signal output level of the solid output signal and then outputs the above-mentioned displacement over-signal level through the output buffer 3〇6 as a signal buffer and outputs it, and divides the county (10). (10) Melon, in order to drive, the secret line of the display panel G1 ~ GN (10) towel is not _). Shooting, shifting the temporary unit also generates the above-mentioned n inputs according to the control signal cs

The shift register unit 304 includes a shift register H 3 〇 7 and a logic control circuit 308. The shift register 3〇7 is configured to receive the start signal and the clock signal CPV, and accordingly generate the plurality of shift money described above. The logic control circuit 308 is electrically connected to the shift register 3〇7 and the voltage detecting unit to receive the output enable signal GE, the N-index signal, and the control signal cs. The logic control circuit 308 inputs the above-mentioned N shift signals according to the output enable signal 〇e to form the above-mentioned u output signals. The logic control circuit 308 is also operative to simultaneously generate the N output signals in accordance with the control signal cs. 4 is a circuit diagram of a voltage detecting unit in accordance with an embodiment of the present invention. Please refer to Figure 4. 4 is an internal circuit of the voltage detecting unit 3〇2 of FIG. 3, which includes a comparing circuit 401 and a selecting circuit 4〇2. The comparison circuit 401 is electrically connected to the logic driving voltage vddd of the driving unit and the reference voltage VTH for comparing the values of the logic driving voltage VDDD and the multi-test voltage VTH, and outputting the comparison signal ps accordingly. The selection circuit 11 200822011 0610067ITW 20914twf.doc/n 402 is electrically connected between the logic driving voltage VDDD of the driving unit 301 and the ground voltage GND for determining the logic driving voltage VDDD and the ground voltage GND of the output driving unit according to the comparison signal PS. one of them. In this embodiment, the comparison circuit 401 is implemented as a comparator 403, and the selection circuit 402 is implemented as a transistor 404 and a transistor 405, wherein the transistor 404 is a PMOS transistor and the transistor 405 is an NMOS transistor.

Comparator 403 has a positive input, a negative input, and an output. The negative input terminal of the comparator 403 is electrically connected to the logic driving voltage VDDD of the driving unit, and the positive input terminal of the comparator 403 is electrically connected to the reference voltage vth, and the output terminal of the comparator is electrically connected to the transistor 4〇4 and the transistor 4 〇5 gate. The gate of the transistor 404 receives the comparison signal ps, and the source of the transistor 4〇4 is electrically connected to the logic driving voltage vddd of the driving unit. The gate of the transistor 405 receives the comparison signal ps, the gate of the transistor 4〇5 is electrically connected to the pole of the transistor 404, and the source of the transistor 405 is electrically connected to the grounding power~'π田j If necessary, the design of the internal circuit is changed. The above-mentioned actual method is used to limit the comparison circuit 401 to select the circuit (4). When the voltage ΓΓ is connected to (4) the logic __ press is called the reference electric M VTH, the comparator 403 rotates the electric crystal, the partial selection I· + turns out the comparison ^ S is high logic, and the control domain CS of 11 is the ground voltage. GND (ie low logic 12 200822011 0610067ITW 20914twf.doc/n series). When the logic driving voltage VDDD received by the comparator 403 is greater than the reference voltage VTH, the comparison signal ps output by the comparator 403 is low logic, so that the transistor 404 is turned on and the transistor 4〇5 is turned on, so the voltage detecting unit 302 The output control signal cs is the logic drive voltage VDDD (ie, high logic). Therefore, the voltage detecting unit 3〇2 determines whether the control signal CS is south logic or low logic by comparing the values of the logic driving voltage VDDD and the reference voltage VTH, so that the driving unit 3〇1 shown in FIG. 3 can be based on the control signal. The signal state of CS simultaneously produces output signals OUT1 to OUTN.凊 Refer to Figure 3 and Figure 5 for the requirements of A? and description. Fig. 5 is an internal circuit diagram of a driving device in accordance with an embodiment of the present invention. Referring to FIG. 5, the input buffer 501, the shift register 5, the logic control circuit 503, and the voltage detecting unit 505 shown in FIG. 5 are respectively input buffers 303 and shifts shown in FIG. The register 307, the logic control circuit 3〇8, and the voltage detecting unit 302, and the level shifter and output buffer 5〇4 shown in FIG. 5 are the level shifters 305 shown in FIG. Combined with the output buffer 3〇6. The voltage detecting unit 5〇5 shown in FIG. 5 is designed by using the voltage detecting unit shown in FIG. 4, and the logic control circuit 5〇3 of FIG. 5 is the inside of the logic control circuit 308 of FIG. The actual design of the circuit. The logic control circuit 503 includes N gates 507, N gates 508, and inversions and 51 turns. One of the inputs 507 outputs an inverted signal /0E of the enable signal OE, and the other input of each of the gates 5〇7 correspondingly receives one of the shift signals Q1~(3>^. And one of the inputs of each of the gates 5〇8 receives the inverted signal /CS of the control signal cs, and each of the other inputs of the 13200822011 0610067ITW20914twf.doc/n gate 508 correspondingly receives the gates (10) The output end of the thin 508 wheel is ^^ρι~ρΝ. However, in the embodiment shown in FIG. 5, the voltage detecting unit 5〇5 is not limited to (4) the voltage of the tf of FIG. Design method. 2 The drive device design logic control circuit 'is the logical operation of the domain in the drive assembly. The design method of Yang Shangzao logic control circuit is not the same, so the logic control circuit 5图3 of Fig. 5 The circuit of η 二 is also not used to define the internal circuit of the logic control circuit. Winter printing refers to Figure 4 and Figure 5 according to the needs of the description. Please refer to Figure 4 first. At this time, the logic drive voltage is greater than the reference voltage VTH, so the control money (^ is high) In the above case, the control signal cs ^ outputted by the voltage detecting unit 5〇5 is inverted to its inverted signal /cs (ie, low logic), so the logic control circuit N or gates 508 of 503 are operated according to the signals K1~KN output by the N gates 507, so that the driving device outputs the output signals OUT1~OUTN in sequence to sequentially drive the gate lines of the display panel. G1~GN (not shown). Referring to Figure 4, when the display panel is turned off, the voltage detecting unit 505 detects the logic driving voltage VDDD. When the logic driving voltage VDDD is less than the reference voltage vTH, The control signal cs is low logic. Figure 6 is a timing diagram of some internal signals of the driving device according to an embodiment of the invention. Please refer to FIG. 5 and FIG. 6. In the above case, the voltage detecting unit 505 of FIG. The control signal cS (which is low logic, as shown in Figure 2, 200822011 0610067ITW 20914twf.doc/n 601) is inverted by the inverter 51〇 into its inverted signal /cs (ie high logic 'Figure 6 602), so N of the logic control circuits 5〇3 The gate 5〇8 outputs the high logic output signal P1~PN at the same time according to the high logic inverted signal /cs(5), as shown in Fig. 6 and the ?1 and !>2, wherein P1 of Fig. 6 P2 is the state of the ρι盥p/ corresponding to FIG. 5, and the level shifter of the output buffer H5〇4 towel is used to receive and shift the above-mentioned N output signals ρι~ρΝ The signal bit is then transmitted through the level shifter and the output buffer 5〇4 b: on the N output signals of the signal level to make a signal = the output is OUT1~OUTN to drive the display panel at the same time The closed lines G1 to GN (not shown). In this way, it is possible to solve the problem of the axial sanding caused by the different discharge speeds of the respective halogen crystals. It is worth mentioning that, although in the above embodiments, the internal circuit of the unit and the logic control circuit; the type of pressure detection is possible, but those skilled in the art should be aware that each manufacturer - the early control circuit and the logic control circuit The riding method is not the same, because the ^ Fort detection application does not p (four) 彳 in this possible type H. The reference voltage of the present invention and the logic driving of the driving unit "using the pre-made signal" and using the original logic buckle in the driving device to simultaneously drive the gate line of the display panel, is already the spirit of the signal. In view of the above, the present invention is based on picking in the driving device and comparing the preset reference voltage with the voltage detecting unit: 1: Yuan speed = production line := Each pixel in the panel is mounted on the board. This does not require additional reset wafers for additional power in the printed circuit; = cost burden, and no need for a printed circuit for resetting the wafer. Board wiring, simplifies the design and manufacture of display panel definitions = hair and i heat & the skilled person 'without departing from the spirit of the invention' § can make some changes and retouching, so the invention has been gardened It is subject to the definition of the application for Wei Xing. ... u [Simple diagram of the diagram] Figure 1 is a block diagram of the structure of a conventional gate driver. Figure 2 is a signal timing diagram of a conventional gate driver. 3 for Figure 4 is a circuit diagram of a voltage side unit in accordance with an embodiment of the present invention. Fig. 5 is an internal circuit 16 of a driving apparatus according to an embodiment of the invention. 200822011 0610067ITW 20914twf. Doc/n Figure 6 is a timing diagram of a portion of internal signals of a driving device in accordance with an embodiment of the present invention. [Description of Main Component Symbols] 101, 303, 501: Input Buffer 102: Shift Registers 103, 305: Bits Quasi-shifter 104, 306: output buffer 105: reset circuit 201, 202, 601, 602, 603: state 301 of signal: drive unit 302, 505: voltage detection unit 304: shift register unit 307 502: shift register 308, 503: logic control circuit 401: comparison circuit 402: selection circuit 403: comparator 404, 405: transistor 504: level shifter and output buffer 507: and gate 508: OR gate 509, 510: inverter CPV: clock signal CS: control signal 17 200822011 0610067ITW 20914twf.doc/n GND : ground voltage K1 ~ KN: and gate output signal OE: output enable signal OUT1 ~ OUTN-l , OUTN · · Output Signal PS : Comparison Signals P1 to PN: or gate output signals Q1 to QN: shift signal STV: start signal VDDD: logic drive voltage VTH: reference voltage Χοη: full output enable signal /CS: inverted signal of control signal /ΟΕ: Output inversion signal of the enable signal 18

Claims (1)

200822011 X. Patent application scope: -1·- kind of driving device, suitable for driving - display panel comprising a plurality of gate lines, the driving device comprises: - driving unit 70' for generating a plurality of output signals, by The output signals drive the gate lines; and π: the voltage side is 7L, electrically connected to the nanoscale element, and according to the driving voltage of the driving ^70, the control is generated, and the voltage is sealed. The control number is to the _ unit, so that the driving unit generates the output signals according to the control signal. The moving unit includes a -shift temporary storage unit, and the heart is pure-initiated Signal, the shift register unit outputs the signal. The drive device according to the first aspect of the invention, wherein the drive is configured to receive a start signal, a time and the control signal, and the shift is temporarily stored. Generating multiple shift signals, and numbers, to form the outputs The burst control circuit outputs the shift signals according to the output enable signal to form the output signals, and the logic control circuit simultaneously generates the output signals according to the control signals. 4. The driving device of claim 2, wherein the driving unit further comprises: a quasi-shifter electrically connected to the shift register unit for receiving the output signals and displacing the The signal level of these output signals. 5. The driving device of claim 4, wherein the driving unit further comprises: 〃 an output buffer electrically connected to the level shifter for receiving and buffering the level shifter The output. 6. The device as claimed in claim 2, wherein the driving unit further comprises: an input buffer electrically connected to the shift register unit for receiving and buffering the start signal, the time Pulse signal, and the output enable signal. 7. The driving device of claim 2, wherein the voltage detecting unit comprises: a vectoring circuit that electrically connects the logic driving voltage and the voltage of the driving unit to compare the logic driving. The voltage and the value of the reference voltage, and according to the output of a comparison signal; The circuit is electrically connected to the logic driving voltage of the driving unit between the voltages of the ... i voltages for determining, according to the comparison signal, one of the logic driving voltages of the driving circuit and the ground voltage. The driving device of claim 7, wherein the selection circuit comprises: 200822011 0610067IT W 20914twf. doc/n - the first transistor - the gate of the first transistor receives the comparison signal, the first a logic driving voltage of the driving unit in which the source/source is not electrically connected; and a gate of the second transistor receiving the comparison signal, and one source/drain of the second transistor Another connection to the electrical connection is another source of the second transistor / 汲 = ground voltage. 9. The driving device according to item 8 of the patent application scope, wherein the middle (n) circuit comprises a comparator, the comparator has a positive input terminal, and an output terminal, the negative input terminal of the comparator Electrically connecting the logic driving voltage of the driving unit, the positive input end of the comparator is electrically connected to the reference voltage, and the output end of the comparator is electrically connected to the gate of the first transistor and the second transistor . 10. The driving device of claim 9, wherein the first transistor comprises a PMOS transistor. The driving device of claim 10, wherein the transistor comprises an NMOS transistor. 2. The driving device of claim 3, wherein the logic control circuit comprises a plurality of gates and a plurality of gates, wherein each of the gates receives an output enable signal a phase signal, each of the other input terminals correspondingly receiving one of the shift signals, and each of the OR gates receives an inverted signal of the control signal, each of the Or the other input end of the gate correspondingly receives the output of one of the gates and the output terminals of the gates output the output signals. The driving device of claim i, wherein the logic control circuit further comprises a first inverter for receiving the output enable signal. To invert the output enable signal to its inverted signal. °,. The driving device of claim 12, wherein the control circuit further comprises a second inverter, wherein the second inverter is configured to control a signal to invert the control signal into Inverted signal. twenty two