TWI406250B - Boot sequnce protection circuit and method thereof - Google Patents

Abstract

The boot sequence protection circuit includes a comparator, an input voltage level detection circuit, a logic gate, a switch, and a gate low voltage output end. The boot sequence protection circuit receives an input voltage, a gate low voltage and a gate high voltage. The boot sequence protection circuit transmits the gate low voltage to the gate driver circuit. When the gate low voltage has reached a low level, the comparator outputs a gate low voltage level detection signal. The input voltage level detection circuit outputs an input voltage level detection signal. The logic gate outputs a gate high voltage level detection signal according to the input voltage level detection signal and the gate low voltage level detection signal, for closing the switch. When the switch closes, the gate high voltage is transmitted to the gate driver circuit.

Description

Start timing protection circuit and method

The present invention relates to a startup timing protection circuit, and more particularly to a startup timing protection circuit for a gate drive circuit.

Please refer to Figure 1. Figure 1 is a schematic illustration of a prior art liquid crystal display 10. The liquid crystal display 10 includes a power circuit 12, a gate driving circuit 14, a source driving circuit 16, and a display panel 18. The power supply circuit 12 receives the input voltage V _CC and accordingly generates a data driving voltage V _S , a gate low voltage V _{GL ,} and a gate high voltage V _GH . The gate driving circuit 14 is electrically connected to the power supply circuit 12. The gate driving circuit 14 is configured to receive the gate low voltage V _GL and the gate high voltage V _GH to generate the gate control signal SG. The source driving circuit 16 is electrically connected to the power circuit 12 for receiving the data driving voltage V _S to generate the data driving signal S _S .

The display panel 18 includes a plurality of data lines, a plurality of gate lines perpendicular to the data lines, and a plurality of thin film transistors (TFTs). More specifically, a thin film transistor is electrically connected to each of the data lines and the scanning lines of the display panel 18. Each of the thin film electro-crystal systems corresponds to a pixel, that is, the thin film electro-crystal system is distributed on the display panel 18 in a matrix manner. The source driving circuit 16 is electrically connected to each of the data lines of the display panel 18 , and the gate driving circuit 14 is electrically connected to each of the scanning lines of the display panel 18 . That is to say, each data line in the display panel 18 is driven by the data driving signal S _S , and each scanning line of the display panel 18 is driven by the gate control signal S _G . In short, the source driving circuit 16 and the gate driving circuit 14 control the conduction of the thin film transistor in the display panel 18 to display a picture.

Please refer to Figure 2. Fig. 2 is a waveform diagram showing the normal voltage when the gate driving circuit 14 is activated. When the liquid crystal display 10 is turned on, the input voltage V _{CC is} stabilized, and then the gate low voltage V _GL reaches a low level (for example, the gate low voltage V _GL drops from the original 0 volt to -6 volts), so that the gate The drive circuit 14 turns off all of the scan lines of the display panel 18 to prevent boot noise. Thereafter, the gate high voltage V _{GH is} again activated to a high level (for example, the gate high voltage V _GH rises from the original 0 volts to 18 volts) to turn on the display panel 18 and drive its scan line. Therefore, under normal operation, the voltage timing of the liquid crystal display 10 being turned on is: V _CC → V _GL → V _GH .

However, the prior art gate drive circuit 14 does not have any mechanism for detecting voltage timing. When the order in which the power supply circuit 12 transmits the gate low voltage V _GL and the gate high voltage V _GH to the gate driving circuit 14 is not as described above, it is possible that the gate of the gate driving circuit 14 is turned off during the power-on phase. The pole drive signal S _G turns on the display panel 18 to display the previously remaining picture, causing noise. In addition, the abnormal power-on voltage timing causes the gate driving circuit 14 to operate incorrectly at the moment when the liquid crystal display 10 is turned on. As such, the liquid crystal display 10 may fail to activate or even damage the gate drive circuit 14.

The present invention provides a startup timing protection circuit. The startup timing protection circuit includes a comparator for detecting whether a gate low voltage reaches a first predetermined level, and includes a first input terminal for receiving the gate low voltage; and a second input terminal And an output end for outputting a gate low voltage level determination signal according to the comparison result of the gate low voltage and the gate reference voltage; determining an input voltage level The circuit is configured to receive an input voltage and generate an input voltage level determining signal according to an input reference voltage; a logic gate includes a first input end electrically connected to the input voltage level determining circuit, Receiving the input voltage level determination signal; a second input terminal electrically connected to the comparator for receiving the gate low voltage level determination signal; and an output terminal for the input voltage level The bit determining signal and the gate low voltage level determining signal are logically operated to output a gate high voltage level determining signal at the output end of the logic gate; a switch electrically connected to the logic Gate; and a gate low voltage output terminal, for receiving the gate voltage is low, and transmit it to a gate driving circuit.

The present invention further provides a method of starting voltage timing. The method includes receiving a gate low voltage and a gate high voltage; outputting the gate low voltage to a gate driving circuit; and detecting whether the gate low voltage reaches a first level by comparing with a gate reference voltage a predetermined level to generate a first control signal; receiving an input voltage; and detecting whether the input voltage reaches a second predetermined level by comparing with an input reference voltage to generate a second control signal And outputting the gate high voltage to the gate driving circuit according to the first control signal and the second control signal.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the differences in the functions of the elements as the basis for the distinction. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "electrical connection" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is electrically connected to a second device, it means that the first device can be directly connected to the second device or indirectly connected to the second device through other devices or connection means.

Accordingly, it is an object of the present invention to provide a gate drive circuit having a startup timing protection circuit for ensuring that the voltage timing of the liquid crystal display is in compliance with specifications.

Please refer to Figure 3. Figure 3 is a schematic view showing the liquid crystal display 30 of the present invention. The liquid crystal display 30 includes a power supply circuit 32, a gate drive circuit 34, a start timing protection circuit 33, a source drive circuit 36, and a display panel 38. When the liquid crystal display 30 is turned on, the power supply circuit 32 receives the input voltage V _CC and accordingly generates a data driving voltage V _S , a gate low voltage V _{GL ,} and a gate high voltage V _GH . The startup timing protection circuit 33 is electrically connected between the power supply circuit 32 and the gate driving circuit 34 while receiving the input voltage V _CC . The startup timing protection circuit 33 is used to ensure the correct timing of the gate low voltage V _GL and the gate high voltage V _GH . The gate driving circuit 34 is configured to receive the gate low voltage V _GL and the gate high voltage V _{GH of the} correct startup timing from the startup timing protection circuit 33 to generate the gate control signal S _G . The source driving circuit 36 is electrically connected to the power circuit 32 for receiving the data driving voltage V _S to generate the data driving signal S _S . The display panel 38 is electrically connected to the gate driving circuit 34 and the source driving circuit 36. The display panel 38 displays a picture based on the received gate control signal S _G and the data drive signal S _S .

Please refer to Figure 4. Figure 4 is a schematic diagram of the startup timing protection circuit 33 of the present invention. The startup timing protection circuit 33 includes a gate reference voltage source 331, a comparator 332, a gate 333, an input voltage level determining circuit 334, a switch 335, and an output terminal O _GL . The gate reference voltage source 331 provides a gate reference voltage that is close to a negative voltage of 0 volts (for example, -0.5 volts). The comparator 332 includes a first input terminal, a second input terminal, and an output terminal. The gate low voltage V _{GL is} input to one of the first inputs of the comparator 332 and is input to the gate driving circuit 34 through the output terminal O _GL ; the gate reference voltage source 331 is the input gate reference voltage to the comparator 332 One of the second inputs. The comparator 332 is configured to compare the gate reference voltage with the gate low voltage V _GL and accordingly generate a gate low voltage level determination signal S _GL . For example, when the gate low voltage V _GL is 0 volts, the gate low voltage V _{GL is} higher than the gate reference voltage, and the gate low voltage level determination signal S _GL is logic "0" (low potential); When the gate low voltage V _GL drops to -6 volts, the gate low voltage V _{GL is} lower than the gate reference voltage, and the gate low voltage level determination signal S _GL is logic "1" (high power standing).

The input voltage level determining circuit 334 is configured to receive the input voltage V _CC and generate an input voltage level determining signal S _CC according to an input reference voltage. For example, the input reference voltage is 2 volts; when the input voltage V _CC is 0 volts (below the input reference voltage), the input voltage level determination signal S _CC is logic "0" (low potential); when the input voltage When V _CC is 5 volts (higher than the input reference voltage), the input voltage level determination signal S _CC is logic "1" (high potential). The gate 333 includes a first input terminal, a second input terminal, and an output terminal. The first input end of the gate 333 is electrically connected to the input voltage level determining circuit 334 for receiving the input voltage level determining signal S _CC ; the second input end is electrically connected to the output end of the comparator 332 for receiving The gate low voltage level judgment signal S _GL . The gate 333 performs an AND operation on the input voltage level determination signal S _CC and the gate low voltage level determination signal S _GL for outputting a gate high voltage level determination signal S _GH . For example, when the input voltage level determination signal S _CC and the gate low voltage level determination signal S _GL are both logic "1" (high potential), the gate 333 outputs a logic "1" (high potential) gate. Very high voltage level judgment signal S _GH .

The switch 335 is used to receive the gate high voltage V _GH and is electrically connected to the output of the AND gate 333. The switch 335 is controlled by the gate high voltage level determining signal S _GH outputted by the gate 333. For example, when the gate high voltage level determination signal S _GH is logic "0" (low potential), the switch 335 is non-conducting; when the gate high voltage level determination signal S _GH is logic "1" (high) At the potential), the switch 335 is turned on. When the switch 335 is turned on, the gate high voltage V _GH can be transferred to the gate drive circuit 34 via the switch 335.

Furthermore, the gate high voltage V _GH can be transmitted to the gate driving circuit 34 via the switch 335 only when the switch 335 is in the on state; only when the gate high voltage level determining signal S _GH is logic "1" (High potential), the switch 335 will be turned on; only when the input voltage level determination signal S _CC and the gate low voltage level determination signal S _GL are both logic "1" (high potential), the gate 333 will The gate high-voltage level determination signal S _{GH of the} logic "1" (high potential) is output; the comparator 332 outputs a logic "1" (high) only when the gate low voltage V _GL falls to -6 volts. The gate of the potential) low voltage level judgment signal S _GL . Therefore, by the protection of the startup timing protection circuit 33, the gate driving circuit 34 must first receive the gate low voltage V _GL reaching the low level, and then receive the gate high voltage V _GH reaching the high level.

Please refer to FIG. 5, which is a flow chart for explaining the operation of the startup timing protection circuit 33 of the present invention. The startup timing protection circuit 33 operates in accordance with the following steps:

Step 51: The liquid crystal display 30 is turned on, the input voltage V _{CC is} input to the power supply circuit 32 and the input voltage level determining circuit 334;

Step 52: The power supply circuit 32 generates a gate low voltage V _GL and a gate high voltage V _GH ; the start timing protection circuit 33 inputs the gate low voltage V _GL to the gate drive circuit 34 through the output terminal O _GL ;

Step 53: The comparator 332 detects whether the gate low voltage V _GL reaches a low level according to the reference voltage source 331; if yes, proceed to step 54; if not, return to step 52;

Step 54: Comparator 332 outputs a logic "1" (high potential), so that the gate 333 outputs a logic "1" (high potential), thereby turning on the switch 332;

Step 55: The gate high voltage V _{GH is} input to the gate driving circuit 34 via the switch 332. When the liquid crystal display 40 is turned on, the input voltage V _{CC is} simultaneously input to the power supply circuit 32 and the input voltage level determining circuit 334. Input voltage level determination circuit 334 according to the level of the input voltage V _CC, for generating an input signal voltage level is determined S _CC. The power supply circuit 32 generates a gate low voltage V _GL and a gate high voltage V _GH according to the input voltage V _CC . The gate low voltage V _GL and the gate high voltage V _GH are transmitted to the comparator 332 of the timing protection circuit 33 and the switch 335, respectively. Next, the timing protection circuit 33 first transfers the gate low voltage V _GL to the gate driving circuit 34 through the output terminal O _GL . The comparator 332 detects whether the gate low voltage V _GL reaches a low level based on the reference voltage source 331. When the gate low voltage V _GL reaches the low level, the comparator 332 outputs a gate low voltage level determination signal S _{GL of} logic "1" (high potential). The gate 333 performs an AND operation on the input voltage level determination signal S _CC and the gate low voltage level determination signal S _GL . When the input voltage level determination signal S _CC and the gate low voltage level determination signal S _GL are both logic "1" (high potential), the gate 333 outputs a logic "1" (high potential) gate high voltage level. Bit judgment signal S _GH . When the gate high voltage level determination signal S _GH is logic "1" (high potential), the switch 335 is turned off, and the gate high voltage V _GH is input to the gate driving circuit 34 via the switch 335. The timing protection circuit 33 of the present invention can control the gate low voltage V _GL and the gate high voltage by delaying the output gate high voltage V _GH to the gate driving circuit 34 by using the gate high voltage level determining signal S _GH . The timing of V _GH is in compliance with the specifications.

In summary, the startup timing protection circuit provided by the present invention can effectively ensure that the voltage timing of the liquid crystal display is in compliance with the specification, and provides great convenience for the user.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 30. . . LCD Monitor

12, 32. . . Power circuit

14, 34. . . Gate drive circuit

16, 36. . . Source drive circuit

18, 38. . . Display panel

33. . . Start timing protection circuit

331. . . Reference voltage source

332. . . Comparators

333. . . Gate

334. . . Input voltage level judgment circuit

335. . . switch

51~55. . . step

O _GL . . . Output

S _CC . . . Input voltage level judgment signal

S _GH . . . Gate high voltage level judgment signal

S _GL . . . Gate low voltage level judgment signal

S _G . . . Gate control signal

S _S . . . Data drive signal

V _S . . . Data drive voltage

V _CC . . . Input voltage

V _GH . . . Gate high voltage

V _GL . . . Gate low voltage

Figure 1 is a schematic illustration of a prior art liquid crystal display.

Figure 2 is a waveform diagram of the normal voltage at the start of the gate drive circuit.

Figure 3 is a schematic view showing the liquid crystal display of the present invention.

Figure 4 is a schematic diagram of the startup timing protection circuit of the present invention.

Figure 5 is a flow chart showing the operation of the startup timing protection circuit of the present invention.

33. . . Start timing protection circuit

331. . . Gate reference voltage source

332. . . Comparators

333. . . Gate

334. . . Input voltage level judgment circuit

335. . . switch

O _GL . . . Output

S _CC . . . Input voltage level judgment signal

S _GH . . . Gate high voltage level judgment signal

S _GL . . . Gate low voltage level judgment signal

V _CC . . . Input voltage

V _GH . . . Gate high voltage

V _GL . . . Gate low voltage

Claims (15)

A startup timing protection circuit includes: a comparator for detecting whether a gate low voltage reaches a first predetermined level, comprising: a first input terminal for receiving the gate low voltage; a second input terminal for receiving a gate reference voltage; and an output terminal for outputting a gate low voltage level determination signal according to the comparison result of the gate low voltage and the gate reference voltage; an input voltage a level determining circuit for receiving an input voltage and generating an input voltage level determining signal according to an input reference voltage; a logic gate comprising: a first input terminal electrically connected to the input voltage level a determining circuit for receiving the input voltage level determining signal; a second input terminal electrically connected to the comparator for receiving the gate low voltage level determining signal; and an output terminal, the logic gate is The input voltage level determining signal and the gate low voltage level determining signal are logically operated to output a gate high voltage level determining signal at the output end of the logic gate; a switch, electrical Connected to the logic gate; and a gate low voltage output terminal, for receiving the gate voltage is low, and transmit it to a gate driving circuit. The startup timing protection circuit of claim 1, wherein the gate reference voltage is a negative voltage. The startup timing protection circuit of claim 2, wherein when the gate low voltage is lower than the gate reference voltage, the comparator outputs the gate low voltage level determination signal indicating a first logic. The start timing protection circuit of claim 3, wherein when the input voltage is higher than the input reference voltage, the input voltage level determining circuit outputs the input voltage level determining signal indicating the first logic. The startup timing protection circuit of claim 4, wherein the logic gate is a gate and a AND operation. The startup timing protection circuit of claim 5, wherein when the input voltage level determination signal and the gate low voltage level determination signal are all the first logic, the gate high voltage level determination signal is The first logic. The start timing protection circuit of claim 6, wherein when the gate high voltage level determination signal is the first logic, the switch is turned on; when the gate high voltage level determination signal is not the first When logic, the switch does not turn on. The startup timing protection circuit of claim 7, wherein the gate high voltage is transmitted to the gate driving circuit via the switch when the switch is turned on. The startup timing protection circuit of claim 1, further comprising: a power supply circuit for generating the gate low voltage and the gate high voltage according to the input voltage. The activation timing protection circuit of claim 9, wherein the first input end of the comparator is electrically connected to the power supply circuit to receive the gate low voltage; the switch is electrically connected to the power supply circuit to Receiving the gate high voltage; the gate low voltage output terminal is electrically connected to the power supply circuit to transmit the gate low voltage to the gate driving circuit. A method for starting a voltage sequence, comprising: receiving a gate low voltage and a gate high voltage; outputting the gate low voltage to a gate driving circuit; detecting the gate by comparing with a gate reference voltage Whether the low voltage reaches a first predetermined level to generate a first control signal; receiving an input voltage; and detecting whether the input voltage reaches a second predetermined level by comparing with an input reference voltage, Generating a second control signal; and outputting the gate high voltage to the gate driving circuit according to the first control signal and the second control signal. The method of claim 11, further comprising: providing the input voltage; and generating the gate low voltage and the gate high voltage according to the input voltage. The method of claim 12, wherein the first control signal is a first logic when the gate low voltage reaches the first predetermined level. The method of claim 13, wherein the second control signal is the first logic when the input voltage reaches the second predetermined level. The method of claim 14, wherein when the first control signal and the second control signal are both the first logic, the gate high voltage is output to the gate driving circuit.