TWI413051B - Start protection circuit for gate driver and liquid crystal display thereof - Google Patents

Abstract

A start protection circuit of a gate driver, which is applied in a liquid crystal display, includes a detection circuit and a switch. The detection circuit detects a gate low voltage to generate a control signal. The switch is electrically connected to the detection circuit controlled by the control signal, for transmitting a gate high voltage. The detection circuit outputs the gate low voltage first and detects if the gate low voltage reaches to a predetermined level. When the gate low voltage reaches to the predetermined level, the detection circuit turns on the switch to output the gate high voltage.

Description

Start-up protection circuit of gate driver and liquid crystal display using same

The present invention relates to a gate driver, and more particularly to a gate driver having a startup protection circuit.

Please refer to FIG. 1 , which is a schematic diagram of a prior art liquid crystal display. The liquid crystal display 10 includes a system board 12 and a display panel 16. The system board 12 is provided with a power circuit 14, and the display panel 16 is provided with a gate driver 18. The gate driver 18 includes a shift register 181, a level shifter 182, and an output buffer 183. The shift register 181 receives the control signals CPV, UD, XON, OE, STV of the liquid crystal display 10, and the potential converter 182 receives the gate low voltage VEEG and the gate high voltage VDDG generated by the power supply circuit 14 to generate the gate control. The signal buffer 183 outputs the gate control signal VG to the display panel 16. The power circuit 14 is used to generate the voltage required by the liquid crystal display 10. The power circuit 14 includes a DC/DC converter 141, a charge pump 142, a first retarder 143, and a second retarder 144. The DC/DC converter 141 converts the power supply voltage VCC into a voltage VDDA, and the charge pump 142 generates a gate low voltage VEEG and a gate high voltage VDDG according to the voltage VDDA.

Please refer to Figure 2, which is a waveform diagram of the voltage at which the gate driver is activated. When the liquid crystal display 10 is turned on, the power supply voltage VCC is stabilized, and then the gate low voltage VEEG reaches a low level, so that the gate driver 18 turns off all the scan lines to prevent the startup noise, and then activates the gate high voltage VDDG to reach one. High level to drive the scan line. Therefore, in order to ensure the normal operation of the liquid crystal display 10 and prevent damage to the gate driver 18, the voltage timings of the liquid crystal display 10 are respectively:

VCC→VEEG→VDDG

According to the voltage sequence, the gate low voltage VEEG and the gate high voltage VDDG pass through the first delay 143 and the second retarder 144 before the input potential converter 182, respectively, so that the gate low voltage VEEG and the gate high voltage VDDG will It is sent to the gate driver 18 in sequence to produce the correct boot sequence.

Please refer to Figure 3, which is a schematic diagram of the voltage timing error when the gate driver is started. Under normal conditions, the gate low voltage VEEG will operate before the gate high voltage VDDG starts, so that the gate driver 18 turns off all the scan lines, thus avoiding the undesirable phenomenon that may occur when the liquid crystal display 10 is turned on. However, since there is no mechanism for detecting the voltage timing inside the general gate driver 18, when the power supply circuit 14 synchronously transmits the gate low voltage VEEG and the gate high voltage VEEG to the display panel 16, the liquid crystal display 10 At the moment of power-on, the gate low voltage VEEG generates a glitch due to the coupling phenomenon of the gate high voltage VDDG, causing the gate driver 18 to operate incorrectly, so that the liquid crystal display 10 may not be turned on or even damage the gate driver 18.

Accordingly, it is an object of the present invention to provide a start-up protection circuit for a gate driver of a liquid crystal display to solve the above problems.

The invention provides a start protection circuit for a gate driver, comprising a detection circuit and a switch. The detection circuit is configured to transmit and detect a gate low voltage to generate a control signal. The switch is electrically connected to the detecting circuit, and the switch is controlled by the control signal for transmitting a gate high voltage.

The invention further provides a method for protecting a startup voltage of a gate driver, comprising: receiving a gate low voltage and a gate high voltage; outputting the gate low voltage; and detecting whether the gate low voltage reaches a preset level Bit; and when the gate low voltage reaches the preset level, the gate high voltage is output.

The invention further provides a gate driver comprising a startup protection circuit, a shift register, a potential converter and an output buffer. The startup protection circuit is configured to transmit a gate low voltage, and output a gate high voltage when the gate low voltage reaches a predetermined level. The shift register is configured to receive a display signal. The potential converter is electrically connected to the shift register, the detecting device and the switch for generating a gate control signal according to the display signal, the gate low voltage and the gate high voltage. The output buffer is electrically connected to the potential converter for outputting the gate control signal.

The invention further provides a liquid crystal display comprising a display panel, a start protection circuit and a gate drive circuit. The startup protection circuit is electrically connected to the display panel for transmitting a gate low voltage, and outputs a gate high voltage when the gate low voltage reaches a predetermined level. The gate driver is electrically connected to the detecting circuit and the switch for driving the liquid crystal display panel according to the gate low voltage and the gate high voltage.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the differences in the functions of the elements as the basis for the distinction. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "electrical connection" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is electrically connected to a second device, it means that the first device can be directly connected to the second device or indirectly connected to the second device through other devices or connection means.

Please refer to FIG. 4, which is a schematic diagram of a first embodiment of a liquid crystal display of the present invention. The liquid crystal display 40 includes a system board 42 and a display panel 46. The system board 42 is provided with a power circuit 44. The display panel 46 is provided with a gate driver 48. The gate driver 48 includes a shift register 481, a level shifter 482, an output buffer 483, and a startup protection circuit 49. The shift register 481 receives the display signals CPV, UD, XON, OE, STV of the liquid crystal display 40, and the potential converter 482 receives the gate low voltage VEEG and the gate high voltage VDDG generated by the power supply circuit 44 to generate the gate control. The signal VG, the output buffer 483 outputs the gate control signal VG to the display panel 46. The power circuit 44 is used to generate the voltage required by the liquid crystal display 40. The power circuit 44 includes a DC/DC converter 441 and a charge pump 442. The DC/DC converter 441 converts the power supply voltage VCC into a voltage VDDA, and the charge pump 442 generates a gate low voltage VEEG and a gate high voltage VDDG according to the voltage VDDA. The startup protection circuit 49 prevents the timing of the gate high voltage VDDG and the gate low voltage VEEG from being incorrect when the gate driver 48 is turned on, causing the screen of the liquid crystal display 40 to be abnormal or unable to be turned on normally.

Please refer to Figure 5, which is a timing diagram of the voltage at which the gate driver is activated. First, the power supply voltage VCC is stabilized after a first time t1, then the gate low voltage VEEG reaches a low level after a second time t2, and finally the gate high voltage VDDG reaches a high after a third time t3. Level. The second time t2 and the third time t3 are determined according to the specifications of the liquid crystal display. In the embodiment of the present invention, the startup protection circuit 49 can detect the level of the gate low voltage VEEG. When the gate low voltage VEEG reaches the low level, the gate high voltage VDDG is input to the gate driver 48, thus starting. The protection circuit 49 can avoid the erroneous voltage timing of the gate high voltage VDDG and the gate low voltage VEEG synchronous input gate driver 48, or the gate high voltage VDDG being input to the gate driver 48 before the gate low voltage VEEG.

Please refer to Figure 6, which is a schematic diagram of the startup protection circuit of Figure 4. The startup protection circuit 49 includes a detection circuit 491 and a switch 492. The detection circuit 491 is configured to detect the gate low voltage VEEG to generate a control signal S1. The switch 492 is electrically connected to the detecting circuit 491 and controlled by the control signal S1. The gate low voltage VEEG is transmitted to the gate driver 48 via the detection circuit 491, and the gate high voltage VDDG is transmitted to the gate driver 48 via the switch 492. The startup protection circuit 49 ensures that the timing of the gate high voltage VDDG and the gate low voltage VEEG is correct by detecting whether the gate low voltage VEEG reaches a low level. When the gate low voltage VEEG is less than the low level, the control signal S1 turns off the switch 492. When the gate low voltage VEEG reaches the low level, the control signal S1 turns on the switch 492 to cause the gate high voltage VDDG to be input to the gate driver 48. Therefore, the gate driver 48 must first receive the gate low voltage VEEG that reaches the low level, and then receive the gate high voltage VDDG that reaches the high level.

Please refer to Fig. 7. Fig. 7 is a flow chart showing the operation of the start protection circuit of Fig. 4. The startup protection circuit 49 operates in accordance with the following steps:

Step 710: The liquid crystal display 40 is turned on, and the power supply voltage VCC is input into the system board 42.

Step 720: The power supply circuit 44 generates a gate low voltage VEEG and a gate high voltage VDDG, and the detection circuit 491 inputs the gate low voltage VEEG to the gate driver 48.

Step 730: The detecting circuit 491 detects whether the gate low voltage VEEG reaches the low level. If yes, proceed to step 740. If not, return to step 720.

Step 740: The detection circuit 491 turns on the switch 492.

Step 750: The gate high voltage VDDG is input to the gate driver 48 via the switch 492. When the liquid crystal display 40 is turned on, the power supply circuit 44 generates the gate low voltage VEEG and the gate high voltage VDDG by using the charge pump 442. At this time, the detecting circuit 491 first transmits the gate low voltage VEEG to the gate driver 48, and continues. It is detected whether the gate low voltage VEEG reaches a low level to generate the control signal S1. When the gate low voltage VEEG reaches the low level, the control signal S1 turns on the switch 492, at which time the gate high voltage VDDG is input to the gate driver 48 via the switch 492. In addition, in the specification of the voltage timing, after the gate low voltage VEEG reaches the low level, it is set that the gate high voltage VDDG can reach the high level after a predetermined time. Therefore, in the embodiment of the present invention, the output gate high voltage VDDG may be delayed by the control signal S1, so that the timings of the gate low voltage VEEG and the gate high voltage VDDG conform to the specifications.

Please refer to FIG. 8. FIG. 8 is a schematic view showing a second embodiment of the liquid crystal display of the present invention. In this embodiment, the power circuit 44 further includes a first delay 443 and a second delay 444. Therefore, the gate low voltage VEEG and the gate high voltage VDDG pass through the first retarder 443 and the second retarder 444 before inputting the gate driver 48, so that the gate low voltage VEEG and the gate high voltage VDDG are successively It is sent to the gate driver 48 to produce the correct power-on sequence. However, the first delay 443 and the second delay 444 cannot ensure that the power supply circuit 44 outputs the gate voltage VEEG and the gate high voltage VDDG of the correct timing. Therefore, the startup protection circuit 49 of the present invention is also suitable for providing the delay circuit. Power circuit 44.

Please refer to FIG. 9. FIG. 9 is a schematic view showing a third embodiment of the liquid crystal display of the present invention. The circuit architecture of this embodiment is similar to that of the first embodiment of FIG. 4, except that in the present embodiment, the startup protection circuit 49 is disposed in the power supply circuit 44. In this way, the gate low voltage VEEG and the gate high voltage VDDG first enter the startup protection circuit 49 before the input gate driver 48, so that the gate low voltage VEEG and the gate high voltage VDDG are sequentially sent to the gate driver. 48 to produce the correct boot sequence. Therefore, the startup protection circuit 49 is disposed in the power supply circuit 44 to ensure that the power supply circuit 44 generates the gate voltage VEEG and the gate high voltage VDDG at the correct timing.

In summary, the start protection circuit of the gate driver of the present invention comprises a detection circuit and a switch. The detection circuit is configured to detect a gate low voltage to generate a control signal. The switch is electrically connected to the detecting circuit and controlled by the control signal for transmitting a gate high voltage. The detecting circuit first outputs the gate low voltage and detects whether the gate low voltage reaches a predetermined level. When the gate low voltage reaches the predetermined level, the detecting circuit turns on the switch to output the gate high voltage.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 40. . . LCD Monitor

12, 42. . . System board

14, 44. . . Power circuit

16, 46. . . Display panel

18, 48. . . Gate driver

181, 481. . . Shift register

182, 482. . . Potential converter

183, 483. . . Output buffer

441. . . DC/DC converter

442. . . Charge pump

49. . . Start protection circuit

491. . . Detection circuit

492. . . switch

710~750. . . step

VCC. . . voltage

VDDA. . . Voltage

VEEG. . . Gate low voltage

VDDG. . . Gate high voltage

VG. . . Gate control voltage

CPV, UD, XON, OE, STV. . . Display signal

S1. . . Switch control signal

T1. . . first timing

T2. . . Second time

T3. . . Third time

Figure 1 is a schematic illustration of a prior art liquid crystal display.

Figure 2 is a waveform diagram of the voltage at which the gate driver is activated.

Figure 3 is a diagram showing the error in the voltage timing at the start of the gate driver.

Figure 4 is a schematic view showing a first embodiment of the liquid crystal display of the present invention.

Figure 5 is a timing diagram of the voltage at which the gate driver is turned on.

Figure 6 is a schematic diagram of the startup protection circuit of Figure 4.

Figure 7 is a flow chart showing the operation of the start-up protection circuit of Figure 4.

Figure 8 is a schematic view showing a second embodiment of the liquid crystal display of the present invention.

Figure 9 is a schematic view showing a third embodiment of the liquid crystal display of the present invention.

40. . . LCD Monitor

42. . . System board

44. . . Power circuit

46. . . Display panel

48. . . Gate driver

481. . . Shift register

482. . . Potential converter

483. . . Output buffer

49. . . Start protection circuit

Claims (15)

A start-up protection circuit for a gate driver includes: a detection circuit for transmitting and detecting a gate low voltage to generate a control signal; and a switch electrically connected to the detection circuit, the switch is Controlled by the control signal for transmitting a gate high voltage; wherein the detecting circuit is electrically connected to a charge pump to receive a gate low voltage generated by the charge pump; The charge pump is connected to receive a gate high voltage generated by the charge pump. The start protection circuit of the gate driver according to claim 1, wherein the detection circuit is configured to detect whether the gate low voltage reaches a predetermined level. The start protection circuit of the gate driver of claim 2, wherein the opening is turned on when the gate low voltage reaches the predetermined level. The start-up protection circuit of the gate driver of claim 1, wherein the detection circuit is electrically connected to the charge pump via a first delay circuit; the open relationship is electrically connected to the charge pump via a second delay circuit. The start protection circuit of the gate driver according to claim 1, wherein the detection circuit is electrically connected to a level shifter to lower the gate voltage Transmitted to the potential converter; the open relationship is electrically connected to the potential converter to transmit the gate high voltage to the potential converter. A method for protecting a startup voltage of a gate driver includes: receiving a gate low voltage and a gate high voltage; outputting the gate low voltage; detecting whether the gate low voltage reaches a predetermined level; When the gate low voltage reaches the preset level, the gate high voltage is output after a predetermined time. The method of claim 6, further comprising: providing a power supply voltage; and generating the gate low voltage and the gate high voltage according to the power supply voltage. The method of claim 6, further comprising: transmitting the gate low voltage and the gate high voltage to the gate driver. A gate driver includes: a start protection circuit for transmitting a gate low voltage, and outputting a gate high voltage when the gate low voltage reaches a predetermined level; and shifting the register to use Receiving a display signal; a potential converter electrically connected to the shift register, a detecting circuit and a switch for generating the signal according to the display signal, the gate low voltage and the gate high voltage Generating a gate control signal, wherein the detection circuit is electrically connected to a charge pump to receive a gate low voltage generated by the charge pump; the open circuit is electrically connected to the charge pump to receive the charge pump a gate high voltage; and an output buffer electrically connected to the potential converter for outputting the gate control signal. The gate driver of claim 9, wherein the boot protection circuit comprises: a detecting circuit for transmitting and detecting whether the gate low voltage reaches the predetermined level to generate the control signal; A switch is electrically connected to the detecting circuit, and the switch is controlled by the control signal for transmitting the gate high voltage. The gate driver of claim 10, wherein the opening is turned on when the gate low voltage reaches the predetermined level. The gate driver of claim 9, wherein the detecting circuit is electrically connected to the charging pump via a first delay circuit; the open relationship is electrically connected to the charging pump via a second delay circuit. A liquid crystal display comprising: a display panel; a start protection circuit electrically connected to the display panel for transmitting a gate low voltage, and outputting a gate high when the gate low voltage reaches a predetermined level Voltage; a gate driver electrically connected to the detecting circuit and the switch for driving the liquid crystal display panel according to the gate low voltage and the gate high voltage; and a charge pump for generating the gate low voltage And the gate is high voltage. The liquid crystal display of claim 13, wherein the activation protection circuit comprises: a detection circuit for transmitting and detecting whether the gate low voltage reaches the predetermined level to generate a control signal; and a switch And electrically connected to the detecting circuit, the switch is controlled by the control signal for transmitting the gate high voltage. The liquid crystal display of claim 14, wherein the opening is turned on when the gate low voltage reaches the predetermined level.