TWI411993B - Flat display apparatus - Google Patents

Abstract

A timing control circuit includes a gate voltage supply module, a control module and a gate voltage adjusting module. The gate voltage supplying module generates and outputs a gate voltage. The control module outputs at least one control signal following a variation of time during a period for displaying a frame of image. The gate voltage adjusting module is electrically connected both to the gate voltage supply module and the control module, and adjusts a change rate of an original gate voltage on a junction between the gate voltage adjusting module and the gate voltage supply module according to the at least one control signal. The change rate of the original gate voltage is gradually decreasing or increasing, and the gate voltage output is relative to the original gate voltage. A flat display apparatus using the timing control circuit is also provided.

Description

Flat display device

The present invention relates to a flat display device, and more particularly to a flat display device having a timing control circuit.

With the development of flat panel display technology, consumers are paying more and more attention to the picture quality of flat display devices. Among them, one of the factors affecting the quality of this picture is the uniformity of the gate voltage of the thin film transistor.

1 is a schematic view of a conventional flat display device. Referring to FIG. 1 , the conventional flat display device 100 includes at least a gate voltage supply circuit module 110 , a gate driving circuit 120 , and a display panel 130 . The display panel 130 includes a plurality of scanning lines GL ₁ to GL _m , a plurality of data lines DL ₁ to DL _n and a plurality of pixels P _1,1 to P _m,n . In order to clearly express the relationship between each pixel, the scan line and the data line, the pixel P _{x, y} is defined as a pixel electrically coupled to the scan line GL _x and the data line DL _y , and 1 ≦ x ≦ m, 1 ≦y≦n. For example, the pixel P _1,1 is a pixel electrically coupled to the scan line GL ₁ and the data line DL ₁ , and so on. Specifically, the gate voltage supply circuit module 110 outputs the gate voltage V1 to the gate driving circuit 120, and the gate driving circuit 120 generates the pulse scanning signal A according to the gate voltage V1, and sequentially transmits the pulse scanning signal A. In the scan lines GL ₁ GL GL _m , whether the pixels P _x,1 -P _x,n electrically coupled to the same scan line GL _x are controlled to receive display data from their respective corresponding data lines DL ₁ -DL _n . Therefore, the pulse scanning signal A is related to the gate voltage V1.

Since the pulse scanning signal A is transmitted to the pixels P _x,1 ~ P _x,n electrically coupled to the same scanning line GL _x by a different distance, the pulse scanning signal A is affected by the parasitic resistance and capacitance of the wire during the transmission. There is a distortion phenomenon. Thus, each pixel P _{x, y} of the received pulses will scan signal because the distance A signal transmission vary, thereby affecting the picture quality. To reduce this phenomenon, the falling edge of the pulse scanning signal A will have a chamfered angle V1a. However, this method only improves the distortion phenomenon of the pulse scanning signal A of the pixels P _x,1 ~P _x,n electrically coupled to the same scanning line GL _x , that is, it can only improve the signal distortion phenomenon in the horizontal direction. In fact, the pulse scanning signal A received by the scanning lines GL ₁ to GL _m from the gate driving circuit 120 may also be distorted due to the difference in the distance of the signal transmission, but the foregoing manner cannot solve the vertical direction. Signal distortion. Therefore, the picture quality in the vertical direction is still prone to color difference.

The present invention provides a timing control circuit for a flat display device to provide a gate voltage that can adjust the chamfer slope of the pulse scan signal.

The invention further provides a display panel to improve picture quality.

The invention provides a timing control circuit for a flat display device, which comprises a gate voltage supply circuit module, a control circuit module and a gate voltage adjustment circuit module. The gate voltage supply circuit module is configured to generate and output a gate voltage. The control circuit module outputs at least one control signal at a time when the plane display device displays one frame of the screen, depending on the time at which the frame screen is displayed. The gate voltage adjustment circuit module is electrically coupled to the control circuit module and the gate voltage supply circuit module. The gate voltage adjustment circuit module determines how to adjust the change speed of the original gate voltage electrically coupled to the gate voltage supply circuit module according to the control signal outputted by the control circuit module. Moreover, the rate of change of the original gate voltage is gradually slowed or gradually increased with time, and the gate voltage is related to the original gate voltage.

In an embodiment of the invention, the gate voltage adjusting circuit module includes a plurality of resistors connected in parallel and a plurality of switches. One end of the parallel resistors is electrically coupled to the original gate voltage. Each switch is electrically coupled between one of the parallel resistors and the preset potential, and the control signal output by the control circuit module determines whether to be turned on. Wherein, when either switch is turned on, a discharge path corresponding to the original gate voltage is provided to gradually decrease the original gate voltage.

In an embodiment of the invention, the gate voltage adjustment circuit module includes a first resistor, a second resistor, a third resistor, a first switch, and a second switch. The first resistor and the second resistor are electrically coupled to the original gate voltage, and the third resistor is electrically coupled between the original gate voltage and the preset potential. The first switch is electrically coupled between the other end of the first resistor and the preset potential, and the second switch is electrically coupled between the other end of the second resistor and the preset potential. The at least one control signal output by the control circuit module is used to control whether the first switch and the second switch are turned on.

In an embodiment of the invention, the gate voltage adjustment circuit module includes a variable resistor. The variable resistor is electrically coupled between the original gate voltage and the preset potential, and the variable resistor receives at least one control signal output by the control circuit module, and determines the resistance of the variable resistor according to the received control signal. value.

The present invention further provides a display panel including a plurality of data lines, a plurality of scan lines, and a plurality of pixels. These data lines are each used to provide display information. The scan lines are arranged in a first direction, and the scan lines are used to transmit a pulse scan signal. Moreover, each pixel is electrically coupled to one of the scan lines and one of the data lines. Wherein, the pulse scanning signals respectively transmitted by the scanning lines have chamfered edges at the falling edges, and the slopes of the chamfers change toward the same trend along the first direction.

In an embodiment of the invention, the display panel further includes a timing control circuit. The timing control circuit comprises a gate voltage supply circuit module, a control circuit module and a gate voltage adjustment circuit module. The gate voltage supply circuit module is configured to generate and output a gate voltage. The control circuit module outputs at least two control signals in a period in which the plane display device displays one frame of the screen, depending on the time at which the frame screen is displayed. The gate voltage adjustment circuit module is electrically coupled to the control circuit module and the gate voltage supply circuit module. The gate voltage adjustment circuit module determines how to adjust the change speed of the original gate voltage electrically coupled to the gate voltage supply circuit module according to the control signal outputted by the control circuit module. Moreover, the gate voltage is the limit of the pulse scan signal.

In the present invention, the gate voltage adjusting circuit module can determine how to adjust the changing speed of the original gate voltage according to the control signal outputted by the control circuit module, thereby compensating for providing the gate voltage to different scan lines. The effect of parasitic resistance and capacitance effects in different lengths of signal transmission paths. Therefore, the flat display device of the present invention can reduce the image quality defect caused by the pulse scanning signal unevenness in the vertical direction.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

2 is a schematic diagram of a flat display device according to an embodiment of the present invention, and FIG. 3 is a schematic diagram of the timing control circuit and the gate driving circuit of FIG. Referring first to FIG. 2, the flat display device 200 of the present embodiment includes a display panel 210. The display panel 210 includes a plurality of scanning lines GL ₁ to GL _m , a plurality of data lines DL ₁ to DL _{n ,} and a plurality of pixels P _1,1 to P _m,n . In the present embodiment, for example, 900*1600 pixels, 900 scanning lines GL ₁ to GL _900, and 1600 data lines DL ₁ to DL _{1600 are taken} as an example. In order to clearly express the relationship between each pixel, the scan line and the data line, the pixel P _{x, y} is defined as a pixel electrically coupled to the scan line GL _x and the data line DL _y , and 1 ≦ x ≦ 900, 1 ≦y≦1600. For example, the pixel P _1,2 is a pixel electrically coupled to the scan line GL ₁ and the data line DL ₂ , and so on. The data lines DL ₁ ~ DL _{1600 are} used to provide display materials. The scan lines GL ₁ to GL ₉₀₀ are arranged along the first direction D1 and are used to transmit the pulse scan signals G ₁ to G ₉₀₀ . The pulse scanning signals G ₁ to G ₉₀₀ respectively transmitted by the scanning lines GL ₁ to GL ₉₀₀ have a chamfering angle Ga/Gb/Gc at the falling edge, and the slope of each chamfer varies along the first direction D1 toward the same trend. , for example, to gradually slow down or gradually increase.

In the above, in order to change the slope of each of the chamfers of the pulse scanning signals G ₁ to G ₉₀₀ , the planar display device 200 of the present embodiment further includes a timing control circuit 220 . Referring to FIG. 2 and FIG. 3 together, the timing control circuit 220 includes a gate voltage supply circuit module 221, a control circuit module 222, and a gate voltage adjustment circuit module 223. The gate voltage supply circuit module 221 generates and outputs a gate voltage Vgh. The control circuit module 222 outputs the control signal CT at least once during the display of the one-frame picture by the flat display device 200. The gate voltage adjustment circuit module 223 is electrically coupled to the control circuit module 222 and the gate voltage supply circuit module 221 . The gate voltage adjustment circuit module 223 determines how to adjust the change speed of the original gate voltage (the voltage of the node R) according to the control signal CT outputted by the control circuit module 222. Moreover, the rate of change of the original gate voltage is gradually slowed or gradually increased with time, the gate voltage Vgh is related to the original gate voltage, and the gate voltage Vgh is the limit value of the pulse scanning signals G ₁ to G ₉₀₀ .

Specifically, the gate voltage adjustment circuit module 223 includes, for example, a plurality of parallel resistors and a plurality of switches. In the present embodiment, for example, three resistors and two switches are taken as an example, but it is not limited thereto. this invention. In order to clarify the present invention, it is assumed here that the three resistors are a first resistor R1, a second resistor R2, and a third resistor R3, respectively, and the two switches are a first switch W1 and a second switch W2, respectively. The first resistor R1, the second resistor R2 and the third resistor R3 are electrically coupled to the original gate voltage, and the third resistor R3 is electrically coupled between the original gate voltage and the preset potential D. The first switch W1 is electrically coupled between the other end of the first resistor R1 and the preset potential D, and the second switch W2 is electrically coupled between the other end of the second resistor R2 and the preset potential D.

In the above, the control signal CT outputted by the control circuit module 222 is used to control whether the first switch W1 and the second switch W2 are turned on. In the present embodiment, the control circuit module 222 is exemplified by the secondary control signals CT1 and CT2. When different switches are turned on, a discharge path with different original gate voltages is provided to gradually reduce the original gate voltage. (or rise).

Referring to FIG. 2, FIG. 3 and FIG. 4, the control circuit module 222 provides a start signal ST to the gate drive circuit 230 to activate the gate drive circuit 230. The control circuit module 222 further provides a time control signal Y to the gate voltage supply circuit module 221 to determine the discharge time t of the original gate voltage. Moreover, the control signals CT1 and CT2 outputted by the control circuit module 222 are respectively used to control whether the first switch W1 or the second switch W2 is turned on, thereby providing a discharge path corresponding to the original gate voltage, and the original gate voltage is made. decreasing gradually. In addition, the control circuit module 222 further provides a clock signal CLK to the gate driving circuit 230, so that the gate driving circuit 230 sequentially transmits the pulse scanning signals G ₁ to G ₉₀₀ to the scanning lines GL ₁ to GL ₉₀₀ .

In more detail, the control signals CT1, CT2 are changed with time during one frame display period, and thus the amount of decrease of the original gate voltage is different depending on whether the first switch W1 or the second switch W2 is turned on. In the present embodiment, the control signals CT1, CT2 are changed three times in total during one frame display period. In order to clearly explain the design concept of this specification in conjunction with the drawings, the period in which the clock signal CLK controls the scanning lines GL ₁ to GL ₃₀₀ , GL ₃₀₁ GL GL ₆₀₀ , and GL ₆₀₁ GL _{900 is} defined as the first period I, Second period II, third period III. First, during the period when the clock signal CLK controls the scan lines GL ₁ to GL ₃₀₀ , the control signals CT1 and CT2 are at a high potential, and the first switch W1 and the second switch W2 are controlled to be turned on. At this time, the first resistor R1 and the second resistor are turned on. R2 is turned on and connected in parallel with the third resistor R3, and the time control signal Y is used to determine the discharge time t of the original gate voltage. Thus, after the original gate voltage is processed by the gate voltage supply circuit module 221, the gate voltage formed is as shown by the gate voltage Vgh of the first period I of FIG. Then, the gate driving circuit 230 sequentially forms the pulse scanning signals G ₁ to G ₃₀₀ according to the gate voltage Vgh and the clock signal CLK, and transmits the signals to the scanning lines GL ₁ to GL ₃₀₀ . Thus, the pulse scanning signal G ₁ received by the scanning line GL ₁ is as shown in FIG. 4, and has a chamfering Ga at its falling edge.

In the second period, the control signal CT1 is high and the control signal CT2 is low, so the first switch W1 is turned on but the second switch W2 is not turned on, so that the first resistor R1 is turned on and the third resistor R3 is turned on. Parallel, thereby reducing the amount of discharge of the original gate voltage during the discharge time t. Therefore, when the clock signal CLK controls the scanning lines GL ₃₀₁ to GL ₆₀₀ , respectively, the gate voltage input to the gate driving circuit 230 is as shown by the gate voltage Vgh of the second period II of FIG. 4, and the discharge rate is relatively high. Alleviate. Then, when the clock signal CLK controls the scan lines GL ₆₀₁ GL GL ₉₀₀ , respectively, the control signals CT1, CT2 control the first switch W1 and the second switch W2 to be non-conducting, and the discharge amount of the original gate voltage during the discharge time t As a result, the slope of the chamfering Gc of the pulse scanning signal G601 is smaller than the slope of the chamfering angle Gb of the pulse scanning signal G301.

In addition, the gate driving circuit 230 sequentially transmits the pulse scanning signals G ₁ G G ₉₀₀ to the scanning lines GL ₁ -GL ₉₀₀ according to the clock signal CLK provided by the control circuit module 222, thereby controlling the electrical coupling to the same Whether the pixels P _x,1 to P _{x, 1600} in the scanning line GL _x receive display data from the corresponding data lines DL ₁ to DL ₁₆₀₀ . Among them, x≦900. Since the gate driving circuit 230 adjusts the pulse scanning signals G ₁ to G ₉₀₀ according to the gate voltage Vgh, the pulse scanning signals G ₁ to G _{900 are} related to the gate voltage Vgh. When the gate voltage supply circuit module 221 changes with time, a gate voltage Vgh as shown in FIG. 4 is generated, and the amount of voltage change during the discharge time t changes with the same trend with time. Therefore, the chamfering angle Ga/Gb/Gc of the pulse scanning signals G ₁ to G ₉₀₀ input to the different scanning lines GL ₁ to GL ₉₀₀ also changes in accordance with the amount of change in the gate voltage Vgh. In other words, when the gate driving circuit 230 sequentially supplies the pulse scanning signals G ₁ to G ₉₀₀ to the different scanning lines GL ₁ to GL ₉₀₀ , the pulse scanning signals G ₁ to G _{900 are} adjusted by adjusting the changing speed of the original gate voltage. The slope of the chamfer varies with the signal transmission path of different lengths, thereby reducing the effects of parasitic resistance and capacitance effects in different lengths of signal transmission paths.

It is worth mentioning that the number of changes of the control signal CT during the display period of one frame can also be changed according to the design requirements. Please refer to FIG. 3 and FIG. 5. In another embodiment, the period, the control signal CT1, CT2 number of changes may be one, so that the input to the scanning lines GL ₁ ~ GL scan signal falling edge pulse ₉₀₀ having a different cut in a two-screen display Angle slope.

In addition, the resistance values of the multiple resistors can also be different depending on the design requirements. Together with the changes of the control signals CT1 and CT2, the chamfer slope of the pulse scanning signal can be varied according to the design requirements. Referring to FIG. 3 and FIG. 6, in an embodiment, the resistance value of the first resistor is smaller than the resistance value of the second resistor, and the number of changes of the control signals CT1, CT2 is three times. The pulse scanning signals G ₁ "~G ₂₂₅ ", G _{226 『} ~G ₅₀₀ ”, G ₅₀₁ ”~G ₇₇₅ ”, G ₇₇₆ ”~G ₉₀₀ ” are respectively controlled by the switching of the first resistor and the second resistor. The chamfering angles are Ga", Gb", Gc", and Gd" to reduce the difference in the pulse scanning signals received by each pixel due to the different signal transmission lengths, thereby improving the picture quality.

It should be noted that although the gate voltage adjusting circuit module 223 of the above embodiment is exemplified by a plurality of parallel resistors and a plurality of switches, one of the spirits of the present invention is to use a change in resistance to change the pulse scanning signal. The chamfer slope. In other embodiments, the design may be changed according to the use requirements, such as using a variable resistor and electrically coupling between the original gate voltage and the preset potential D, and outputted by the control circuit module 222. The control signal CT determines the resistance value of the variable resistor. In addition, the change of the potential of the control signals CT1 and CT2, that is, the change of the chamfer slope of the pulse scanning signal is not limited to be changed in the equal time interval as in the above embodiment (the screen is equally divided). In other embodiments, the change may also be used. Change the design as needed.

In summary, in the flat display device of the present invention, the gate voltage adjusting circuit module can determine how to adjust the changing speed of the original gate voltage according to the control signal outputted by the control circuit module, thereby compensating for the gate The effect of parasitic resistance and capacitance effects in different lengths of signal transmission paths when the pole voltage is supplied to different scan lines. Therefore, the flat display device of the present invention can reduce the image quality defect caused by the gate voltage non-uniformity in the vertical direction.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100, 200. . . Flat display device

110. . . Gate voltage supply circuit module

120. . . Gate drive circuit

130, 210. . . Display panel

GL ₁ ~GL _m , GL _x , GL ₁ ~GL ₉₀₀ . . . Scanning line

DL ₁ ~ DL _n , DL _y , DL ₁ ~ DL ₁₆₀₀ . . . Data line

P _1,1 ~P _m,n , P _x,y ,P _x,1 ~P _x,n . . . Pixel

220. . . Timing control circuit

221. . . Gate voltage supply circuit module

222. . . Control circuit module

223. . . Gate voltage adjustment circuit module

230. . . Gate drive circuit

CT, CT1, CT2. . . Control signal

D. . . Preset potential

D1. . . First direction

R. . . node

R1. . . First resistance

R2. . . Second resistance

R3. . . Third resistance

W1, W2. . . switch

A, G ₁ ~ G ₉₀₀ , G ₁ '~G ₉₀₀ ', G ₁ ”~G ₉₀₀ ”. . . Pulse scan signal

CLK. . . Clock signal

ST. . . Start signal

V1, Vgh. . . Gate voltage

V1a, Ga, Gb, Gc, Ga', Gb', Gc', Ga", Gb", Gc", Gd". . . Chamfering

Y. . . Time control signal

t. . . Discharge time

I, I’, I"...first period

II, II', II"...second period

III, III"...the third period

IV"...fourth period

1 is a schematic view of a conventional flat display device.

2 is a schematic diagram of a flat display device according to an embodiment of the present invention.

3 is a schematic diagram of the timing control circuit and the gate driving circuit of FIG. 2.

Figure 4 is a timing diagram of the signal in Figure 3.

Figure 5 is a timing diagram of signals in accordance with another embodiment of the present invention.

Figure 6 is a timing diagram of signals in accordance with yet another embodiment of the present invention.

221. . . Gate voltage supply circuit module

222. . . Control circuit module

223. . . Gate voltage adjustment circuit module

230. . . Gate drive circuit

CT, CT1, CT2. . . Control signal

D. . . Preset potential

R1. . . First resistance

R2. . . Second resistance

R3. . . Third resistance

W1, W2. . . switch

G. . . Pulse scan signal

CLK. . . Clock signal

ST. . . Start signal

Vgh. . . Gate voltage

Ga, Gb, Gc. . . Chamfering

R. . . node

Y. . . Time control signal

Claims (8)

A timing control circuit for a flat display device, comprising: a gate voltage supply circuit module for generating and outputting a gate voltage; and a control circuit module, wherein the display device displays a frame of the screen, The gate signal voltage adjustment circuit module is electrically coupled to the control circuit module and the gate voltage supply circuit module, and the gate voltage adjustment circuit module is configured to output the control signal at least once. Determining, according to the control signal outputted by the control circuit module, how to adjust a change speed of an original gate voltage electrically coupled to the gate voltage supply circuit module, wherein the original gate voltage changes speed The adjustment of time is gradually slowed or gradually increased, and the gate voltage is related to the original gate voltage. The timing control circuit of claim 1, wherein the gate voltage adjustment circuit module comprises: a plurality of parallel resistors, one end electrically coupled to the original gate voltage; and a plurality of switches, each The switches are electrically coupled between one of the parallel resistors and a predetermined potential, and the switches are controlled by the control signals output by the control circuit module, wherein any of the switches are When turned on, a discharge path corresponding to the original gate voltage is provided to gradually decrease the original gate voltage. The timing control circuit of claim 1, wherein the gate voltage adjustment circuit module comprises: a first resistor, one end electrically coupled to the original gate voltage; and a second resistor, one end electrically The third resistor is electrically coupled between the original gate voltage and a predetermined potential; a first switch is electrically coupled to the other end of the first resistor and And a second switch electrically coupled between the other end of the second resistor and the predetermined potential, wherein at least one control signal output by the control circuit module is used to control Whether the first switch and the second switch are turned on. The timing control circuit of claim 1, wherein the gate voltage adjustment circuit module comprises: a variable resistor electrically coupled between the original gate voltage and a predetermined potential, The variable resistor receives at least one control signal output by the control circuit module, and determines a resistance value of the variable resistor according to the received control signal. A display panel includes: a plurality of data lines each for providing display data; a plurality of scan lines arranged along a first direction, and each of the scan lines is configured to transmit a pulse scan signal; a plurality of pixels, each One of the pixels is electrically coupled to one of the scan lines and one of the data lines; and a timing control circuit includes: a gate voltage supply circuit module that generates and outputs a gate voltage to the pixels Scan line a control circuit module, wherein at least one control signal is outputted according to a different time of displaying the frame picture during a display of the frame picture; and a gate voltage adjustment circuit module electrically coupled to the control a circuit module and the gate voltage supply circuit module, the gate voltage adjustment circuit module determines how to adjust the electrical coupling with the gate voltage supply circuit module according to the control signals output by the control circuit module a rate of change of the original gate voltage of the junction, wherein the pulse scan signals respectively transmitted by the scan lines have a chamfer angle at the falling edge, and the slope of each chamfer varies along the first direction toward the same trend. The gate voltage is the limit of the pulse scan signal. The display panel of claim 5, wherein the gate voltage adjustment circuit module comprises: a plurality of parallel resistors, one end electrically coupled to the original gate voltage; and a plurality of switches, each The switches are electrically coupled between one of the parallel resistors and a predetermined potential, and the switches are controlled by the control signals output by the control circuit module, wherein any of the switches are turned on. A discharge path corresponding to the original gate voltage is provided to gradually decrease the original gate voltage. The display panel of claim 5, wherein the gate voltage adjusting circuit module comprises: a first resistor, one end electrically coupled to the original gate voltage; and a second resistor electrically coupled at one end Connected to the original gate voltage; a third resistor electrically coupled between the original gate voltage and a predetermined potential; a first switch electrically coupled between the other end of the first resistor and the predetermined potential; and a The second switch is electrically coupled between the other end of the second resistor and the predetermined potential, wherein at least one control signal output by the control circuit module is used to control the first switch and the second switch Whether it is conductive. The display panel of claim 5, wherein the gate voltage adjustment circuit module comprises: a variable resistor electrically coupled between the original gate voltage and a predetermined potential, the variable The resistor receives at least one control signal output by the control circuit module, and determines a resistance value of the variable resistor according to the received control signal.