TWI384755B - Shift register improving image residual at power failure - Google Patents

Description

A shift register that can improve the afterimage of power failure

The present invention relates to a shift register for a liquid crystal display, and more particularly to a shift register for improving image sticking during power-off.

At present, the main reason for the shutdown of the liquid crystal display is that when the power supply of the liquid crystal display is turned off, the discharge voltage of the pixel of the display panel is too slow, so that the residual charge after the shutdown cannot be released in time and remains in the liquid crystal capacitor, resulting in shutdown. After the LCD monitor has residual images, it is the afterimage.

Please refer to FIG. 1 , which is a schematic diagram of a prior art liquid crystal display capable of eliminating the afterimage of shutdown. The liquid crystal display 10 includes a power supply 11 , a voltage detector 12 , a display panel 13 , a gate driver 14 , and a source driver 15 . The power supply 11 supplies a power supply voltage VCC to the source driver 15 and the gate driver 14. At the same time, the power supply 11 also supplies a power supply voltage VCC to the voltage detector 12, and the voltage detector 12 compares the power supply voltage VCC with a reference voltage. When the liquid crystal display 10 is turned off, the power supply voltage VCC drops to a level lower than the reference voltage. At this time, the voltage detector 12 sends a control signal XAO to the gate driver 14, and the gate driver 14 receives the control signal XAO. The thin film transistors on the display panel 13 are all turned on, so that the residual charge is effectively released, so that the shutdown afterimage can be improved.

Please refer to FIG. 2, which is a schematic diagram of the gate signal generated by the shift register of the gate driver. The gate driver 14 uses the shift register 16 to generate a sequential gate signal to turn on the thin film transistor on the display panel. In the second figure, the PMOS shift register is taken as an example. When the gate signal is at a low level, the thin film transistor on the gate line will be turned on. When the liquid crystal display 10 is turned off, after the gate driver 14 receives the control signal XAO, all the gate signals will output a low level to turn on the thin film transistor on the gate line. However, assuming that the liquid crystal display 10 has a non-shutdown power-off condition at the timing t1, the gate signal outputted by the shift register 16 of each stage will remain at a high level, so the display panel 13 will display the image of the previous picture. .

In summary, the liquid crystal display uses an external voltage detector to detect the level of the power supply voltage. When detecting that the power supply voltage is lower than the reference voltage level, the voltage detector outputs a control signal to the gate. The pole driver is used to activate the liquid crystal display to eliminate the phenomenon of shutdown image sticking. At this time, the gate driver will turn on all the thin film transistors of the display panel to release the residual charge, so as to eliminate the shutdown afterimage. However, when the liquid crystal display is powered off without being turned off, the gate driver does not open all of the thin film transistors on the display panel. Therefore, there is still residual charge on the display panel and the image of the previous screen can be seen, which causes inconvenience to the user.

Accordingly, it is an object of the present invention to provide a shift register that can improve image sticking during power down.

The present invention provides a shift register comprising a plurality of stages of electrically connected shifting units, wherein each shifting unit comprises a boosting circuit, a lifting drive circuit, a pull-down circuit, a pull-down drive circuit, and a power-off Control circuit. The boosting circuit is configured to output a first voltage level to an output node according to a voltage of a driving node. The lifting drive circuit is electrically connected to the driving node for driving the lifting circuit according to a voltage of an output node of the shifting unit of the upper stage. The pull-down circuit is electrically connected to the output node, and is configured to output a second voltage level to the output node according to a voltage of an output node of the shifting unit of the next stage. The pull-down driving circuit is electrically connected to the driving node, and is configured to output the second voltage level to the driving node according to a voltage of the output node. The power-off control circuit is configured to turn off the boost circuit and the pull-down circuit according to a first power signal and a second power signal, and output the first voltage level to the output node.

Please refer to FIG. 3, which is a display of the shift register of the present invention. In the embodiment of the present invention, the description of the PMOS shift register is taken as an explanation. The shift register 20 includes a plurality of stages of electrically connected shifting units, each stage shifting unit includes a boosting circuit 21, a boosting driving circuit 22, a pull-down circuit 23, a pull-down driving circuit 24, and a power-off control circuit. 25. The boosting circuit 21 outputs a first voltage level to the output node Gn according to the voltage of the driving node Q. The boost drive circuit 22 drives the boost circuit 21 in accordance with the voltage of the output node Gn-1 of the shift stage unit of the previous stage. The pull-down circuit 23 outputs a second voltage level to the output node Gn according to the voltage of the output node Gn+1 of the shifting unit of the next stage. The pull-down driving circuit 24 outputs a second voltage level to the driving node Q according to the voltage of the output node Gn. The power-off control circuit 25 turns off the boost circuit 21 and the pull-down circuit 23 according to the first power signal XDON and the second power signal XDONB, and outputs a first voltage level to the output node Gn. The boost circuit 21 includes a first transistor M1. The pull-down circuit 23 includes a second transistor M2. The power down control circuit 25 includes a control isolation circuit and a voltage output circuit. The control isolation circuit includes a third transistor M3 and a fifth transistor M5. The voltage output circuit includes a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7. The boost drive circuit 22 includes an eighth transistor M8 and a ninth transistor M9. The pull-down drive circuit 24 includes a tenth transistor M10 to a seventeenth transistor M17.

The first end of the first transistor M1 is used to receive the clock signal CLK, the control end of the first transistor M1 is used to receive the voltage of the driving node Q, and the second end of the first transistor M1 is electrically connected to the output node Gn. . The first end of the second transistor M2 is electrically connected to the output node Q, and the control end of the second transistor M2 is used to receive the voltage of the output node Gn+1 of the next stage shifting unit, and the second transistor M2 is second. The terminal is used to receive the second voltage level. The first end of the third transistor M3 is electrically connected to the driving node Q, the control end of the third transistor M3 is used to receive the first power signal XDON, and the second end of the third transistor M3 is electrically connected to the first electrode The control end of crystal M1. The first end of the fourth transistor M4 is used to receive the second voltage level, the control end of the fourth transistor M4 is used to receive the second power signal XDONB, and the second end of the fourth transistor M4 is electrically connected to the first end. The control terminal of the transistor M1. The first end of the fifth transistor M5 is electrically connected to the control end of the second transistor M2, the control end of the fifth transistor M5 is used to receive the first power signal XDON, and the second end of the fifth transistor M5 is electrically Connected to the output node Gn+1 of the next stage shifting unit. The first end of the sixth transistor M6 is electrically connected to the control end of the second transistor M2, the control end of the sixth transistor M6 is used to receive the second power signal XDONB, and the second end of the sixth transistor M6 is used Receiving the second voltage level. The first end of the seventh transistor M7 is used to receive the second power signal XDONB, the control end of the seventh transistor M7 is electrically connected to the first end of the seventh transistor M7, and the second end of the seventh transistor M7 is electrically The connection is made to the output node Gn. The first end of the eighth transistor M8 is electrically connected to the output node Gn-1 of the upper stage shifting unit, and the control end of the eighth transistor M8 is electrically connected to the first end of the eighth transistor M8. The first end of the ninth transistor M9 is electrically connected to the second end of the eighth transistor M8, and the control end of the ninth transistor M9 is electrically connected to the control end of the eighth transistor M8, and the ninth transistor M9 The second end is electrically connected to the driving node Q. In the present embodiment, the tenth transistor M10 and the sixteenth transistor M16 receive the gate low level voltage VGL. In another embodiment of the present invention, the pull-down driving circuit 25 can also be controlled by using complementary clock signals CLK and XCLK, that is, the tenth transistor M10 receives the clock signal CLK, and the sixteenth transistor M16 receives the clock. Signal XCLK.

Please refer to FIG. 4, and FIG. 4 is an operation waveform diagram of the shift register of FIG. STV is a vertical start signal, CLK and XCLK are complementary clock signals, XDON and XDONB are power signals, and G1~G4 are gate signals. When the power supply is stable, the signal XDON is at a low level, and the signal XDONB is at a high level, so the third transistor M3 and the fifth transistor M5 are turned on, and the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are turned on. shut down. Therefore, the shift register 20 can operate normally. When the primary output node Gn-1 is at a low level before the shift register 20, the eighth transistor M8 and the ninth transistor M9 are turned on, and the low level voltage is transmitted to the gate of the first transistor M1. A transistor M1 is turned on, so the output node Gn outputs a low level voltage of the clock signal CLK. When the output node Gn+1 of the lower stage of the shift register 20 is at a low level, the second transistor M2 is turned on, and the gate high level voltage VGH is transmitted to the output node Gn. At the timing t1, the power signal XDON is converted from the low level to the high level, indicating that the power supply is interrupted, and the power-off control circuit starts to operate. When the power signal XDON is at a high level, the third transistor M3 and the fifth transistor M5 are turned off, and the power signal XDONB is at a low level, so the fourth transistor M4, the sixth transistor M6, and the seventh transistor are M7 is turned on. Therefore, the gate high-level voltage VGH is transmitted to the control terminal of the first transistor M1 through the fourth transistor M4 to turn off the first transistor M1; the gate high-level voltage VGH is transmitted to the second through the sixth transistor M6. The control terminal of the transistor M2 turns off the second transistor M2, and the seventh transistor M7 turns on to transfer the low level of the power signal XDONB to the outgoing node Gn. In this way, when the power interruption occurs, the power-off control circuit will turn off the boost circuit and the pull-down circuit, and then transfer the low level of the power signal to the gate line to turn on all the transistors on the gate line, and write the same data. . In the case of normal power supply, the data line will output gray scale data. However, when the power supply is interrupted, all data lines will output low voltage level GND, so the LCD panel will display a white screen or black screen.

In summary, the shift register of the present invention can turn on the thin film transistors on all gate lines when the power is off, so that a white screen or a black screen is displayed on the display panel to solve the problem of image sticking. The shift register of the present invention comprises a boost circuit, a boost drive circuit, a pull-down circuit, a pull-down drive circuit and a power-off control circuit. The boosting circuit outputs a first voltage level to an output node according to a voltage of a driving node. The boost drive circuit drives the boost circuit according to the voltage of the output node of the shifting unit of the upper stage. The pull-down circuit outputs a second voltage level to the output node according to the voltage of the output node of the shifting unit of the next stage. The pull-down driving circuit outputs the second voltage level to the driving node according to the voltage of the output node. The power-off control circuit turns off the boost circuit and the pull-down circuit according to a first power signal and a second power signal, and outputs the first voltage level to the output node.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . LCD Monitor

11. . . Power Supplier

12. . . Voltage detector

13. . . Display panel

14. . . Gate driver

15. . . Source driver

16, 20. . . Shift register

twenty one. . . Pull-up circuit

twenty two. . . Pull-up drive circuit

twenty three. . . Pull-down circuit

twenty four. . . Pull-down drive circuit

25. . . Power failure control circuit

VCC. . . voltage

XAO. . . Control signal

M1~M17. . . Transistor

XDON. . . First power signal

XDONB. . . Second power signal

CLK. . . Clock signal

VGH. . . Gate high level voltage

VGL. . . Gate low level voltage

Gn. . . Output node

Q. . . Drive node

FIG. 1 is a schematic diagram of a prior art liquid crystal display capable of eliminating the afterimage of shutdown.

Figure 2 is a schematic diagram of the gate signal generated by the shift register of the gate driver.

Figure 3 is a display of the shift register of the present invention.

Figure 4 is an operational waveform diagram of the shift register of Figure 3.

20. . . Shift register

twenty one. . . Pull-up circuit

twenty two. . . Pull-up drive circuit

twenty three. . . Pull-down circuit

twenty four. . . Pull-down drive circuit

25. . . Power failure control circuit

M1~M17. . . Transistor

XDON. . . First power signal

XDONB. . . Second power signal

CLK. . . Clock signal

VGH. . . Gate high level voltage

VGL. . . Gate low level voltage

Gn. . . Output node

Q. . . Drive node

Claims (12)

A shift register comprising a plurality of stages of electrically connected shifting units, wherein each stage of shifting unit comprises: a boosting circuit for outputting a first voltage level to an output node according to a voltage of a driving node; a lifting drive circuit electrically connected to the driving node for driving the lifting circuit according to a voltage of an output node of the shifting unit of the upper stage; a pull-down circuit electrically connected to the output node for shifting according to the next stage The voltage of the output node of the unit outputs a second voltage level to the output node; the pull-down driving circuit is electrically connected to the driving node, and is configured to output the second voltage level to the driving node according to the voltage of the output node. And a power-off control circuit for turning off the boost circuit and the pull-down circuit according to a first power signal and a second power signal, and outputting the first voltage level to the output node. The shift register of claim 1, wherein the boosting circuit comprises: a first transistor having a first end for receiving a first clock signal, and a control end for receiving the driving node The voltage, and a second end are electrically connected to the output node. The shift register according to claim 2, wherein the pull-down circuit comprises: a second transistor having a first end electrically connected to the output node, and a control end for receiving the next stage shifting unit The voltage of the output node and a second terminal are used to receive the second voltage level. The shift register according to claim 3, wherein the power-off control circuit comprises: a control isolation circuit for isolating the voltage of the first transistor from receiving the driving node and isolating the control end of the second transistor Receiving a voltage of an output node of the shifting unit of the next stage; and a voltage output circuit for outputting the first voltage level to the output node. The shift register of claim 4, wherein the control isolation circuit comprises: a third transistor having a first end electrically connected to the driving node, and a control terminal for receiving the first power signal And a second end electrically connected to the control end of the first transistor; a fourth transistor having a first end for receiving the second voltage level, and a control end for receiving the second power source a signal, and a second end electrically connected to the control end of the first transistor; a fifth transistor having a first end electrically connected to the control end of the second transistor, and a control end for receiving The first power signal, and a second end electrically connected to the output node of the next stage shifting unit; and a sixth transistor having a first end electrically connected to the control end of the second transistor, The control terminal is configured to receive the second power signal, and a second terminal is configured to receive the second voltage level. The shift register according to claim 4, wherein the voltage output circuit comprises: a seventh transistor having a first end for receiving the second power signal, and a control terminal electrically connected to the first The terminal and the second end are electrically connected to the output node. The shift register of claim 3, wherein the boost drive circuit comprises: an eighth transistor having a first end electrically connected to an output node of the shifting unit of the upper stage, and a control terminal electrically connected a first end, and a second end; and a ninth transistor having a first end electrically connected to the second end of the eighth transistor, and a control end electrically connected to the eighth transistor The control end and a second end are electrically connected to the driving node. The shift register of claim 3, wherein the pull-down driving circuit comprises: a tenth transistor having a first end, a control end electrically connected to the first end, and a second end; An eleventh transistor having a first end electrically connected to the second end of the tenth transistor, a control end electrically connected to the output node of the upper stage shifting unit, and a second end for receiving a second voltage level; a twelfth transistor having a first end electrically connected to the output node, a control end electrically connected to the second end of the tenth transistor, and a second end; The thirteenth transistor has a first end electrically connected to the second end of the twelfth transistor, a control end electrically connected to the control end of the eleventh transistor, and a second end for receiving a second voltage level; a fourteenth transistor having a first end electrically connected to the driving node, a control end electrically connected to the second end of the twelfth transistor, and a second end a fifteenth transistor having a first end electrically connected to the second end of the fourteenth transistor a control terminal electrically connected to the second end of the twelfth transistor, and a second end for receiving the second voltage level; a sixteenth transistor having a first end and a control end Electrically connected to the first end, and a second end; and a seventeenth transistor having a first end electrically connected to the second end of the sixteenth transistor, and a control end electrically connected to The output node and a second end are configured to receive the second voltage level. The shift register of claim 8, wherein the first end of the tenth transistor is configured to receive the first voltage level, and the first end of the sixteenth transistor is configured to receive the first voltage Level. The shift register of claim 8, wherein the first end of the tenth transistor is configured to receive the first clock signal, and the first end of the sixteenth transistor is configured to receive a second time Pulse signal. The shift register of claim 1, wherein the first power signal and the second power signal are complementary signals to indicate a power supply drop. A gate driving circuit comprising a power-off detecting circuit and a shift register according to claim 1, wherein the power-off detecting circuit is configured to provide the first power signal and the second power signal when the power source When the voltage is interrupted, the first power signal is converted from a low level to a high level, and the second power signal is converted from the high level to the low level.