TWI263166B - Sense mechanism for microprocessor bus inversion - Google Patents
Sense mechanism for microprocessor bus inversionInfo
- Publication number
- TWI263166B TWI263166B TW093138643A TW93138643A TWI263166B TW I263166 B TWI263166 B TW I263166B TW 093138643 A TW093138643 A TW 093138643A TW 93138643 A TW93138643 A TW 93138643A TW I263166 B TWI263166 B TW I263166B
- Authority
- TW
- Taiwan
- Prior art keywords
- bus
- bits
- data
- inversion
- cycle
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microcomputers (AREA)
- Manipulation Of Pulses (AREA)
- Semiconductor Integrated Circuits (AREA)
- Measurement Of Current Or Voltage (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US54939104P | 2004-03-02 | 2004-03-02 | |
US10/946,828 US7411840B2 (en) | 2004-03-02 | 2004-09-22 | Sense mechanism for microprocessor bus inversion |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200530913A TW200530913A (en) | 2005-09-16 |
TWI263166B true TWI263166B (en) | 2006-10-01 |
Family
ID=34991485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093138643A TWI263166B (en) | 2004-03-02 | 2004-12-13 | Sense mechanism for microprocessor bus inversion |
Country Status (3)
Country | Link |
---|---|
US (1) | US7411840B2 (zh) |
CN (1) | CN1664800B (zh) |
TW (1) | TWI263166B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI570571B (zh) * | 2014-12-09 | 2017-02-11 | 英特爾公司 | 以可程式化終端階層來進行動態匯流排反相的技術 |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7406608B2 (en) * | 2004-02-05 | 2008-07-29 | Micron Technology, Inc. | Fast and compact circuit for bus inversion |
EP1856869B1 (en) * | 2005-01-20 | 2017-09-13 | Rambus Inc. | High-speed signaling systems with adaptable pre-emphasis and equalization |
US20060270113A1 (en) * | 2005-05-26 | 2006-11-30 | Cisco Technology, Inc. | Method and system for reducing simultaneous switching output noise |
US7869525B2 (en) * | 2005-08-01 | 2011-01-11 | Ati Technologies, Inc. | Dynamic bus inversion method and system |
KR100656448B1 (ko) * | 2005-11-29 | 2006-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리의 dbi 신호 생성장치 및 방법 |
DE102006015114B4 (de) * | 2006-03-31 | 2011-06-30 | Qimonda AG, 81739 | Integrierter Halbleiterspeicher mit Erzeugung von Daten und Verfahren zum Betreiben eines Halbleiterspeichers |
US7688102B2 (en) * | 2006-06-29 | 2010-03-30 | Samsung Electronics Co., Ltd. | Majority voter circuits and semiconductor devices including the same |
KR100837813B1 (ko) * | 2006-12-07 | 2008-06-13 | 주식회사 하이닉스반도체 | 반도체 집적 회로의 dbi 신호 생성 장치 및 방법 |
KR100837812B1 (ko) * | 2006-12-07 | 2008-06-13 | 주식회사 하이닉스반도체 | 반도체 집적 회로의 dbi 신호 생성 장치 및 방법 |
JP2008165494A (ja) * | 2006-12-28 | 2008-07-17 | Fujitsu Ltd | 信号制御回路および信号制御装置 |
US7668988B2 (en) | 2007-09-19 | 2010-02-23 | Via Technologies, Inc. | Data bus inversion detection mechanism |
US7501963B1 (en) * | 2007-10-17 | 2009-03-10 | Micron Technology, Inc. | Balanced data bus inversion |
US7925844B2 (en) | 2007-11-29 | 2011-04-12 | Micron Technology, Inc. | Memory register encoding systems and methods |
KR20090059838A (ko) * | 2007-12-07 | 2009-06-11 | 삼성전자주식회사 | 반도체 장치에서 데이터를 전송하는 방법, 장치 및 시스템 |
US7616133B2 (en) * | 2008-01-16 | 2009-11-10 | Micron Technology, Inc. | Data bus inversion apparatus, systems, and methods |
CN101515916A (zh) * | 2008-02-21 | 2009-08-26 | 北京京东方光电科技有限公司 | 一种实现数据传输的方法及装置 |
US8069403B2 (en) * | 2008-07-01 | 2011-11-29 | Sandisk Technologies Inc. | Majority voting logic circuit for dual bus width |
US7729166B2 (en) * | 2008-07-02 | 2010-06-01 | Mosaid Technologies Incorporated | Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same |
US8260992B2 (en) * | 2010-04-12 | 2012-09-04 | Advanced Micro Devices, Inc. | Reducing simultaneous switching outputs using data bus inversion signaling |
US8364913B2 (en) | 2010-04-29 | 2013-01-29 | SK Hynix Inc. | Semiconductor memory apparatus and data input and output method thereof |
US8405529B2 (en) * | 2011-03-11 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using bus inversion to reduce simultaneous signal switching |
US9025409B2 (en) * | 2011-08-05 | 2015-05-05 | Rambus Inc. | Memory buffers and modules supporting dynamic point-to-point connections |
US8942309B1 (en) * | 2012-05-04 | 2015-01-27 | Rambus Inc. | Signal output improvement using data inversion and/or swapping |
US9219509B1 (en) | 2012-05-04 | 2015-12-22 | Rambus Inc. | System performance improvement using data reordering and/or inversion |
WO2014146012A2 (en) * | 2013-03-15 | 2014-09-18 | Gsi Technology, Inc. | Systems and methods involving data bus inversion memory circuitry, configuration and /or operation including data signals grouped into 10 bits and/or other features |
US9385032B2 (en) * | 2013-03-15 | 2016-07-05 | Gsi Technology, Inc. | Systems and methods involving data bus inversion memory circuitry, configuration and/or operation |
US9244875B1 (en) * | 2014-07-18 | 2016-01-26 | Qualcomm Incorporated | Systems and methods for transition-minimized data bus inversion |
US9922686B2 (en) * | 2016-05-19 | 2018-03-20 | Micron Technology, Inc. | Apparatuses and methods for performing intra-module databus inversion operations |
US10090027B2 (en) * | 2016-05-25 | 2018-10-02 | Ememory Technology Inc. | Memory system with low read power |
CN110603786B (zh) * | 2017-03-08 | 2022-01-04 | 罗伯特·博世有限公司 | 用于通信网络中的节点的操作的方法 |
EP3905251B1 (en) * | 2019-10-25 | 2023-04-19 | Changxin Memory Technologies, Inc. | Write operation circuit, semiconductor memory device, and write operation method |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3100622B2 (ja) * | 1990-11-20 | 2000-10-16 | 沖電気工業株式会社 | 同期型ダイナミックram |
US6243779B1 (en) * | 1996-11-21 | 2001-06-05 | Integrated Device Technology, Inc. | Noise reduction system and method for reducing switching noise in an interface to a large width bus |
US6898648B2 (en) * | 2002-02-21 | 2005-05-24 | Micron Technology, Inc. | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing |
JP4447200B2 (ja) * | 2002-07-19 | 2010-04-07 | Necエレクトロニクス株式会社 | 映像データ転送方法、表示制御回路及び液晶表示装置 |
US20040068594A1 (en) * | 2002-10-08 | 2004-04-08 | Anthony Asaro | Method and apparatus for data bus inversion |
ITRM20030012A0 (it) * | 2003-01-14 | 2003-01-14 | St Microelectronics Srl | Metodo e sistema circuitale per la trasmissione sincrona di segnali digitali attraverso un bus. |
DE102005013322B3 (de) * | 2005-03-22 | 2006-10-05 | Infineon Technologies Ag | Schaltung zur Erzeugung eines Datenbitinvertierungsflags (DBI) |
-
2004
- 2004-09-22 US US10/946,828 patent/US7411840B2/en active Active
- 2004-12-13 TW TW093138643A patent/TWI263166B/zh active
-
2005
- 2005-03-01 CN CN200510008654XA patent/CN1664800B/zh active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI570571B (zh) * | 2014-12-09 | 2017-02-11 | 英特爾公司 | 以可程式化終端階層來進行動態匯流排反相的技術 |
US10031868B2 (en) | 2014-12-09 | 2018-07-24 | Intel Corporation | Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines |
US10437746B2 (en) | 2014-12-09 | 2019-10-08 | Intel Corporation | Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines |
US10802996B2 (en) | 2014-12-09 | 2020-10-13 | Intel Corporation | Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines |
Also Published As
Publication number | Publication date |
---|---|
CN1664800B (zh) | 2013-01-16 |
US7411840B2 (en) | 2008-08-12 |
CN1664800A (zh) | 2005-09-07 |
US20050216630A1 (en) | 2005-09-29 |
TW200530913A (en) | 2005-09-16 |
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