TWI261901B - Quad flat no-lead chip package structure - Google Patents

Quad flat no-lead chip package structure Download PDF

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Publication number
TWI261901B
TWI261901B TW094102285A TW94102285A TWI261901B TW I261901 B TWI261901 B TW I261901B TW 094102285 A TW094102285 A TW 094102285A TW 94102285 A TW94102285 A TW 94102285A TW I261901 B TWI261901 B TW I261901B
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TW
Taiwan
Prior art keywords
package structure
wafer
lead
flat
quad flat
Prior art date
Application number
TW094102285A
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Chinese (zh)
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TW200627608A (en
Inventor
Chien Liu
Meng-Jen Wang
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Advanced Semiconductor Eng
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Priority to TW094102285A priority Critical patent/TWI261901B/en
Publication of TW200627608A publication Critical patent/TW200627608A/en
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Publication of TWI261901B publication Critical patent/TWI261901B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A QFN type chip package structure is provided. The structure includes a chip, a lead frame and a molding compound. The lead frame has a plurality of bump bonding leads and a metal plate surrounded by the bump bonding leads for electrically connection with bumps on the chip. In addition, the metal plate has a first surface, a second surface and a plurality of mold lock holes concaved from the first surface, especially, the inner size of each mold lock hole is increased gradually from the first surface to the second surface. The cross-section shape of the mold lock holes is trapezoid or arc, for example. Therefore, the delamination between compound and metal plate is reduced to get better mold lock.

Description

1261901 15714twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構，且特別是有關於 一種四方扁平無接腳（Quad Flat No-lead，QFN)之晶片封 裝結構。 【先前技術】 半導體工業是近年來發展速度最快之高科技工業之 一，隨著電子技術的日新月異，高科技電子產業的相繼問 世，使得更人性化、功能更佳的電子產品不斷地推陳出新， 並朝向輕、薄、短、小的趨勢設計。目前在半導體製程當 中，引腳架（lead frame)是經常使用的構裝元件之一，而 四方扁平無接腳之晶片封裝結構（QFN chip package 所使用之引腳架，其引腳之外端切齊於晶片封 f體之四方，因此可縮小晶片封裝體的體積、提高訊號傳 遞的速度。 。月$考圖1，其纷示習知一種四方扁益 的示意圖。以覆晶接合⑽pchip 片契引腳架120為例，晶片110透過多數個導電凸塊 m Ϊ ^ 120 (thecal pad) ，、糸由V,4佳的金屬所製成，例如 用以將晶片110所產峰沾舳处γ山道也 姑寺至屬片 埶片124,再由⑽的―、、、里由寺熱凸塊114傳遞至散 值得、、主片124的織逸到大氣環境中。 思的疋’封膠(molding c〇mp〇Und) 13〇填入 5 1261901 15714twf.doc/g 於晶片110與散熱片12〇之間的間隙 熱凸塊114之周圍表面之後，固化之封圍於每—導 之間經過長時間的熱漲冷縮作用 认轉散熱片124 層（ddaminati〇n)，因而度^^容易產生脫 【發明内容】 罪哎卩牛低4問題。 本七明的目的就是在提供_種四、 片封裝結構’其II由改善娜與散 Μ腳之晶 來提高晶片封裝結構的可靠度。…、3的脫層現象， 要包出—種四方扁平無弓丨腳之晶片封U構主 要括曰曰片、—弓I腳架以及-封勝。曰片呈女:冓，主 塊，而引腳架具有多數個凸塊接合塾二=2數個凸 凸塊接合墊環繞於金屬片之外圍，並轉二這些 該第-表面之多數個孔弟且=片;:;表=凹陷於 該些凸塊連接，且每一:二面與晶片之 封膠包覆曰片盘凡坫 、 乂糸'、縮口。此外， 塊接合墊之下表面以及全屬 中，且凸 外。 乂及以片之弟—表面係暴露於封膠之 依本發明的較佳實施例所述，上述之孔例如 二=，孔之内徑係由第一表面往第 例如呈梯形或圓弧形。 ^面域 明因採料殊的鎖膠孔以增強封膠與金屬片之 曰、曰強度’特別是鎖膠孔之開口係為一縮口狀，因此 6 1261901 15714twf.doc/g =:與金屬片之間產生聲進而提高謂 易懂為和其他目的、特徵和優點能更明顯 明如下。，+父佳實施例，並配合所附圖式，作詳細說 【實施方式]BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a chip package structure, and more particularly to a quad flat no-lead (QFN) wafer. Package structure. [Prior Art] The semiconductor industry is one of the fastest growing high-tech industries in recent years. With the rapid development of electronic technology, the high-tech electronics industry has emerged, making electronic products that are more user-friendly and functionally better. It is designed to be light, thin, short and small. Currently in the semiconductor manufacturing process, the lead frame is one of the frequently used components, and the quad flat no-pin chip package structure (the lead frame used by the QFN chip package, the pin end It is cut into the square of the wafer package, so the volume of the chip package can be reduced, and the speed of signal transmission can be improved. The monthly cost is shown in Fig. 1, which shows a schematic diagram of a square-shaped flat benefit. The flip chip bonding (10) pchip piece For example, the die lead frame 120 is formed by a plurality of conductive bumps m Ϊ ^ 120 (thecal pad), and is made of a metal of V, 4, for example, to immerse the peak of the wafer 110. The γ mountain road is also a piece of 埶 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 (molding c〇mp〇Und) 13〇fill 5 1261901 15714twf.doc/g after the gap between the wafer 110 and the heat sink 12〇 around the surface of the thermal bump 114, the curing is enclosed between each guide After a long period of heat expansion and contraction, the 124th layer of the heat sink is recognized (ddaminati〇n), thus ^^ is easy to produce off [invention content] sin yak low 4 problem. The purpose of this seven Ming is to provide _ kinds of four, piece package structure 'the II is improved by the crystal and the crystal of the foot to improve the chip package structure Reliability. The delamination phenomenon of ..., 3, should be packaged out - a kind of flat square without a bow and a foot of the wafer seal U structure mainly including the cymbal, the bow I tripod and - Feng Sheng. The cymbal is female: 冓, The main block, and the lead frame has a plurality of bump joints = 2 = 2 convex bump bond pads around the periphery of the metal sheet, and two of the first surface of the first surface and = sheet; Table = recessed in the bumps, and each: the two sides of the wafer and the sealing of the wafer cover the cymbal disk, 乂糸', shrinkage. In addition, the lower surface of the block bonding pad and all of the genus, and The outer surface of the sheet is exposed to the sealant. According to a preferred embodiment of the invention, the hole is, for example, two, and the inner diameter of the hole is, for example, a trapezoidal shape from the first surface. Arc shape. ^The surface of the hole is due to the special glue hole to enhance the seal and the strength of the metal sheet, especially the opening of the glue hole. The system is a neck-shaped, so 6 1261901 15714twf.doc / g =: and the sound generated between the metal sheet and improved to become easy to understand and other purposes, features and advantages can be more clearly as follows., + parent embodiment, And in conjunction with the drawings, detailed description [embodiment]

〔第一實施例J 明茶考圖2及圖3，其分麟 1 tr結構主要包括—晶片训、-引腳架 |曰^妾人的封^30,特別是一種晶片210與引腳架220 平封裝體’因此引腳架220無外引腳突 片封古而是引腳222的外側壁切齊於整個晶 =衣體200的四方，且引腳222的底部顯露於封膠现 =，以縮小晶片封裝結構的體積，並加快訊號傳遞的速 ，片2H)例如是記憶體晶片 <可進行編碼 =輯運算的控制晶片’其藉由導電凸塊2性連 接，^塊212的材質例如為錫錯凸塊或無錯 連 引腳架⑽具有多數個凸塊接合塾（引腳）功盘一全卜 片224,而凸塊接合墊222用以電性連接晶片加 212，以將訊號傳遞到外部媒體（例如是印刷電路板鬼 另外，金屬片224位於引腳架22〇之中央區 塊接伽環繞於金屬片224之周圍，且金; 1261901 15714twf.doc/g 可藉由多數個導熱凸塊214與晶片210連接，用以快速傳 遞晶片210所產生的熱能。其中，金屬片224例如是與凸 塊接合墊222相同的材質（最佳為銅）所形成，或是其他 導熱性佳的金屬（鋁及其他材質），且金屬片224之底面 還可暴露於封膠230之外5如圖3所示。 值得庄思的是’為了使金屬片224與封膠230能緊密 接合，金屬片224係在第一表面224a(接近晶片端的表面） 開設多數個鎖膠孔226，且鎖膠孔226之内徑由第一表面 224a往第二表面224b依序遞增，以使鎖膠孔226之接近 晶片端的開口 228係為一縮口狀，如圖2所示。在本實施 例中，鎖膠孔226凹陷於金屬片224之第一表面22如，、以 使封膠230除了填入於晶片21()與金屬片22q之間的間隙 入於鎖膠孔226之内，以加強封膠230與金 2声:！的接合強度。其中’鎖膠孔226例如是凹孔， 以以：擇適當加工加以定義，甚至鎖膠孔226亦可 寸由?:第一表面224a貫穿至第二表面·，ί 如圖2所示。、Α ’以形成類似梯形剖面之鎖膠孔226， 〔第二實施例〕 凊參考圖4及圖5，苴分別給一 —種四方扁平無接腳的晶片、封本發明第二實施例之 f片训的種類、凸塊312、3U、=的剖面示意圖。有關 320之凸塊接合墊322的排列方^成分、用途以及引腳架 2、圖3的1明，、， 式可苓照第一實施例與圖 兄明亚以不同的標號代表對應的元件，在^ 1261901 15714twf.doc/g 再贅述。本實施例與第—實施例不同的是，用以快速導熱 =金屬# 324具有多數個鎖膠孔3施或遍，其凹陷於 第-表面324a，特別是，鎖膠孔3施或遍為具有縮口 狀開口的一凹穴。 如圖4所不’鎖膠孔326a的剖面輪廊為一梯形，其内 =由上往下依序遞增。此外，如圖5所示，_孔遍 面輪廓為-圓弧形。由此可知，當封膠真入於此 、士:膠孔326a^或326b中並緊密嵌合於鎖膠孔3施或3施 =330與導熱用的金屬片324長時間受到熱漲 ^佰仍能保持良好的接合性，故能有效解決 白知脫層寻可靠度降低的問題。 括=上所’本發賴封裝結構，且特別是 構種妾合強度的四方爲平無接腳的晶片封裝結 寸殊〇lJ面形狀的鎖膠孔以增強封膠與金屬片之 Γ接合強度’特別是鎖觀之卩扣係為-縮π狀^ 可避免習知封膠盥金屬H 口此 裝結構的可靠度Γ 間產生脫層，進而提高晶片封 if本毛月已以較佳實施例揭露如上，然其並非用以 限疋本發明，任何熟 賴以 和範圍内，當可作此呼之=二不^發明之精神 範圍當視後附之中更動與潤飾’因此本發明之保護 【圖式簡單說;】以彻騎界定者鱗。 示意^u會示習知—種四方扁平無接腳之晶片封衰、结構的 1261901 15714twf.doc/g 圖2繪示本發明第一實施例之一種四方扁平無接腳之 晶片封裝結構的剖面示意圖。 圖3繪示本發明第一實施例之一種四方扁平無接腳之 晶片封裝結構的底視圖。 圖4及圖5分別繪示本發明第二實施例之一種四方扁 平無接腳的晶片封裝結構的剖面示意圖。 【主要元件符號說明】 110 :晶片 112 :導電凸塊 114 :導熱凸塊 120 :引腳架 122 :凸塊接合墊 124:散熱片 130 ··封膠 200 :晶片封裝結構 210 :晶片 212 :導電凸塊 214 :導熱凸塊 220 :引腳架 222 :凸塊接合墊（引腳） 224 :金屬片 224a :第一表面 224b :第二表面 226 :鎖膠孔 1261901 15714twf.doc/g 228 :開口[First Embodiment J Ming tea test Figure 2 and Figure 3, the split 1 tr structure mainly includes - wafer training, - lead frame | 曰 ^ 妾 people's seal ^ 30, especially a wafer 210 and lead frame 220 flat package 'so the lead frame 220 has no outer lead tabs, but the outer sidewall of the pin 222 is tangent to the entire square of the crystal body 200, and the bottom of the pin 222 is exposed to the sealant. In order to reduce the volume of the chip package structure and speed up the signal transmission, the slice 2H) is, for example, a memory chip < a control chip that can be coded = set operation, which is connected by a conductive bump, The material is, for example, a tin bump or a staggered lead frame (10) having a plurality of bump bonding pads (pins), and a bump bonding pad 222 for electrically connecting the wafers 212 to The signal is transmitted to the external medium (for example, a printed circuit board ghost. In addition, the metal piece 224 is located around the central block of the lead frame 22, surrounded by the metal piece 224, and gold; 1261901 15714twf.doc/g can be used by A plurality of thermally conductive bumps 214 are coupled to the wafer 210 for rapid transfer of thermal energy generated by the wafer 210. The metal piece 224 is formed of the same material (preferably copper) as the bump bonding pad 222, or other metal (aluminum and other materials) having good thermal conductivity, and the bottom surface of the metal piece 224 may be exposed to the sealing material. In addition to 230, FIG. 3 is shown in Fig. 3. It is worthwhile to think that 'in order to enable the metal piece 224 to be tightly bonded to the sealant 230, the metal piece 224 is attached to the first surface 224a (the surface close to the end of the wafer) to open a plurality of glue holes. 226, and the inner diameter of the glue hole 226 is sequentially increased from the first surface 224a to the second surface 224b, so that the opening 228 of the glue hole 226 close to the wafer end is in the shape of a neck, as shown in FIG. In this embodiment, the glue hole 226 is recessed in the first surface 22 of the metal piece 224, such that the sealant 230 is filled in the gap between the wafer 21 () and the metal piece 22q. Inside, to strengthen the joint strength of the sealant 230 and the gold 2:!, wherein the 'lock glue hole 226 is, for example, a recessed hole, to be defined by appropriate processing, even the glue hole 226 can be inch by?: first The surface 224a penetrates to the second surface ·, ί as shown in Fig. 2. Α 'to form a trapezoidal profile Plastic hole 226, [Second embodiment] Referring to FIG. 4 and FIG. 5, respectively, a type of flat flat pinless wafer, a type of f-training of the second embodiment of the present invention, a bump 312, 3U, = cross-sectional schematic diagram. The arrangement of the bump bonding pad 322 of 320, the use and the lead frame 2, Figure 3, and the formula can be referred to the first embodiment and the brother The different reference numerals denote corresponding components, which are further described in ^1261901 15714twf.doc/g. This embodiment differs from the first embodiment in that it has a plurality of glue holes 3 for rapid thermal conduction = metal #324. It is recessed in the first surface 324a, and in particular, the glue hole 3 is applied as a recess having a constricted opening. As shown in Fig. 4, the section of the lock hole 326a is a trapezoidal shape, and the inner side thereof is sequentially increased from top to bottom. Further, as shown in Fig. 5, the _ hole surface profile is a circular arc shape. It can be seen that when the sealant is actually inserted into the glue hole 326a^ or 326b and tightly fitted into the glue hole 3 or 3, the metal sheet 324 for heat conduction is heated for a long time. It still maintains good jointability, so it can effectively solve the problem of reduced reliability of Baizhi delamination. Included in the above-mentioned package structure, and in particular, the four sides of the combination of the strength of the combination are flat-pinned chip-packed holes of the shape of the jJ face to enhance the bond between the sealant and the metal piece. The strength 'especially the buckle of the lock is π-shaped φ. It can avoid the delamination of the reliability of the structure of the packaged metal HH, which improves the wafer seal if the hair is better. The embodiments are disclosed above, but are not intended to limit the scope of the invention, and the scope of the invention may be changed and retouched in the context of the invention. The protection [simplification of the diagram;] to define the scales by riding. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a cross-sectional view of a quad flat unpinned chip package structure according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of a quad flat unpinned chip package structure according to a first embodiment of the present invention. schematic diagram. 3 is a bottom view of a quad flat no-pin chip package structure in accordance with a first embodiment of the present invention. 4 and 5 are cross-sectional views showing a four-sided flat and unpinned chip package structure according to a second embodiment of the present invention. [Major component symbol description] 110: Wafer 112: Conductive bump 114: Thermal bump 120: Lead frame 122: Bump bond pad 124: Heat sink 130 · Sealant 200: Wafer package structure 210: Wafer 212: Conductive Bump 214: Thermal bump 220: Lead frame 222: Bump bond pad (pin) 224: Metal piece 224a: First surface 224b: Second surface 226: Locking hole 1261901 15714twf.doc/g 228: Opening

230 :封膠 310 :晶片 312、314 :凸塊 320 :引腳架 322 :凸塊接合墊 324 :金屬片 324a :第一表面 326a、326b :鎖膠孔 330 :封膠 11230: Sealant 310: Wafer 312, 314: Bump 320: Lead frame 322: Bump bond pad 324: Metal piece 324a: First surface 326a, 326b: Locking hole 330: Sealing 11

Claims (1)

1261901 15714twfl.doc/006 % Γ X 95-6-5 十、申請專利範圍： 1·一種四方扁平無引腳之晶片封裝結構，包括： 一晶片，具有多數個凸塊；1261901 15714twfl.doc/006 % Γ X 95-6-5 X. Patent application scope: 1. A quad flat no-lead chip package structure, comprising: a wafer having a plurality of bumps; 一引腳架，具有多數個凸塊接合墊以及一金屬片 塊ϊΐ墊環繞於該金屬片之外圍，並與該些凸塊電 貫〜，二中5亥金屬片具有一第™表面、-第二表面以及 以：d及該第二表面之多數個貫孔，該金屬片係 於㈣—表面係具-縮口；以及 母》亥些貝孔 些貫ϋτ包覆該晶片與該些凸塊之周圍，並填入於該 該第-&gt; “且該些凸塊接合墊之下表面以及該金屬片之 币一表面係暴露於該封膠之外。 片申請專利範圍第1項所述之四方扁平無引腳之晶 之材ίΐΐ其中該引腳架之該些凸塊接合墊與該金屬片 片封如申請專利範圍第1補述之四方4平無引腳之晶 、衣結構，其中該封膠之材質為熱固性高分子聚合物。 片封申請專利範圍第1項所述之四方扁平無引腳之晶 、衣、〜構，其中該些凸塊接合墊之外侧壁切齊於該封膠 〈侧緣。 乂 片隹二=申請專利範圍第1項所述之四方扁平無引腳之晶 塊、衣、、°構，其中接合於該金屬片之該些凸塊係為散熱凸 6·如申請專利範圍第1項所述之四方扁平無引腳之晶 12a lead frame having a plurality of bump bonding pads and a metal piece pad surrounding the periphery of the metal piece, and electrically connected to the bumps, the second metal plate has a TM surface, a second surface and a plurality of through holes of: d and the second surface, the metal piece is attached to the (four)-surface fastener-shrinkage; and the mother hole is covered with the ϋτ to cover the wafer and the convex Around the block, and filled in the -> "and the lower surface of the bump bonding pads and the surface of the metal sheet are exposed to the sealant. The four-sided flat leadless crystal material ΐΐ 该 该 该 该 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸 凸The material of the sealant is a thermosetting polymer. The flat-shaped lead-free crystal, clothing, and structure described in claim 1 of the patent application, wherein the outer surfaces of the bump pads are aligned In the sealant <side edge. 乂片隹二=the square of the patent application mentioned in item 1 A flat leadless crystal, a package, a structure, wherein the bumps bonded to the metal piece are heat dissipating protrusions. 6. The quad flat no-lead crystal according to claim 1 of the patent application. 1261901 15714twfl.doc/006 95-6-5 片封裝結構，其中該些貫孔之内徑係由該第一表面往該第 二表面遞增。 7. 如申請專利範圍第1項所述之四方扁平無引腳之晶 片封裝結構，其中該些貫孔之剖面形狀係呈梯形。 8. 如申請專利範圍第1項所述之四方扁平無引腳之晶 片封裝結構，其中該些貫孔之剖面形狀係呈圓弧形。1261901 15714twfl.doc/006 95-6-5 A package structure in which the inner diameter of the through holes is increased from the first surface toward the second surface. 7. The quad flat no-lead wafer package structure according to claim 1, wherein the cross-sectional shapes of the through holes are trapezoidal. 8. The quad flat no-lead wafer package structure according to claim 1, wherein the cross-sectional shapes of the through holes are circular. 1313
TW094102285A 2005-01-26 2005-01-26 Quad flat no-lead chip package structure TWI261901B (en)

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Publication number Priority date Publication date Assignee Title
TWI409924B (en) * 2007-09-12 2013-09-21 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof

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TWI556359B (en) * 2015-03-31 2016-11-01 南茂科技股份有限公司 Quad flat non-leaded package structure and leadframe thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409924B (en) * 2007-09-12 2013-09-21 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof

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