1261366 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體封裝構造，特別係有關於 一種具有不同水平引腳部間形成傾斜引腳部之半導體封 裝構造。 【先前技術】 習知半導體封裝構造中，導線架之引腳通常區分為水 平狀内引腳與外引腳。於壓模時，會產生一模流壓力，其 係作用於水平狀内引腳與晶片，使該晶片產生一垂直向位 置偏移。 請參閱帛1 ®，一種習知的半導體封裝構造1〇〇係包 含一 LOC導線架之複數個引腳n〇、一晶片12〇、複數個 電連接元件130及一模封膠體14〇。該些引腳11〇可區分 為複數個水平狀内引腳丨丨丨及複數個外引腳丨12，該晶片 120係具有一主動面121及複數個銲墊η]，該晶片（π 之該主動面12 1係以一黏晶膠帶1 5 〇貼附於該些内引腳 1 U，例如銲線之該些電連接元件13 0係電性連接該些内 引腳ill與該晶片120之該些銲墊122，最後以一模封膠 體140密封該晶片12〇、該些内引腳}丨丨及該些電連接元 件 1 3 0。 该半導體封裝構造1 〇〇於壓模時，注入該模封膠體1 5〇 之壓力會產生一垂直向模流壓力差，其係直接作用於該些 水平狀之内引腳1U，導致該晶片12〇產生位置偏移，第 2圖係為在習知半導體封裝構造丨〇〇中，其導線架内引腳 6 !261366 111受到一垂直向模流壓力差產生晶片位移之上視圖。當 该晶片12 0之垂直向位置偏移過大時，會造成該半導體封 裝構造1 0 0有露金線及短路之缺點。 中華民國發明專利證號第142682號「封裝1C裝置之 平衡模流（mold flow)的方法」揭示一種半導體封裝構造， 如第3圖所示，一種習知的半導體封裝構造2〇〇係包含複 數個内引腳2 1 0、一晶片2 2 0、複數個電連接元件2 3 〇及 一模封膠體240。該些内引腳210係具有一彎曲部211， 但該些内引腳210之内端無明顯水平位置變化。該晶片220 係具有一主動面221及複數個銲墊222，該晶片220之該 主動面221係以一黏晶膠帶25〇貼附於該些内引腳21〇之 内端，例如銲線之該些電連接元件23〇係電性連接該些内 引腳210與該晶片22〇之該些銲墊222，最後以一模封膠 體240密封該晶片22〇、該些内引腳21〇及該些電連接元 件230。此一習知半導體封裝構造2〇〇係利用該些内引腳 21〇之彎曲部211來改善壓模時所形成之上下模流平衡， 但仍未解決晶片會產生垂直向位置偏移之問題。 【發明内容】 本發明之主要目的係在於提供一種半導體封裝構 造，複數個引腳（約内引腳之部位）係區分為複數個第—水 平引腳部、複數個傾斜引腳部以及複數個第二水平引腳 邛該些傾斜引腳部與對應該些第一水平引腳部之連接處 二7成為第一彎折線，其係鄰近或位於該模封膠體之一 邊緣，该些傾斜引腳部與對應該些第二水平引腳部之連接 7 1261366 處係形成_第 蠻 乐考折線，其係鄰近該 提供足夠長度之該 片之相】面。藉以 生 、斜引腳邛以分散垂直向模法 差，改善壓模時晶片垂直 祆机壓力 生罝向位置偏移之問題。 本發明之次一目的# + 造，1 φ 、/、在於提供一種半導體封妒構 u利用在傾斜引腳部 “冓 線之間的一垂直古许至 4折線與第二彎折 Μ置同度差以在相同上 片在上下模具内之相 …、比例下改變晶 故能延用既有之上下模星，相…於-晶片之厚度， 横一達到壓模時保護晶片 依據本發明，一鐺主增_ 心日的。 +導體封裝構造係包含一導 複數個引腳、一晶片、 3導線架之 矽曰片伤^ # 電連接兀件及一模封膠體。 = 料㈣，該些電連接元㈣電性連接該 一 』胗體係也封该晶片、該些電連接 兀件與該些引腳之一部位，1 心 〆 其中，该些引腳被該模封膠體 #封之部分係區分為複數個笛 * ^ 要文個第一水平引腳部、複數個傾斜 引腳部以及複數個第二水平丨 ^ 十引腳邛，該些傾斜引腳部盘 應該些第-水平引腳部之連接處係形成為一第—彎折 線，其係鄰近或位於該模封膠體之—邊緣，該些傾斜引腳 部與對應該些第二水平引腳部之連接處係形成一第二彎 折線，其係鄰近該晶片之_側面，該些傾斜引腳部係連接 對應之該些第-水平引腳部與m二水平引腳部並使 該第-彎折線與該第二f折線之間形成# _垂直高度差。 【實施方式】 依據本發明之第一具體實施例，揭示一種半導體封裝 構造300。請參閱第4圖，一種半導體封裝構造3〇〇係包 1261366 ::導線架之複數個引腳31。、一晶片32。、複數個電連 架及—模封膠體340。具有該些引腳310之導線 …—L〇C(Lead_〇n-ChiP)導線架，該晶4 320係具有 動：321、—背面322以及複數個側面⑵，該晶片 2〇之:亥主動φ 321係為矩形而具有兩長邊與兩短邊。複 固銲墊324係形成於該主動面321。在本實施例中，該 二引腳310由該模封膠體34()之邊緣外往内係區分為複數 個第-水平引腳部311、複數個傾斜引腳部312以及複數 個第二水平引腳部313,藉由-黏晶膠帶㈣使該晶片320 =該主動面321貼附於該些第二水平引腳部313。第一水 平引聊部311係猶伸入該模封膠體34〇内並可突伸於該模 封膠體340之邊緣之外’以供模具夾固。如第5圖所示， 該些傾斜引腳部312與對應該些第一水平引腳部3ιι之連 接處係形成為-第—f折線314，其係鄰近或位於該模封 膠體340之一邊緣，可位在該模封膠體340内部或剛好切 齊於該模封膠體34〇之邊緣，其中該第—彎折線314與該 模封膠體340之間的鄰近距離應控制在不超過25〇微米α m)。該些傾斜引腳部312與對應該些第二水平引腳部⑴ 之連接處係形成一第二彎折線315，其係鄰近該晶片 之對應之其中一侧面323。簡而言之，該些傾斜引腳部3工2 係由該晶片320之對應侧面323斜向延伸至接近該模封膠 體340之邊緣，故使該些傾斜引腳部312具有相當長度， 以分散垂直向模流壓力差，更具有注膠（fining)時導流以 及加熱固化膠體（packing)時引腳彈性回復之功效。此外， 9 1261366 該第一彎折線314與該第二彎折線315之間係具有一垂直 高度差，可大於、小於或概略等於該晶片320之厚度，以 改變該晶片320於該模封膠體340内之相對位置，故能延 用既有之上下模具達到壓模時保護黏晶面向改變之晶片 3 20之目的。較佳地，該第一彎折線3丨4與該第二彎折線 3 1 5之間的垂直高度差係不小於該晶片32〇之厚度，故气 些第二水平引腳部3 1 3係可形成於不同於該些第一水平引 腳部311之一平面，以供該晶片320反向黏貼至該導線架 之該些第二水平引腳部313。此外，而該些傾斜引腳部3|2 係可具有不小於300微米（# 之水平向長度，以增進引 腳彈性回復之能力。 該些電連接元件330係電性連接該晶片32〇之該些銲 塾324至該些第二水平引腳部313。在本實施例中，該些 電連接元件330係為銲線。該模封膠體34〇係以壓模方式 形成，其係密封該晶片320、該些電連接元件33〇與該些 引腳3 1 0 t部位。藉由該第一彎折線3 } 4與該第二彎折 線3 1 5之間的該垂直高度差，能改變該晶片32〇在上下模 /、中之相對位置及其主動面321之朝向，故能延用既有之 上下模具達到壓模時保護該晶片32〇之目的。 請參閱第5圖，依據本發明之第一具體實施例，該導 線木係S a有i少一擾流板3 i 6，丨係位於模流注入口 與排出口（圖未繪出），該擾流板316可防止該模封膠體34〇 產生模*不平均的現象。該導線架係界定有—模封區3 1 了 以及在該模封區317内之一黏晶區318，該模封區317係 10 1261366 作為該封膠體340之形成位置，該黏晶區318之尺寸與位 置係對應之該晶片320之該主動面321之尺寸與位置。在 本實施例中，如第5圖所示，該些第二水平引腳部3 13係 可由該黏晶區318(即該主動面321)之兩短邊延伸至該黏 晶區318上，以縮短該些電連接元件33〇之長度，達到電 性連接該晶片320之該些銲墊324與該些引腳3 1〇(如第4 圖所示）。此外，其中部分第二水平引腳部313a係可不延 伸至該黏晶區318内（如第5圖所示）。 請參閱第6圖，其係為依據本發明之第一具體實施 例’在該半導體封裝構造3〇〇中該晶片32〇受模流壓力差 的垂直方向位移之上視圖。將第2圖與第6圖相比較發現 在第1圖習知結構中該晶片12〇受一模流壓力差所產生之 垂直方向位移為-0.05 19 mm，而在第4圖第一具體實施例 中之該晶片320受一壓力差所產生之垂直方向位移則為 -0.0296刪，因此可推知本發明於第4圖中之該些引腳31〇 _ 叉到的垂直方向之模流壓力差應小於習知第1圖中之該些 水平狀之内引腳1 1 i所受到的垂直方向之模流壓力差。其 原因為該些引腳310之該些傾斜引腳部312將垂直方向之 模流壓力差進一步分解成水平及垂直方向，以減低作用於 該些傾斜引腳部312之垂直方向壓力差，可確實有效改善 晶片在壓模時所產生的垂直向位置偏移情形。 或者，如第7圖所示，依據本發明之第二具體實施例， 揭示種導線架，其係包含有複數個引腳4丨〇，其係界定 有杈封區4 1 7以及在該模封區4丨7内之一黏晶區4丨8。 1261366 該杈封區417係定義一模封膠體之形成位 之尺寸與位置係對應之一曰 。该黏晶區418 <日日片主動面（圖未給屮、夕口 與位置。該些引腳川由該模封區417之外 尺寸 複數個第一水平引腳部 〗内係區分為 複數個第二水平引腳二 該些第-水平引腳部411之連接處係形成為二^彎『應 414，其係鄰近該模封區417 斤線BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure having inclined lead portions formed between different horizontal pin portions. [Prior Art] In the conventional semiconductor package structure, the lead pins of the lead frame are usually divided into horizontal inner pins and outer pins. At the time of stamping, a mold flow pressure is generated which acts on the horizontal inner leads and the wafer to cause a vertical displacement of the wafer. Referring to the 帛1®, a conventional semiconductor package structure includes a plurality of pins n〇 of a LOC lead frame, a wafer 12〇, a plurality of electrical connection elements 130, and a molding compound 14〇. The pins 11 〇 can be divided into a plurality of horizontal inner pins 丨丨丨 and a plurality of outer pins 丨 12, the wafer 120 has an active surface 121 and a plurality of pads η], the wafer (π The active surface 12 1 is attached to the inner leads 1 U by a die-bonding tape 15 5 , and the electrical connecting elements 130 of the bonding wires are electrically connected to the inner leads ill and the wafer 120 . The pads 122 are finally sealed by a molding compound 140, the inner leads 丨丨, and the electrical connecting members 130. The semiconductor package structure 1 is applied to the stamper. The pressure applied to the laminator 15 〇 produces a vertical die flow pressure differential that acts directly on the horizontal pins 1U, causing the wafer 12 to be displaced. Figure 2 is In a conventional semiconductor package structure, the lead frame 6 261 366 111 of the lead frame is subjected to a vertical displacement of the die to generate a wafer displacement. When the vertical position of the wafer 12 is excessively offset, It will cause the shortcomings of the semiconductor package structure 100 gold wire and short circuit. The Republic of China invention patent certificate No. 142, 682, "Method of Packaging Mold Flow of 1C Device" discloses a semiconductor package structure. As shown in FIG. 3, a conventional semiconductor package structure 2 includes a plurality of internal pins 2 1 0, a wafer 2 2 0, a plurality of electrical connecting elements 2 3 〇 and a molding encapsulant 240. The inner leads 210 have a bent portion 211, but the inner ends of the inner leads 210 have no significant horizontal position The wafer 220 has an active surface 221 and a plurality of pads 222. The active surface 221 of the wafer 220 is attached to the inner ends of the inner leads 21 by a die bond tape 25, for example, soldering. The electrical connection elements 23 of the wires are electrically connected to the inner leads 210 and the pads 222 of the wafer 22, and finally the pads 22 are sealed by a molding compound 240, and the inner leads 21 are And the electrical connection component 230. The conventional semiconductor package structure 2 utilizes the curved portions 211 of the inner leads 21 to improve the upper and lower mold flow balance formed during the stamping, but the wafer is still unsolved. The problem of vertical positional shift will occur. [Summary of the Invention] The invention provides a semiconductor package structure in which a plurality of pins (about the inner pin portion) are divided into a plurality of first-horizontal pin portions, a plurality of inclined pin portions, and a plurality of second horizontal pins. The connecting portion 27 of the inclined lead portion and the corresponding first horizontal lead portion becomes a first bending line which is adjacent to or located at one edge of the molding adhesive body, and the inclined lead portions correspond to the second The connection of the horizontal pin portion 7 1261366 forms a _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The problem of vertical offset of the die pressure on the die when the die is shifted. The second object of the present invention is to create a semiconductor package structure, which utilizes a vertical line between the turns of the inclined pin portion to a 4-fold line and a second bend line. The difference in the ratio of the same top sheet in the upper and lower molds, the ratio of the crystal can be extended by the existing upper and lower mold stars, the thickness of the wafer, the thickness of the wafer, and the protection of the wafer when the horizontal one reaches the stamper, according to the present invention, The main conductor is _ heart-shaped. The conductor package structure consists of a plurality of leads, a wafer, a 3 lead frame, a chip joint, an electrical connection, and a mold seal. The electrical connection element (4) is electrically connected to the 胗 system to also seal the wafer, the electrical connection components and one of the pins, 1 core, wherein the pins are sealed by the molding compound # The part is divided into a plurality of flutes * ^ a first horizontal pin portion, a plurality of inclined pin portions, and a plurality of second horizontal 丨 ^ ten pins 邛, the tilted pin portions should be some first-level The junction of the pin portion is formed as a first-bending line which is adjacent to or located in the molding compound. - an edge, the intersection of the inclined lead portions and the corresponding second horizontal lead portions forms a second bending line adjacent to the side of the wafer, and the inclined lead portions are connected to the corresponding The first-horizontal lead portion and the m-two horizontal lead portion form a #_vertical height difference between the first-folding line and the second f-fold line. [Embodiment] According to the first embodiment of the present invention, A semiconductor package structure 300 is disclosed. Referring to FIG. 4, a semiconductor package structure 3 1212366: a plurality of pins 31 of a lead frame, a wafer 32, a plurality of electrical racks, and a mold seal colloid 340. The lead wire having the pins 310...-L〇C (Lead_〇n-ChiP) lead frame, the crystal 4 320 system has a motion: 321, a back surface 322, and a plurality of sides (2), the wafer 2 The galvanic active φ 321 is rectangular and has two long sides and two short sides. The re-bonding pad 324 is formed on the active surface 321 . In this embodiment, the two pins 310 are formed by the molding colloid 34 () The outer edge of the edge is divided into a plurality of first-horizontal pin portions 311, a plurality of inclined pin portions 312, and The plurality of second horizontal lead portions 313 are attached to the second horizontal lead portions 313 by the die bonding tape 321 by the adhesive bonding tape (4). The first horizontal quotation portion 311 is still inserted. The mold seal body 34 can be protruded from the edge of the mold seal 340 to be clamped by the mold. As shown in FIG. 5, the inclined lead portions 312 correspond to the first horizontal lead. The joint of the foot 3 ι is formed as a -f-fold line 314 which is adjacent to or located at one edge of the molding compound 340 and can be located inside the mold seal 340 or just in the same manner as the mold seal 34. The edge of the first bending line 314 and the molding compound 340 should be controlled to be no more than 25 〇 μm α m). The intersection of the inclined lead portions 312 and the corresponding second horizontal lead portions (1) forms a second bending line 315 adjacent to one of the corresponding side faces 323 of the wafer. In short, the inclined lead portions 3 extend obliquely from the corresponding side surface 323 of the wafer 320 to the edge of the molding compound 340, so that the inclined lead portions 312 have a considerable length to Disperse the vertical mold flow pressure difference, and it has the effect of guiding the flow during the filling and the elastic recovery of the pin when heating and curing the colloid. In addition, the first bending line 314 and the second bending line 315 have a vertical height difference, which may be greater than, less than or roughly equal to the thickness of the wafer 320 to change the wafer 320 to the molding compound 340. The relative position within the inside can be extended by the use of the upper and lower molds to achieve the purpose of protecting the die-facing wafers 30 when the die is pressed. Preferably, the difference in vertical height between the first bending line 3丨4 and the second bending line 3 15 is not less than the thickness of the wafer 32〇, so the second horizontal lead portions 3 1 3 The film may be formed on a plane different from the one of the first horizontal lead portions 311 for the reverse bonding of the wafer 320 to the second horizontal lead portions 313 of the lead frame. In addition, the inclined lead portions 3|2 may have a horizontal length of not less than 300 micrometers (# to enhance the elastic recovery of the leads. The electrical connecting members 330 are electrically connected to the wafer 32. The solder bumps 324 are connected to the second horizontal lead portions 313. In the embodiment, the electrical connecting elements 330 are solder wires. The mold sealing body 34 is formed by compression molding, which seals the soldering wires. The chip 320, the electrical connection elements 33 and the pins 3 10 t can be changed by the vertical height difference between the first bending line 3 } 4 and the second bending line 3 1 5 The wafer 32 is oriented at the relative position of the upper and lower molds, and the direction of the active surface 321 thereof, so that the purpose of protecting the wafer 32 when the upper and lower molds are used to reach the stamper can be extended. Please refer to FIG. 5, according to the present invention. In a first embodiment of the invention, the wire wood system S a has a spoiler 3 i 6 , and the tether is located at the mold injection port and the discharge port (not shown), and the spoiler 316 can prevent the The mold encapsulant 34 〇 produces a phenomenon of unevenness of the mold. The lead frame defines a mold seal zone 3 1 and is in the mold seal A die bonding region 318 in the 317, the die sealing region 317 is 10 1261366 as a forming position of the sealing body 340, and the size and position of the die bonding region 318 correspond to the size and position of the active surface 321 of the wafer 320. In this embodiment, as shown in FIG. 5, the second horizontal lead portions 3 13 may extend from the short sides of the die-bonding region 318 (ie, the active surface 321) to the die-bonding region 318. To shorten the length of the electrical connecting elements 33, to electrically connect the pads 324 of the wafer 320 with the pins 31 (as shown in FIG. 4). In addition, some of the second levels The lead portion 313a may not extend into the die attach region 318 (as shown in Fig. 5). Please refer to Fig. 6, which is a first embodiment of the present invention in the semiconductor package structure. The wafer 32 is subjected to a vertical displacement displacement of the die flow pressure difference. Comparing FIG. 2 with FIG. 6 , it is found that the wafer 12 is subjected to a mold flow pressure difference in the conventional structure of FIG. The displacement in the vertical direction is -0.05 19 mm, and the wafer 320 in the first embodiment of Fig. 4 is produced by a pressure difference. The displacement in the vertical direction is -0.0296, so it can be inferred that the differential pressure of the mold in the vertical direction of the pins 31〇_ in the fourth figure of the present invention should be smaller than those in the conventional figure 1 The difference in the mold direction pressure of the pin 1 1 i received in the vertical direction is caused by the inclined pin portions 312 of the pins 310 further decomposing the differential pressure difference in the vertical direction into horizontal and vertical directions. In order to reduce the vertical pressure difference acting on the inclined lead portions 312, the vertical positional displacement caused by the wafer during the stamping can be effectively improved. Or, as shown in FIG. 7, according to the present invention In a second embodiment, a lead frame is disclosed which includes a plurality of pins 4 界定 defining a 杈 sealing region 4 1 7 and a die bonding region 4 该 in the molding region 4 丨 7 8. 1261366 The sealing zone 417 defines one of the dimensions and positional correspondence of the formation of a molding compound. The die-bonding zone 418 <the sunday active surface (the figure is not given, the suffix and the position. The pins are divided by the die-cutting zone 417 and the plurality of first horizontal pin sections) a plurality of second horizontal pins 2 and the junctions of the first-horizontal pin portions 411 are formed as two bends 414, which are adjacent to the mold seal region 417 jin line
412盥對庫兮此笛, 邊緣，该些傾斜引腳部 一對應忒二弟二水平引腳部413 -蠻妍嬙4ις甘^ 炙運接處係形成一第 一#折線415，其係鄰近該黏 4w ^ 418 ’該些傾斜引腳部 係連接對應之該些第一水平引 平引腳部413並使該第一彎 一該些第一水 ((弟考折線414與該第二彎折線415 :間形成有-垂直高度差…在本實施例中，丨晶片之銲 墊位置不同，該此第-太单丨 一弟—水千引腳部413係可由該矩形黏晶 區4 1 8之兩長邊延伸至該黏晶區4丨8。 請參閱第8圖，依據本發明之第三具體實施例，另_ 種半導體封裝構造5⑻之截❹意圖。—種半導體封裝構 造500係包含-導線架之複數個引腳510、一晶片520、 複數個電連接元件53〇及—模封膠體54〇。該導線架係另 包含有一晶片承座516,以供設置該晶片52〇,該晶片52〇 係具有一主動面521、一背面522、複數個側面523及複 數個形成於該主動面521之銲墊524，藉由一黏晶膠55〇 使該晶片520之該背面522貼附於該晶片承座516。該些 引腳510由該模封膠體540之邊緣外往内係區分為複數個 第一水平引腳部5 11、複數個傾斜引腳部5丨2以及複數個 12 1261366 第二水平引腳部5丨3，該歧傾 一彳員斜引腳部512與對應該些第 一水平引腳部5 11之連接處係 一 y 免係形成為一第一彎折線514， 其係鄰近或位於該模封膠體54〇 之邊緣，該些傾斜引腳 第 =斤::應該些第二水平引腳部513之連接處係形成一 "折線515，其係鄰近該晶片520之對應之其中一側 面⑵。較佳地，一膠帶560係黏貼於該些第二水平引腳 部川與該晶片承座516以增加該晶片承座516之支撐 力。此外，該第一弯折線514與該第二弯折線515之間係 具有：垂直高度差’故能延用既有之上下模具達到壓模時 ^蔓该晶片520之目的。該些電連接元件53〇電性連接該 晶片520之該些銲墊524至該些第二水平引㈣川1 些電連接元件別係為銲線。該模封膠體540係以壓模方 式㈣該晶片520、該些電連接元件53()與該些引腳51〇 之一部位。藉由該些傾斜引腳部512以分散垂直向模流堡 力差，改善壓模時晶片垂直向位置偏移之問題。 本發明之保護範圍當視後附之中請專利範圍所界定 ^為準’任何熟知此項技藝者’在不脫離本發明之精神和 範圍内所作之㈣變化與修改，均屬於本發明之保護範 圍0 【圖式簡單說明】 第1圖··習知半導體封裝構造之截面示意圖。 第2圖·在習知半導體封裝構造中，其導線架内引腳受到 垂直向模流壓力差產生晶片位移之上視圖。 第3圖：另一種習知半導體封裝構造之截面示意圖。 13 1261366 第4圖：依據本發明之第一具體實施例，一種半導體封裝 構造之截面示意圖。 第5圖：依據本發明之第一具體實施例，該半導體封裝構 造所使用導線架之内引腳之上視圖。 第6圖：依據本發明之第一具體實施例，在該半導體封裝 構造中，其導線架内引腳受到一垂直向模流壓力 差產生晶片位移之上視圖。412 盥 兮 兮 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 415 415 415 415 415 415 415 415 The viscous pins 4w ^ 418 'the inclined lead portions are connected to the first horizontal flattening pin portions 413 and the first bends the first waters (the dice line 414 and the second bend) The fold line 415 is formed with a vertical height difference. In this embodiment, the pads of the tantalum wafer are different in position, and the first-to-single-single-water-pin portion 413 can be made up of the rectangular die-bonding region 4 1 . The two long sides of 8 extend to the die bonding region 4丨8. Referring to Fig. 8, in accordance with a third embodiment of the present invention, another semiconductor package structure 5(8) is intended to be a parabola. a plurality of pins 510 including a lead frame, a wafer 520, a plurality of electrical connection members 53 and a molding compound 54. The lead frame further includes a wafer holder 516 for disposing the wafer 52, The wafer 52 has an active surface 521, a back surface 522, a plurality of side surfaces 523, and a plurality of active surfaces 521 formed thereon. The pad 524 is attached to the wafer holder 516 by a die bond 55. The pins 510 are divided into a plurality of pins 540 from the edge of the die bond 540. a first horizontal lead portion 5 11 , a plurality of inclined lead portions 5 丨 2, and a plurality of 12 1261 366 second horizontal lead portions 5 丨 3, the slanting oblique member 512 and corresponding first The junction of the horizontal pin portion 5 11 is formed as a first bending line 514, which is adjacent to or located at the edge of the molding compound 54〇, and the inclined pins are: The junction of the two horizontal lead portions 513 forms a " fold line 515 adjacent to one of the corresponding side faces (2) of the wafer 520. Preferably, a tape 560 is adhered to the second horizontal pin portion. And the wafer holder 516 is used to increase the supporting force of the wafer holder 516. In addition, the first bending line 514 and the second bending line 515 have a vertical height difference, so that the upper and lower molds can be extended. The purpose of the wafer 520 is achieved when the stamper is reached. The electrical connection elements 53 are electrically connected to the wafer 520. The solder pads 524 to the second horizontal leads (4) are electrically connected. The mold sealing body 540 is in a stamping manner (4) the wafer 520, the electrical connecting members 53 () and the leads One of the legs 51. By the inclined pin portions 512, the problem of the vertical positional deviation of the wafer during the stamping is improved by dispersing the vertical differential force of the mold. The protection range of the present invention is regarded as a rear attachment. The definitions of the patents are subject to the 'fourth variation and modification' of the present invention without departing from the spirit and scope of the invention. · A schematic cross-sectional view of a conventional semiconductor package structure. Fig. 2 is a top view of the wafer displacement in the lead frame of the conventional semiconductor package in which the lead pins are subjected to a vertical die flow pressure difference. Figure 3: A schematic cross-sectional view of another conventional semiconductor package construction. 13 1261366 Fig. 4 is a schematic cross-sectional view showing a semiconductor package structure in accordance with a first embodiment of the present invention. Figure 5 is a top view of the inner lead of the leadframe used in the semiconductor package construction in accordance with a first embodiment of the present invention. Figure 6: In accordance with a first embodiment of the present invention, in the semiconductor package construction, the lead pins in the leadframe are subjected to a vertical die flow pressure differential to produce a wafer displacement view.
第7圖：依據本發明之第二具體實施例，另一種半導體封 裝構造所使用之導線架之内引腳之上視圖。 第8圖：依據本發明之第三具體實施例，另一種半導體封 裳構造之截面示意圖。 【主要元件符號說明】 100半導體封裝構造Figure 7 is a top view of the inner lead of the leadframe used in another semiconductor package construction in accordance with a second embodiment of the present invention. Figure 8 is a cross-sectional view showing another semiconductor package structure in accordance with a third embodiment of the present invention. [Main component symbol description] 100 semiconductor package structure
110引腳 12 0晶片 130電連接元件 2〇〇半導體封裝構造 111内引腳 121主動面 140模封膠 112外引腳 122銲墊 150黏晶膠帶 2 11彎曲部 221主動面 240模封膠 222銲墊 250黏晶膠帶 21〇内引腳 220晶片 230電連接元件 300半導體封裝構造 310引腳 3 12傾斜引腳部 3 13a第二水平引 第一水平引腳部 第二水平引腳部 腳部 311 14 313 1261366 3 1 4第一彎折線 3 1 7模封區 320晶片 3 2 3側面 330電連接元件 410引腳 412傾斜引腳部 4 1 4第一彎折線 4 1 6擾流板 500半導體封裝構造 510引腳 512傾斜引腳部 5 14第一彎折線 5 1 6晶片承座 520晶片 523側面 530電連接元件 560膠帶 第二彎折線 316 擾流板 黏晶區 主動面 322 背面 銲墊 模封膠體 350 黏晶膠帶 第一水平引腳部 第二水平引腳部 第二彎折線 模封區 418 黏晶區 第一水平引腳部 第二水平引腳部 第二彎折線 主動面 522 背面 鲜塾 模封膠體 550 黏晶膠 15110-pin 12 0 chip 130 electrical connection component 2 〇〇 semiconductor package structure 111 inner pin 121 active surface 140 mold sealant 112 outer pin 122 solder pad 150 adhesive tape 2 11 curved portion 221 active surface 240 mold sealant 222 Pad 250 adhesive tape 21 〇 pin 220 wafer 230 electrical connection element 300 semiconductor package construction 310 pin 3 12 inclined pin portion 3 13a second horizontal lead first horizontal pin portion second horizontal pin portion foot 311 14 313 1261366 3 1 4 first bending line 3 1 7 molding area 320 wafer 3 2 3 side 330 electrical connection element 410 pin 412 inclined pin part 4 1 4 first bending line 4 1 6 spoiler 500 semiconductor Package Construction 510 Pin 512 Tilted Pin Section 5 14 First Bending Line 5 1 6 Wafer Bearing 520 Wafer 523 Side 530 Electrical Connection Element 560 Tape Second Bending Line 316 Spoiler Bonding Area Active Surface 322 Back Pad Model Sealing body 350 Adhesive tape First horizontal lead part Second horizontal lead part Second bending line molding area 418 Adhesive area First horizontal lead part Second horizontal lead part Second bending line Active surface 522 Fresh back塾 mold seal 550 Adhesive glue 15