TWI469276B - Leadframe and semiconductor package having downset spoilers - Google Patents
Leadframe and semiconductor package having downset spoilers Download PDFInfo
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- TWI469276B TWI469276B TW97100499A TW97100499A TWI469276B TW I469276 B TWI469276 B TW I469276B TW 97100499 A TW97100499 A TW 97100499A TW 97100499 A TW97100499 A TW 97100499A TW I469276 B TWI469276 B TW I469276B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- Lead Frames For Integrated Circuits (AREA)
Description
本發明係有關於電傳導的連接元件，可運用於半導體封裝以承載晶片，特別係有關於一種具有下沉擾流板連接結構之導線架以及使用該導線架之半導體封裝構造。The present invention relates to electrically conductive connecting elements that can be used in semiconductor packages to carry wafers, and more particularly to a leadframe having a sinker spoiler connection structure and a semiconductor package construction using the leadframe.
導線架(leadframe)或稱引線框架已是普遍作為半導體封裝之晶片載體，通常該導線架係具有複數個金屬材質之引腳以及一擾流板，通常引腳係用以電性傳遞晶片訊號，擾流板係用以改變而平衡上下模流，以製造品質良好可密封晶片之模封膠體。在一種已知的導線架架構中，LOC(Lead－on－Chip，引腳在晶片上)封裝類型之引腳更可以取代晶片承座(die pad)以提供晶片貼固之用途。然而，無論是使用晶片承座或LOC引腳承載晶片，為了達到模封灌膠製程中平衡上下模流，通常會適度調整擾流板而為下沉型態(downset)而與引腳不在同一平面。故擾流板之連接點須作彎折，會拉扯到被連接引腳導致位移歪斜，造成黏晶不確實與打線製程難以實施之問題。A lead frame or lead frame is commonly used as a wafer carrier for a semiconductor package. Usually, the lead frame has a plurality of metal material pins and a spoiler. Usually, the lead is used to electrically transmit the chip signal. The spoiler is used to change and balance the upper and lower mold flows to produce a mold seal of a good quality sealable wafer. In a known leadframe architecture, a LOC (Lead-on-Chip) package type of pin can replace the die pad to provide wafer bonding. However, whether using a wafer holder or a LOC pin to carry the wafer, in order to achieve a balanced upper and lower mold flow in the mold filling process, the spoiler is usually adjusted appropriately for the sinking type and is not the same as the pin. flat. Therefore, the connection point of the spoiler has to be bent, which will pull the connected pin to cause the displacement to be skewed, which causes the problem that the die bond is not sure and the wire bonding process is difficult to implement.
請參閱第1圖所示，習知導線架100主要包含複數個引腳110、一擾流板120以及一連接條130。該些引腳110係排列於該導線架100之兩相對較長側，該擾流板120係位於該導線架100之兩相對較短側，該擾流板120除了以短繫條121連接至導線架之框壩140，更利用該連接條130連接該擾流板120至鄰近之一引腳111。該框壩140係固定連接該些引腳110與111與該擾流板120。請參閱第2及3圖所示，該擾流板120在形成下沉型態時，該連接條130與該擾流板120連接之一端會形成有一下沉彎折131，以使該些引腳110與該擾流板120分別位於一第一平面101與一第二平面102。再如第2圖所示，此時該連接條130會承受一向下之拉力而產生位移D1，同時拉扯該引腳111，導致該引腳111產生傾斜位移D2。一黏晶膠帶150係貼附於該些引腳110與111之下表面，以供黏貼一晶片(圖中未繪出)。再如第2及3圖所示，由於上述被連接之引腳111受到拉扯而傾斜位移，使得該引腳111與其餘引腳101無法完全共平面，造成該黏晶膠帶150無法平貼於晶片主動面。因此，在黏晶製程中，該黏晶膠帶150與晶片無法緊密貼合，降低該些引腳110與111與晶片之間之黏接強度，容易造成晶片剝離。此外，傾斜位移D2導致該引腳111之上表面為傾斜與位移，而不能提供較佳的打線平面，造成打線製程之困難。Referring to FIG. 1 , the conventional lead frame 100 mainly includes a plurality of pins 110 , a spoiler 120 , and a connecting strip 130 . The pins 110 are arranged on two relatively long sides of the lead frame 100. The spoiler 120 is located on two relatively shorter sides of the lead frame 100. The spoiler 120 is connected to the short strap 121. The frame dam 140 of the lead frame is further connected to the spoiler 120 to the adjacent one of the pins 111 by the connecting strip 130. The frame dam 140 is fixedly connected to the pins 110 and 111 and the spoiler 120. Referring to FIGS. 2 and 3, when the spoiler 120 is in a sinking state, one end of the connecting strip 130 and the spoiler 120 is formed with a depression 34 to make the lead. The foot 110 and the spoiler 120 are respectively located on a first plane 101 and a second plane 102. As shown in FIG. 2, at this time, the connecting strip 130 is subjected to a downward pulling force to generate a displacement D1, and the pin 111 is pulled, causing the pin 111 to generate a tilt displacement D2. A die attach tape 150 is attached to the lower surfaces of the pins 110 and 111 for bonding a wafer (not shown). As shown in the second and third figures, since the connected pin 111 is pulled and tilted, the pin 111 and the remaining pins 101 cannot be completely coplanar, so that the die bond tape 150 cannot be flat on the chip. Active face. Therefore, in the die bonding process, the die bond tape 150 and the wafer cannot be closely adhered, and the bonding strength between the pins 110 and 111 and the wafer is reduced, which is liable to cause wafer peeling. In addition, the tilt displacement D2 causes the upper surface of the pin 111 to be inclined and displaced, and does not provide a better wire bonding plane, which causes difficulty in the wire bonding process.
本發明之主要目的係在於提供一種具有下沉擾流板連接結構之導線架，可減少擾流板在形成下沉型態時對所連接之引腳拉扯，以避免與下沉擾流板連接引腳產生下拉之傾斜位移，以改善打線品質與黏晶接合強度。The main object of the present invention is to provide a lead frame having a sinking spoiler connection structure, which can reduce the pulling of the connected pin when the spoiler forms a sinking type to avoid connection with the sinking spoiler. The pin produces a pull-down tilt shift to improve wire quality and bond strength.
本發明之次一目的係在於提供一種具有下沉擾流板連接結構之導線架，提供水平之晶片黏貼面，以增強在黏晶製程中晶片與引腳的黏接強度。A second object of the present invention is to provide a lead frame having a sinker spoiler connection structure, which provides a horizontal wafer adhesive surface to enhance the bonding strength between the wafer and the lead in the die bonding process.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。依據本發明一種具有下沉擾流板連接結構之導線架，主要包含複數個引腳、一擾流板以及一多曲折連接條。該些引腳係形成於一第一平面。該擾流板係形成於一第二平面。該多曲折連接條係形成於該第一平面與該第二平面之間，以彈性連接該擾流板至鄰近之一引腳。本發明另揭示使用該導線架之一半導體封裝構造。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a lead frame having a sinker spoiler connection structure mainly includes a plurality of pins, a spoiler, and a plurality of meandering connecting strips. The pins are formed on a first plane. The spoiler is formed on a second plane. The multi-folded connecting strip is formed between the first plane and the second plane to elastically connect the spoiler to one of the adjacent pins. The invention further discloses a semiconductor package construction using the leadframe.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述的導線架中，該多曲折連接條係可為S形曲折。In the aforementioned lead frame, the multi-folded connecting strip may be an S-shaped meander.
在前述的導線架中，該多曲折連接條連接該擾流板之一端係可形成有一第一下沉彎折。In the above lead frame, the multi-folded connecting strip is connected to one end of the spoiler to form a first sinking bend.
在前述的導線架中，該多曲折連接條係可包含有一U形可位移部，並與該第一下沉彎折直接連接。In the aforementioned lead frame, the multi-folded connecting strip may include a U-shaped displaceable portion and is directly connected to the first sinking bend.
在前述的導線架中，可另包含有一框壩，以連接該些引腳與該擾流板。In the foregoing lead frame, a frame dam may be further included to connect the pins and the spoiler.
在前述的導線架中，該擾流板係可以複數個繫條連接至該框壩，每一繫條係形成有一第二下沉彎折。In the aforementioned lead frame, the spoiler may be connected to the frame dam by a plurality of tie bars, each of which is formed with a second sinking bend.
在前述的導線架中，上述與該多曲折連接條連接之引腳係可為一匯流條接地/電源引腳。In the above lead frame, the pin connected to the multi-folded connecting strip may be a bus bar ground/power pin.
在前述的導線架中，該多曲折連接條係可包含三個或更多的曲折。In the aforementioned lead frame, the multi-folded connecting strip may comprise three or more zigzags.
在前述的導線架中，可另包含有一黏晶膠帶，其係黏貼於該些引腳之下表面。In the foregoing lead frame, an adhesive tape may be further included, which is adhered to the lower surface of the pins.
依據本發明之一具體實施例，揭示一種具有下沉擾流板連接結構之導線架。通常導線架是在一片導電性的金屬薄片上，依照積體電路或電晶體等需要的電路腳數，以蝕刻(etching)或沖壓(punching)的方式形成所需之引腳數量。導線架除了用以設置晶片之外，同時也作為將元件的內部功能傳輸至外部印刷電路板。請參閱第4圖所示，一種具有下沉擾流板連接結構之導線架200主要包含複數個引腳210、一擾流板220以及一多曲折連接條230。該導線架200之材質係可為鐵、銅或其他金屬材料。非限定地，該些引腳210與211係可分別位於該導線架200之兩相對之較長側，而該擾流板220係位於該導線架200之兩相對較短側，並藉由該多曲折連接條230連接至該些引腳210之其中之一。如第4圖所示，該些引腳210中，被該多曲折連接條230所連接之引腳標示為211。藉由壓陷該擾流板220以使該擾流板220與該些引腳210之間具有一高度差(如第6圖所示)，以使該擾流板220能發揮較佳的上下模流平衡效果。請再參閱第6圖所示，該些引腳210係形成於該導線架200之一第一平面201。該些引腳210係分別排列在該導線架200之兩相對之較長側，其內端係往該導線架200之一中心線往內延伸以形成接指。請再參閱第6圖所示，該擾流板220係形成於該導線架200之一第二平面202。該擾流板220係可具有複數個擾流通孔223，用以較佳化擾流效果。由於該第一平面201係高於該第二平面202，故該擾流板220係為下沉型態(downset)設計，藉以達到在模封灌膠製程中平衡上下模流。According to an embodiment of the present invention, a lead frame having a sinker spoiler connection structure is disclosed. Usually, the lead frame is formed on a piece of conductive metal foil, and the required number of pins is formed by etching or punching according to the number of circuit pins required for an integrated circuit or a transistor. In addition to the placement of the wafer, the leadframe also serves to transfer the internal functions of the component to the external printed circuit board. Referring to FIG. 4, a lead frame 200 having a sinker spoiler connection structure mainly includes a plurality of pins 210, a spoiler 220, and a multi-folded connecting strip 230. The lead frame 200 may be made of iron, copper or other metal materials. Without limitation, the pins 210 and 211 are respectively located on opposite sides of the lead frame 200, and the spoiler 220 is located on two relatively shorter sides of the lead frame 200, and by the A plurality of meandering connecting strips 230 are coupled to one of the pins 210. As shown in FIG. 4, among the pins 210, the pin connected by the multi-folded connecting strip 230 is denoted as 211. By injecting the spoiler 220 to have a height difference between the spoiler 220 and the pins 210 (as shown in FIG. 6), the spoiler 220 can perform better. Mold flow balance effect. Referring to FIG. 6 again, the pins 210 are formed on a first plane 201 of the lead frame 200. The pins 210 are respectively arranged on two opposite long sides of the lead frame 200, and the inner ends thereof extend inwardly toward a center line of the lead frame 200 to form a finger. Referring to FIG. 6 again, the spoiler 220 is formed on a second plane 202 of the lead frame 200. The spoiler 220 can have a plurality of disturbing flow holes 223 for better effect of the spoiler. Since the first plane 201 is higher than the second plane 202, the spoiler 220 is a downset design, so as to balance the upper and lower mold flows in the mold filling process.
請參閱第5及6圖所示，該多曲折連接條230係形成於該第一平面201與該第二平面202之間，以彈性連接該擾流板220至鄰近之一引腳211，以減少該擾流板220在形成下沉型態時對該引腳211拉扯。在一實施例中，該多曲折連接條230係可為S形曲折(如第4圖所示)。請參閱第5圖所示，該多曲折連接條230係可包含三個或更多的曲折233。在此所指「曲折」係指形成與導線架同平面之彎曲。該多曲折連接條230連接該擾流板220之一端係可形成有一第一下沉彎折231，該第一下沉彎折231係可彎折成垂直或是其他角度。在此所指「下沉彎折」係指形成與導線架不同平面的彎曲。請參閱第5圖所示，該多曲折連接條230係可包含有一U形可位移部232，並與該第一下沉彎折231直接連接，以提供適當之彈性伸縮。請再參閱第5圖所示，該擾流板220在形成下沉型態時，該U型可位移部232可彈性地向下移動位移(如第5圖之位移量D3，但不致於影響到該引腳211)，使該擾流板220可向下位移且不會拉扯該引腳211而造成該引腳211之位移與歪斜。在另一實施例中，請參閱第8圖所示，與該多曲折連接條230連接之引腳211’係可為一匯流條接地/電源引腳，可形成為把手形狀。Referring to FIGS. 5 and 6, the plurality of zigzag connecting strips 230 are formed between the first plane 201 and the second plane 202 to elastically connect the spoiler 220 to one of the adjacent pins 211. The spoiler 220 is reduced to pull the pin 211 when forming a sinking pattern. In one embodiment, the multi-folded connecting strip 230 can be an S-shaped meander (as shown in FIG. 4). Referring to FIG. 5, the multi-folded connecting strip 230 may include three or more zigzags 233. As used herein, "tortuous" means forming a bend in the same plane as the lead frame. The multi-folded connecting strip 230 is connected to one end of the spoiler 220 to form a first sinking bend 231, and the first sinking bend 231 can be bent into a vertical or other angle. As used herein, "sinking and bending" means forming a curve that is different from the plane of the leadframe. Referring to FIG. 5, the multi-folded connecting strip 230 can include a U-shaped displaceable portion 232 and is directly coupled to the first sinking bend 231 to provide proper elastic expansion and contraction. Referring to FIG. 5 again, when the spoiler 220 forms a sinking type, the U-shaped displaceable portion 232 can elastically move downward (for example, the displacement amount D3 in FIG. 5, but does not affect To the pin 211), the spoiler 220 can be displaced downward without pulling the pin 211 to cause displacement and skew of the pin 211. In another embodiment, as shown in FIG. 8, the pin 211' connected to the multi-folded connecting strip 230 may be a bus bar ground/power pin, which may be formed in a handle shape.
請參閱第4圖所示，該導線架200中係可另包含有一框壩240，以連接該些引腳210與211與該擾流板220。具體而論，該擾流板220係可以複數個繫條221連接至該框壩240，每一繫條221係形成有一第二下沉彎折222。由於該擾流板220之兩端係分別與該引腳211以及該框壩240連接，故可避免在模封灌膠製程中受模流衝擊而變形。請參閱第6圖所示，該導線架200中係可另包含有一黏晶膠帶250，其係黏貼於該些引腳210之內端接指之下表面，用以黏著固定一晶片10(如第7圖所示)於該些引腳210(包含被該多曲折連接條230所連接之引腳211)。Referring to FIG. 4, the lead frame 200 can further include a frame dam 240 for connecting the pins 210 and 211 and the spoiler 220. In particular, the spoiler 220 can be connected to the frame dam 240 by a plurality of tie bars 221, and each tie bar 221 is formed with a second sinker bend 222. Since the two ends of the spoiler 220 are respectively connected to the pin 211 and the frame dam 240, it can be prevented from being deformed by the impact of the mold flow in the molding and potting process. As shown in FIG. 6, the lead frame 200 may further include an adhesive tape 250 adhered to the lower surface of the inner end of the pins 210 for bonding and fixing a wafer 10 (eg, Figure 7 shows the pins 210 (including the pins 211 connected by the multi-folded connecting strip 230).
因此，藉由該多曲折連接條230之設置，能減少該擾流板220在形成下沉型態時對該引腳211之拉扯，以避免該引腳211產生向下傾斜位移。並可使該些引腳210與211在該擾流板220形成下沉型態後，仍係位於該第一平面201，特別是該引腳211無位移與歪斜的現象(如第5及6圖所示)，使得該黏晶膠帶250可與每一引腳210與211呈水平之緊密貼合，以增強在黏晶製程中該些引腳210與211與晶片之間的黏接強度。此外，由於該引腳211並不會有傾斜位移之問題，故可增加在打線製程中銲線與該引腳211之鍵合強度，也不會有無法打線之問題。Therefore, by the arrangement of the multi-folded connecting strip 230, the pulling of the pin 211 by the spoiler 220 when forming the sinking mode can be reduced to avoid the downward tilting displacement of the pin 211. And the pins 210 and 211 are still located in the first plane 201 after the spoiler 220 is in a sinking state, in particular, the pin 211 has no displacement and skew (such as 5th and 6th). As shown in the figure, the adhesive tape 250 can be horizontally adhered to each of the leads 210 and 211 to enhance the bonding strength between the pins 210 and 211 and the wafer in the die bonding process. In addition, since the pin 211 does not have a problem of tilt displacement, the bonding strength of the bonding wire to the pin 211 in the wire bonding process can be increased, and there is no problem that the wire cannot be wired.
依據本發明之上述具體實施例，該導線架200可進一步應用於一半導體封裝構造。請參閱第7圖，一種半導體封裝構造包含該導線架200之該些引腳210與該擾流板220、一晶片10、複數個電性連接元件20以及一封膠體30。該晶片10係具有一主動面11，該主動面11上係設有複數個銲墊12，以作為該晶片10之對外電極。該晶片10之該主動面11係黏貼於該黏晶膠帶250，使該晶片10係貼附於該些引腳210與211。藉由該多曲折連接條230使得該擾流板220形成下沉型態後，該些引腳210(包含該引腳211)仍可提供水平之晶片黏貼面，故能增強該些引腳210與該晶片10之間的黏接強度及避免該晶片10剝離。請參閱第7圖，該導線架200係應用於「引腳在晶片上」(Lead－on－Chip，LOC)封裝，可不具有晶片10承座(die pad)，而是以該些引腳210(包含該引腳211)作為該晶片10之固定。此外，本發明並不限定該導線架200僅能運用於引腳在晶片上封裝，亦可應用於「晶片在引腳上」(Chip－on－Lead，COL)封裝。該些電性連接元件20係電性連接該晶片10之該些銲墊12至該些引腳210與211。在本實施例中，該些電性連接元件20係包含複數個銲線。該封膠體30係以壓模方式形成，其係密封該晶片10、該些電性連接元件20、該擾流板220以及該些引腳210與211之一部位，用以避免受外界污染物侵入污染。In accordance with the above-described embodiments of the present invention, the leadframe 200 can be further applied to a semiconductor package construction. Referring to FIG. 7 , a semiconductor package structure includes the leads 210 of the lead frame 200 and the spoiler 220 , a wafer 10 , a plurality of electrical connecting elements 20 , and a colloid 30 . The wafer 10 has an active surface 11 on which a plurality of pads 12 are provided to serve as external electrodes of the wafer 10. The active surface 11 of the wafer 10 is adhered to the die bonding tape 250, and the wafer 10 is attached to the pins 210 and 211. After the spoiler 220 is formed into a sinking type by the multi-folded connecting strip 230, the pins 210 (including the pin 211) can still provide a horizontal wafer bonding surface, thereby enhancing the pins 210. The bonding strength with the wafer 10 and the peeling of the wafer 10 are avoided. Referring to FIG. 7, the lead frame 200 is applied to a "Lead-on-Chip (LOC) package, and may have no die pad, but with the pins 210. (Include this pin 211) as the fixing of the wafer 10. In addition, the present invention is not limited to the use of the lead frame 200 for pin-on-wafer packaging, and can also be applied to a "chip-on-lead" (COL) package. The electrical connection elements 20 are electrically connected to the pads 12 of the wafer 10 to the pins 210 and 211 . In this embodiment, the electrical connection elements 20 comprise a plurality of bonding wires. The encapsulant 30 is formed by stamping, sealing the wafer 10, the electrical connecting elements 20, the spoiler 220, and one of the pins 210 and 211 to avoid external pollutants. Invade pollution.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，本發明技術方案範圍當依所附申請專利範圍為準。任何熟悉本專業的技術人員可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention.
10．．．晶片10. . . Wafer
11．．．主動面11. . . Active surface
12．．．銲墊12. . . Solder pad
20．．．電性連接元件20. . . Electrical connection element
30．．．封膠體30. . . Sealant
100．．．導線架100. . . Lead frame
101．．．第一平面101. . . First plane
102．．．第二平面102. . . Second plane
110．．．引腳110. . . Pin
111．．．引腳111. . . Pin
120．．．擾流板120. . . Spoiler
121．．．繫條121. . . Tie
130．．．連接條130. . . Connecting strip
131．．．下沉彎折131. . . Sinking and bending
140．．．框壩140. . . Box dam
150．．．黏晶膠帶150. . . Adhesive tape
200．．．導線架200. . . Lead frame
201．．．第一平面201. . . First plane
202．．．第二平面202. . . Second plane
210．．．引腳210. . . Pin
211．．．引腳211. . . Pin
211’．．．引腳211’. . . Pin
220．．．擾流板220. . . Spoiler
221．．．繫條221. . . Tie
222．．．第二下沉彎折222. . . Second sinking bend
223．．．擾流通孔223. . . Disturbing flow hole
230．．．多曲折連接條230. . . Multi-folded connecting strip
231．．．第一下沉彎折231. . . First sinking bend
232．．．U形可位移部232. . . U-shaped displacement
233．．．曲折233. . . tortuous
240．．．框壩240. . . Box dam
250．．．黏晶膠帶250. . . Adhesive tape
D1．．．習知連接條之位移量D1. . . Conventional connection strip displacement
D2．．．習知引腳之位移量D2. . . Conventional pin displacement
D3．．．多曲折連接條之位移量D3. . . The displacement of the multi-folded connecting strip
第1圖：習知導線架之平面示意圖。Figure 1: Schematic diagram of a conventional lead frame.
第2圖：繪示習知導線架在形成下沉彎折時引腳之位移區域示意圖。Fig. 2 is a schematic view showing the displacement area of the pin when the conventional lead frame is bent and formed.
第3圖：習知導線架在形成下沉彎折後沿擾流板剖切之示意圖。Figure 3: Schematic diagram of a conventional lead frame cut along a spoiler after forming a sinking bend.
第4圖：依據本發明之一具體實施例，一種具有下沉擾流板連接結構之導線架之平面示意圖。Figure 4 is a plan view showing a lead frame having a sinking spoiler connection structure in accordance with an embodiment of the present invention.
第5圖：依據本發明之一具體實施例，繪示該導線架中一多曲折連接條之位移區域示意圖。Figure 5 is a schematic view showing a displacement area of a multi-folded connecting strip in the lead frame according to an embodiment of the present invention.
第6圖：依據本發明之一具體實施例，沿該導線架之擾流板剖切之示意圖。Figure 6 is a schematic cross-sectional view of a spoiler along the lead frame in accordance with an embodiment of the present invention.
第7圖：依據本發明之一具體實施例，使用該導線架之半導體封裝構造並沿該擾流板剖切之示意圖。Figure 7 is a schematic illustration of a semiconductor package construction using the leadframe and cut along the spoiler in accordance with an embodiment of the present invention.
第8圖：依據本發明之一具體實施例，繪示該導線架中另一變化之引腳之局部平面示意圖。Figure 8 is a partial plan view showing another variation of the lead frame in the lead frame according to an embodiment of the present invention.
210．．．引腳210. . . Pin
211．．．引腳211. . . Pin
220．．．擾流板220. . . Spoiler
230．．．多曲折連接條230. . . Multi-folded connecting strip
231．．．第一下沉彎折231. . . First sinking bend
232．．．U形可位移部232. . . U-shaped displacement
233．．．曲折233. . . tortuous
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW97100499A TWI469276B (en) | 2008-01-04 | 2008-01-04 | Leadframe and semiconductor package having downset spoilers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW97100499A TWI469276B (en) | 2008-01-04 | 2008-01-04 | Leadframe and semiconductor package having downset spoilers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200931604A TW200931604A (en) | 2009-07-16 |
| TWI469276B true TWI469276B (en) | 2015-01-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW97100499A TWI469276B (en) | 2008-01-04 | 2008-01-04 | Leadframe and semiconductor package having downset spoilers |
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| Country | Link |
|---|---|
| TW (1) | TWI469276B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW449855B (en) * | 2000-07-18 | 2001-08-11 | Siliconware Precision Industries Co Ltd | Pasted plastic cloth structure of turbulence plate |
| TW517369B (en) * | 2000-07-10 | 2003-01-11 | Siliconware Precision Industries Co Ltd | Deflector plate structure having downward bending portion |
| TW200707517A (en) * | 2005-08-02 | 2007-02-16 | Chipmos Technologies Inc | Chip package having asymmetric molding |
| TW200713618A (en) * | 2005-09-26 | 2007-04-01 | Chipmos Technologies Inc | Semiconductor package for improving chip shift during molding |
-
2008
- 2008-01-04 TW TW97100499A patent/TWI469276B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW517369B (en) * | 2000-07-10 | 2003-01-11 | Siliconware Precision Industries Co Ltd | Deflector plate structure having downward bending portion |
| TW449855B (en) * | 2000-07-18 | 2001-08-11 | Siliconware Precision Industries Co Ltd | Pasted plastic cloth structure of turbulence plate |
| TW200707517A (en) * | 2005-08-02 | 2007-02-16 | Chipmos Technologies Inc | Chip package having asymmetric molding |
| TW200713618A (en) * | 2005-09-26 | 2007-04-01 | Chipmos Technologies Inc | Semiconductor package for improving chip shift during molding |
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| Publication number | Publication date |
|---|---|
| TW200931604A (en) | 2009-07-16 |
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