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經濟部智慧財產局員工消費合作社印製 五、發明說明（f ) 本發明是有關於一種擾流板貼膠布結構’且特別是有 關於一種應用於半導體之導線架型態封裝之擾流板結構° 在現今資訊爆炸的世界，積體電路已與日常生活有 密不可分的關係，無論在食衣住行育樂方面’都常會用到 積體電路元件所組成之產品。隨著電子科技的不斷演進’ 更人性化、功能性更複雜之電子產品不斷推陳佈新’然而 各種產品無不朝向輕、薄、短、小的趨勢設計’以提供更 便利舒適的使用。 在半導體製程上，已邁入0.18微米積體電路的量產 時代，積極度更高的半導體產品已垂手可得。而積體電路 (Integrated Circuits，1C)的生產’主要分爲二個階段：砂 晶片的製造、積體電路的製作以及積體電路的封裝 (Package)等。就積體電路的封裝而言，此即是完成積體 電路成品的最後步驟。封裝之目的在於提供晶片（Die)與 印刷電路板（Printed Circuit Board ’ PCB)或其他適當元件 之間電性連接的媒介及保護晶片。 在完成半導體製程後，晶片係由晶圓（Wafer)切割形 成。一般在晶片的周邊具有焊墊（BoncHng Pad)，其作用 爲提供晶片檢測之測試點，以及提供晶片與其他元件間 連接之端點。爲了連接晶片和其他元件，因此必須使用 導線（Wire)或凸塊（Bump)作爲連接之媒介。 對一般的半導體記憶體而言，如動態隨機存取記億 體（Dynamic Random Access Memory，DRAM) ’ 其晶片所 使用之封裝的方式，目前主要有小型J型外引腳封裝 — — — — — —----f I ---I--I — — — — — — — » (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4.49 85 b 6084twf.doc/0〇8 五、發明說明（>) (Small Outline J-Lead，SOJ)，與小型外引腳封裝（Thin Small Outline Package，TSOP)兩種。 然而，値得一提的是，在小型J型外引腳封裝（SOJ) 或小型外引腳封裝（TSOP)中，就導線架（Lead Frame)而 言，又可區分爲晶片上有導腳封裝（Lead On Chip，LOC)， 主要做爲動態隨機存取記憶體(DRAM)之封裝結構，其優 點爲傳輸速度快、散熱佳、以及結構小’爲IBM在1988 年之發明，比如US Patent 4,862,245。或導腳上有晶片封 裝(Chip On Lead COL)，如 US Patent 4,989,068 等之導線 架。Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (f) The present invention relates to a spoiler structure with adhesive tape, and in particular to a spoiler structure used in a lead frame type package for semiconductors. ° In today's world of information explosion, integrated circuits have an inseparable relationship with daily life. No matter in terms of food, clothing, living, and entertainment, 'products composed of integrated circuit components are often used. With the continuous evolution of electronic technology, more and more electronic products with more humane functions and more sophisticated features are constantly being promoted. However, all kinds of products are designed to be light, thin, short, and small, to provide more convenient and comfortable use. In the semiconductor manufacturing process, the mass production of 0.18 micron integrated circuits has entered the era, and more aggressive semiconductor products are readily available. The production of integrated circuits (1C) is mainly divided into two stages: the manufacture of sand chips, the manufacture of integrated circuits, and the packaging of integrated circuits. As far as the packaging of integrated circuits is concerned, this is the final step to complete the finished integrated circuit. The purpose of packaging is to provide a medium for the electrical connection between the die and the printed circuit board (PCB) or other appropriate components and to protect the chip. After the semiconductor process is completed, the wafer is formed by wafer cutting. Generally, there are solder pads (BoncHng Pad) on the periphery of the wafer, which are used to provide test points for wafer inspection and provide endpoints for the connection between the wafer and other components. In order to connect the chip and other components, it is necessary to use wires or bumps as the connection medium. For general semiconductor memory, such as Dynamic Random Access Memory (DRAM) ', the packaging methods used for its chips are currently mainly small J-type outer pin packages — — — — — —---- f I --- I--I — — — — — — — »(Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4.49 85 b 6084twf.doc / 0〇 5. Description of the Invention (Small Outline J-Lead, SOJ) Thin Small Outline Package (TSOP). However, it is worth mentioning that in the small J-shaped outer lead package (SOJ) or small outer lead package (TSOP), as far as the lead frame is concerned, it can be distinguished as having lead pins on the chip. Lead on chip (LOC) is mainly used as the packaging structure of dynamic random access memory (DRAM). Its advantages are fast transmission speed, good heat dissipation, and small structure. It was invented by IBM in 1988, such as US Patent 4,862,245. Or chip on lead (COL), such as US Patent 4,989,068, etc.
請參照第1圖，其所繪示爲習知小型外引腳封裝LOC 架構剖面示意圖° 如第1圖所示，以習知晶片上有導腳封裝(LOC)爲例， 其中晶片108係利用黏著層110固定於導腳109下，再覆 蓋以封裝膠體(Mold Compound)，具有上膠體106及下膠 體102，以封裝成型。上膠體〗06具有厚度116，而下膠 體102具有厚度114，而厚度116與厚度114之比例爲1 : 3,封裝後會因上下膠體的厚度及體積不同，因此上膠體106 與下膠體102在冷凝時收縮量亦不同，而導致整個封裝構 件產生扭曲變形(Warpage)。 因此，本發明就是在提供·一種擾流板貼膠布結構， 以達到上下模組件內之膠體比例平衡，使其在冷凝時收縮 量相等，而防止封裝構件扭曲變形。 根據本發明之上述及其他目的，提出一種擾流板貼 4 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公爱） ---------- I Ϊ ! i 丨 _ I II I 訂--I I II I I · <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 d9 A7 6084twf. doc/008 B7 五、發明說明（、） 膠布結構，應用於半導體之導線架型態封裝構件’包括： 導線架'晶片、黏著層、膠布、擾流板、上膠體'以及下 膠體β其中導線架具數個導腳’藉由黏著層將晶片配置於 導腳下。位於晶片之兩側具有二片擾流板，而擾流板其前 端上折至與導線架同平面並形成一凹型空間。接著，將膠 布貼於擾流板之前端與導線架接合之平面處，可防止擾流 板因前端未固定，易受模流(Mold Flow)的衝擊而產生上下 翹曲及外露的問題。最後’覆蓋封裝膠體於導線架之上、 下方，以完成封裝。而藉由調整擾流板所形成之凹型空間 之大小，以達到上下模組件內之膠體比例平衡，防止封裝 構件扭曲變形。 依照本發明之較佳實施例’本發明擾流板貼膠布結 構’應用於半導體之導線架型態封裝構件，係藉由調整擾 流板所形成之凹型空間之大小’可使上膠體與下膠體具有 相同之體積。其在冷凝時收縮量相等，因而防止封裝構件 之扭曲變形。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂’下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖所繪示爲習知小型外引腳封裝L〇c架構剖面 示意圖。 第2A圖繪示依照本發明較佳實施例一種擾流板貼膠 布結構剖面示意圖。 5 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐〉 I I I---r I--- — I * I I-----訂·！ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 d 9 δ5 5 a? 6084twf.doc/008 B7 五、發明說明（y) 第2B圖繪示依照本發明較佳實施例一種擾流板貼膠 布結構剖面模流示意圖。 第3A圖及第3B圖繪示依照本發明較佳實施例一種 擾流板貼膠布結構平面及半剖面示意圖。 圖式之標示說明： 102、202 :下膠體 106、206 :上膠體 1〇4、204 :導線架 108、 208 :晶片 110、210 :黏著層 114、116 :厚度 220 :擾流板 216 :前端 218 :膠布 222 :凹型空間 109、 224 :導腳 240 :入口 242 :模流 3 02 :開孔 實施例 請參照第2A圖，其所繪示爲依照本發明之較佳實施 例一種擾流板貼膠布結構剖面示意圖。在此實施例中，是 以承載器爲導線架且晶片上有導腳封裝（LOC)之型式爲例 來作說明。 6 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） ------„--------裝--------訂----線 <請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 4 49 8^ 5 6084twf.doc/008 五、發明說明（c ) 如第2A圖所示，本發明擾流板貼膠布結構，應用於 半導體之導線架型態封.裝構件，至少包括：一導線架204、 —一晶片208、一黏著層210'數個膠布218、數個擾流板220、 上膠體206、以及下膠體202，其中導線架204具有複數 個導腳224。 本發明之擾流板貼膠布結構係採用導線架204作爲承 載器，而導線架204包括：多個導腳（lead)224，藉由黏著 層210將晶片208配置於導腳224下。其中黏著層可爲聚 亞醯胺（Polyimide)或不導電膠，導腳224又可細分爲內導 腳部份及外導腳部份。而晶片208比如是動態隨機存取記 憶體（DRAM)、唯讀記憶體（ROM)、靜態隨機存取記憶體 (SRAM)、快閃記憶體（Flash Memory)、邏輯電路晶片（LOGIC) 或類比晶片（ANALOG)等各種積體電路晶片，均可應用於 本發明之封裝中。晶片208之表面上均具有多個金屬墊 (pad) ’至於晶片208與導線架204電性接合部份，可以利 用習知打導線方式（wire bonding)，以線型導電材料，比如 金線、鋁線或其他金屬線，將金屬墊與導腳224之內導腳 部份導電地連接。 位於晶片208之兩側具有二片擾流板220,而擾流板220 其前端216上折至與導線架204同平面並形成一凹型空間 222。接著’將膠布218貼於該擾流板220之前端216與 導線架204接合之平面處。最後，覆蓋封裝膠體2〇6於導 線架204之上、下方。藉由調整擾流板220所形成之凹型 空間222之大小，可使上膠體206與該下膠體202具有相 同之體積，並完成最後包裝及成型的部份。 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — I- — — — — — — 一*J·11111111 (請先閱讀背面之注i項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Please refer to Figure 1, which shows a schematic cross-sectional view of a conventional small outer-lead package LOC structure. As shown in Figure 1, a conventional chip-on-lead package (LOC) is used as an example. The chip 108 uses The adhesive layer 110 is fixed under the guide pin 109, and then covered with a mold compound (Mold Compound), which has an upper compound 106 and a lower compound 102 for packaging and molding. Upper colloid 06 has a thickness of 116, and lower colloid 102 has a thickness 114, and the ratio of thickness 116 to thickness 114 is 1: 3. After packaging, the thickness and volume of the upper and lower colloids are different, so the upper colloid 106 and the lower colloid 102 are in the The amount of shrinkage during condensation is also different, resulting in warpage of the entire package. Therefore, the present invention is to provide a spoiler tape structure to achieve a balanced gel proportion in the upper and lower mold components, to make the shrinkage equal when condensing, and to prevent the package member from being deformed. According to the above and other objectives of the present invention, a spoiler sticker is proposed. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 public love) ---------- I Ϊ! I 丨 _ I Order II I--II II II < Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs d9 A7 6084twf. Doc / 008 B7 V. Description of the invention (,) Tape structure The lead frame type packaging components used in semiconductors include: lead frame 'wafer, adhesive layer, adhesive tape, spoiler, upper colloid' and lower colloid β, among which the lead frame has several guide pins', and the chip is passed through the adhesive layer. Placed under the guide feet. There are two spoilers on both sides of the wafer, and the front end of the spoiler is folded to the same plane as the lead frame and forms a concave space. Next, stick the adhesive tape on the plane where the front end of the spoiler joins the lead frame, which can prevent the spoiler from being warped and exposed due to the impact of the mold flow due to the unfixed front end. Finally, the packaging gel is covered above and below the lead frame to complete the packaging. By adjusting the size of the concave space formed by the spoiler, the proportion of colloids in the upper and lower mold components can be balanced to prevent the package members from being deformed. According to a preferred embodiment of the present invention, the “spoiler structure of the spoiler of the present invention” is applied to a lead frame type packaging component of a semiconductor, and the upper colloid and the bottom are adjusted by adjusting the size of the concave space formed by the spoiler Colloids have the same volume. It shrinks equally when condensed, thereby preventing distortion of the package member. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1 Shown is a schematic cross-sectional view of a conventional small external lead package Loc architecture. FIG. 2A is a schematic cross-sectional view showing a structure of a spoiler tape according to a preferred embodiment of the present invention. 5 This paper size applies to Chinese National Standard < CNS) A4 specification (210 X 297 mm) II I --- r I --- — I * I I ----- Order · (Please read the Note for refilling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 d 9 δ5 5 a? 6084twf.doc / 008 B7 V. Description of the invention (y) Figure 2B shows a preferred embodiment of the present invention. Schematic diagram of the cross-section mold flow of the structure of the spoiler tape. Figures 3A and 3B show a schematic plan and half-section diagram of the structure of the spoiler with tape in accordance with a preferred embodiment of the present invention. Lower colloid 106, 206: Upper colloid 104, 204: Lead frame 108, 208: Wafer 110, 210: Adhesive layer 114, 116: Thickness 220: Spoiler 216: Front end 218: Tape 222: Recessed space 109, 224 : Guide leg 240: Entrance 242: Mold flow 3 02: Opening hole embodiment Please refer to FIG. 2A, which is a schematic cross-sectional view of a spoiler tape structure according to a preferred embodiment of the present invention. In this embodiment In the description, a carrier is used as a lead frame and a lead package (LOC) is provided on the chip as an example. 6 The paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) ------ „-------- installation -------- order ---- (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau Staff of the Ministry of Economic Affairs 4 49 8 ^ 5 6084twf.doc / 008 5. Description of the Invention (c) As shown in Figure 2A, The spoiler tape structure of the present invention is applied to the lead frame type sealing of semiconductors. The mounting component includes at least: a lead frame 204, a wafer 208, an adhesive layer 210 ', a plurality of adhesive tapes 218, and a plurality of spoilers. 220, upper colloid 206, and lower colloid 202, wherein the lead frame 204 has a plurality of guide legs 224. The spoiler structure of the present invention uses the lead frame 204 as a carrier, and the lead frame 204 includes: a plurality of guide legs (Lead) 224, the wafer 208 is arranged under the guide pin 224 through the adhesive layer 210. The adhesive layer can be polyimide or non-conductive glue, and the guide pin 224 can be subdivided into the inner guide pin portion and The outer guide pin part, and the chip 208 is, for example, dynamic random access memory (DRAM), read-only memory (ROM), static random access memory (SRAM) Various integrated circuit chips such as flash memory, logic circuit chip (LOGIC) or analog chip (ANALOG) can be used in the package of the present invention. There are multiple metal pads on the surface of the chip 208. As for the electrical bonding part of the chip 208 and the lead frame 204, a wire-type conductive material such as gold wire, aluminum can be used by conventional wire bonding. Wire or other metal wire, the metal pad is electrically conductively connected to the inner guide pin portion of the guide pin 224. Two spoilers 220 are located on both sides of the chip 208, and the front end 216 of the spoiler 220 is folded to the same plane as the lead frame 204 and forms a concave space 222. Then, 'the adhesive tape 218 is affixed to the plane where the front end 216 of the spoiler 220 and the lead frame 204 are joined. Finally, the covering encapsulant 206 is above and below the lead frame 204. By adjusting the size of the concave space 222 formed by the spoiler 220, the upper colloid 206 and the lower colloid 202 can have the same volume, and the final packaging and molding parts can be completed. 7 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) — — — — — — — I- — — — — — — * J · 11111111 (Please read the note i on the back before filling (This page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
Ad9855 A7 6084twf.doc/008 gy 五、發明說明（& ) 請參照第2B圖，其所繪示爲依照本發明之較佳實施 例一種擾流板貼膠布結構剖面模流示意圖。値得一提的 是，如第2B圖所示，於左方入口 240處壓注膠材，此時 模流242之方向會順延著擾流板220,由左至右塡滿模穴， 並同時形成上膠體206及下膠體202。將嘐布218貼於擾 流板220之前端216與導線架204接合平面處之目的，是 爲了防止擾流板220因前端216未固定，易受模流242(Mold Flow)的衝擊而產生上下翹曲及外露的問題。 其中，上膠體206與下膠體202之材質，比如是環氧 樹脂(Epoxy)等絕緣材質，具有相同之體積，可使其在冷凝 時收縮量相等，而防止封裝構件之扭曲變形。 請參照第3A圖及第3B圖，其所繪示依照本發明較佳 實施例一種擾流板貼膠布結構平面及半剖面示意圖。 如第3A圖所示，在擾流板貼膠布結構之上視圖中， 可觀察到擾流板220更包括數個開孔302，目的是爲了在 不影響模流之情況下，以減少擾流板220材料，及改善應 力分佈的問題，增強封裝構件之結構力。 如第3B圖所示，其所繪示依照本發明較佳實施例一 種擾流板貼膠布結構半剖面示意圖。爲對應第3A圖之 3B-3B剖視圖，亦爲2A圖之部分詳圖，僅以半剖面之方 式繪示。而後續將外導腳折彎成型（forming)的部份，以及 外導腳與電路板間以表面焊接技術（Surface Mount Technique，SMT)接合部份，由於與習知技術相同，在此 不再贅述。 綜上所述，本發明至少具有下列優點：Ad9855 A7 6084twf.doc / 008 gy 5. Explanation of the invention Please refer to FIG. 2B, which is a schematic diagram of a cross-sectional mold flow of a spoiler tape structure according to a preferred embodiment of the present invention. It is worth mentioning that, as shown in Figure 2B, the plastic material is injected at the left inlet 240, and the direction of the mold flow 242 will run along the spoiler 220, and the mold cavity will be filled from left to right, and The upper colloid 206 and the lower colloid 202 are formed at the same time. The purpose of attaching the cloth 218 to the plane where the front end 216 of the spoiler 220 and the lead frame 204 is jointed is to prevent the spoiler 220 from being fixed by the front end 216 and easily susceptible to the impact of mold flow 242. Warping and exposed problems. Among them, the material of the upper colloid 206 and the lower colloid 202, such as epoxy resin (Epoxy), have the same volume, which can make them shrink equally when they are condensed, and prevent distortion of the packaging member. Please refer to FIG. 3A and FIG. 3B, which are schematic plan and half cross-sectional views of a structure of a spoiler tape according to a preferred embodiment of the present invention. As shown in Figure 3A, in the top view of the spoiler structure, it can be observed that the spoiler 220 further includes a plurality of openings 302, in order to reduce the turbulence without affecting the mold flow. The material of the board 220 and the problem of improving the stress distribution enhance the structural force of the package member. As shown in FIG. 3B, a half-section schematic diagram of a structure of a spoiler tape according to a preferred embodiment of the present invention is shown. It is the 3B-3B sectional view corresponding to Figure 3A, and it is also a partial detailed view of Figure 2A. It is only shown in a half-section manner. The subsequent forming of the outer guide pin and the joining portion between the outer guide pin and the circuit board by Surface Mount Technique (SMT) are the same as the conventional technique, and will not be repeated here. To repeat. In summary, the present invention has at least the following advantages:
S ^紙張尺度適用t國國家標準（CNS)A4 ^格（210 X 297公釐） — — — — — —— — I I I I I I ·1111111 »1 — — — — — — — (請先閱讀背面之注意事項再填寫本頁) “9855 6084t\vf.doc/008 五、發明說明（） 1. 在原有的導線架之兩側設置二片擾流板，其中擾流 板形成一凹型空間，其前端並上折至與該導線架同平面。 藉由調整擾流板所形成之凹型空間之大小，即可使塡入之 上膠體與下膠體之體積比例平衡，使其在凝時收縮量相 等，防止封裝構件之扭曲變形。 2. 於擾流板之前端與導線架接合之平面處貼上膠布， 可防止擾流板因前端未固定，易受模流的衝擊而產生上下 翹曲及外露的問題。 3. 在擾流板開設數個開孔，可在不影響模流之情況 下，改善應力分佈的問題，增強封裝構件之結構力。 雖然本發明已以一較佳實施例掲露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）S ^ paper size is applicable to National Standards (CNS) A4 ^ (210 X 297 mm) — — — — — — — — IIIIII 1111111 »1 — — — — — — — (Please read the notes on the back first (Fill in this page again) "9855 6084t \ vf.doc / 008 5. Description of the invention () 1. Set two spoilers on both sides of the original lead frame, where the spoiler forms a concave space, and the front end is Fold to the same plane as the lead frame. By adjusting the size of the concave space formed by the spoiler, the volume ratio of the upper colloid to the lower colloid can be balanced to make the shrinkage equal when set, preventing packaging Distortion of the component 2. Adhesive tape is attached to the plane where the front end of the spoiler joins the lead frame, which can prevent the spoiler from being warped and exposed due to the impact of the mold flow due to the unfixed front end. 3. Opening several openings in the spoiler can improve the problem of stress distribution and enhance the structural force of the packaging component without affecting the mold flow. Although the present invention has been disclosed above in a preferred embodiment, then It is not intended to limit the invention, Anyone skilled in this art can make some changes and retouch without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read first Note on the back, please fill in this page again.) The paper printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is compliant with China National Standard (CNS) A4 (210 X 297 mm).