TW449894B - Face-to-face multi-chip package - Google Patents

Face-to-face multi-chip package Download PDF

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Publication number
TW449894B
TW449894B TW088100113A TW88100113A TW449894B TW 449894 B TW449894 B TW 449894B TW 088100113 A TW088100113 A TW 088100113A TW 88100113 A TW88100113 A TW 88100113A TW 449894 B TW449894 B TW 449894B
Authority
TW
Taiwan
Prior art keywords
face
chip package
wafers
item
patent application
Prior art date
Application number
TW088100113A
Other languages
Chinese (zh)
Inventor
Ming-Jr Shiuan
Jeng-De Lin
Original Assignee
United Microelectronics Corp
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Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW088100113A priority Critical patent/TW449894B/en
Application granted granted Critical
Publication of TW449894B publication Critical patent/TW449894B/en

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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract

This invention is about the face-to-face multi-chip package. For the face-to-face multi-chip package, flip-chip technique is used and multi-chips are arranged face-to-face for each other. Additionally, bumps are used to make chips electrically connect with each other, and multi-chips are packaged on the same carrier. Besides, anisotropic conductive glue can be used to fill in between these chips when performing the packaging process so as to improve the electric connection in between chips. Because the flip-chip technique is adopted, the manner of face array can be used for the arrangement of metal pads on the chip to increase package integration. Furthermore, during the packaging filling, part of chip backside can be exposed or arranged with a heat dissipation plate in order to raise the heat dissipation effects.

Description

4 4989 A 403hwrdn<:/(m A7 -----·~_______________ .. -7-________ 五、發明説明（丨' ) 本發明是有關於一種半導體封裝結構，且特別是有關 於—種面對面型多晶片封裝（face_t〇-face multi-chip package)。 隨著半導體業的進展，許多相關技術也日新月異地不 斷演進中。就半導體成品製造而言，一般可分爲三個階段， 〜爲半導體基底的形成’即磊晶技術部份；再則半導體元 件製造，諸如MOS製程、多重金屬內連線等；最後則是 封裝製程(Package)。然而現今所有電子產品之開發莫不朝 向輕、薄、短、小的目標發展，對於半導體來說即是提高 其積集度（Integration) ’至於封裝技術方面，則有晶片尺寸 封裝（Chip Scale Package，CSP)、多晶片型封裝(IVIuiti-Chip Module，MCM)等封裝技術的提出。由於半導體製程技術 已發展至線寬O.lSgm的元件生產，在積集度提高上有許 多突破，因此如何開發出相對應之小體積封裝，以達到產 品縮小化的目的，便成爲現今重要課題。此外，不管在電 月)¾上或民生用品上之應用，爲了縮小產品體積及節省封裝 成本，將多個晶片封裝在一起的多晶片型封裝，將是未來 的趨勢之一。多晶片型封裝可以將處理器（pr〇cess〇r)晶片 及曰己憶體(memory)晶片，或者邏輯電路(L〇gic)晶片及記憶 體晶片（包括DRAM及Flash Mem〇ry)封裝在—起，不但可 ^降低成本，縮小封裝體積，並可縮短訊號傳輸路徑了提 闻效能，並可使不同製程之晶片，合爲一封裝中，而並需 使用特殊整合製程生產。多晶片型封裝可適用於各獅能 及各種應用頻率之多晶片系統，例如： i-g己憶體晶片+微處理器晶片+電阻+電容+電感. 3 —- ,. — __ _ ___ 本紙张尺度埼;fl屮國阼家榡啥（) 乂4規210X297公釐） '~~~------- ("先閱讀背而之注意事項再填寫本頁) ,ιτ 線 4 4989 4 403 5 t\v f.doc/008 A7 五、發明说明（> ) 2.記億體晶片（DRAM)+邏輯電路晶片+記憶體晶片 (Flash Memory)； 3 .|頁比晶片（Anal〇g)+邏輯電路晶片+記億體晶片（包括 DRAM"、SRAM、Flash Memory)+電阻 +電谷電感 ...等等。 請參照第1圖，其所繪示爲一種習知多晶片型封裝。 目前應用於多晶片型封裝的承載器大部份以多層印刷電路 板(multi-level PCB)作爲基材lO(substrate)，而將多個晶片 12以絕緣膠14黏附於基材1〇上。晶片丨2上的焊墊（bonding pad)則以導線16與基材1〇上的接點連接，形成電性導通。 晶片12與基材1〇之連接，除了可以上述打導線(wire bonding)的方法連接外，亦可利用覆晶技術（flip chip or controlled collapse chip connection, C4)以凸塊（bump)作爲 連接。之後，再以樹脂18將晶片12及連接部份包裝起來， 而整個封裝與電路板的電性連接可採用習知錫球格狀陣列 封裝(Ball Grid Array, BGA)的方式，以錫球20與電路板 上的接點接合。然而，習知此種多晶片型封裝的缺點在於 其晶片係並列於同一平面，因此其封裝所佔之面積及體積 均較大’且晶片間建接的訊號路徑較長。此外’此種多晶 片型封裝即使採用覆晶技術作爲晶片與承載器之連接，雖 然可以略爲縮小封裝面積，然晶片間之連接還是利用基材 10上的印刷線路（未繪示），並無法有效改善縮短訊號路 徑，或縮小整體封裝面積及體積的問題。 爲了縮小多晶片型封裝的面積及體積’一種面對面 (face to face)的多晶片型封裝方式曾揭露於美國專利第 4 孓紙讯Λ政诚中國拽笑:標彳（（'NS ) ( 2i〇x 297/>t l ---- 邻先閱讀背而之注意事項再峨转本頁) -5° ¢)449894 4 03 5 t \vf doc/008 Λ 1 ______ B7 _ — 五、發明説明（今） ~ ' 533 1235號中。請參照第2圖，其所繪示爲習知面對面多 晶片型封裝的剖面示意圖。習知面對面多晶片型封裝主要 藉由將二晶片30、32具有元件的表面相互面對配置，而 採用的是軟片自動接合的方式（Tape Automatic Bonding, TAB) ° 在內腳接合的部份（Inner Lead Bonding, ILB)，二 晶片30、32係分別利用凸塊34、36與一具有導線的軟片 承載器38(film carrier)電性連接；而在外腳接合的部份 (Outer Lead Bonding, OLB)，貝[]與一導線架 40(lead frame) 連接’而二晶片30、32間還配置一錫球42，使得二晶片 3〇、32相互連接。二晶片30、32連同軟片承載器38及部 份導線架40，則以鑄模方式用樹脂44將其包覆。習知此 種多晶片型封裝的缺點在於：利用軟片自動接合的封裝方 式，還需透過導線架或其他載體與電路板接合’徒增訊號 傳輸路徑；此外，由於晶片間之連接是透過軟片承載器’ 因此晶片上之金屬墊(Pad)配置依然採用線配置或稱周緣配 置（line layout or peripheral layout)，對於將來局積集度之 半導體晶片，其輸出入接點（I/O nodes)劇增’此種配置將 不敷需求，且無法提高封裝的積極度。 因此本發明目的之一就是在提供一種面對面型多晶片 封裝，可將多個晶片封裝在同一個承載器上。 本發明的另一目的在於提供一種面對面型多晶片封 裝’縮短晶片與晶片間的訊號傳輸路徑，提高晶片的效能。 本發明的再一目的在於提供一種面對面型多晶片*寸 裝，晶片間採用面對面配置，以降低封裝之面積及體積。 本發明又一目的在於提供一種面對面多晶片封裝結 5 _ 木纸认尺度垅；11中阀固家摞嗲（（，NS ) Λ4说招（2彳0X297公麓） (計先間讀背而之注意事項再填寫本頁)4 4989 A 403hwrdn <: / (m A7 ----- · ~ _______________ .. -7 -________ V. Description of the invention (丨 ') The present invention relates to a semiconductor package structure, and in particular, to a face-to-face Multi-chip package (face_t〇-face multi-chip package). With the progress of the semiconductor industry, many related technologies are constantly evolving with each passing day. As far as the manufacture of semiconductor finished products, they can generally be divided into three stages, which are semiconductors. The formation of the substrate is the epitaxial technology part; then the semiconductor device manufacturing, such as MOS process, multi-metal interconnects, etc .; and finally the packaging process (Package). However, the development of all electronic products today is not light, thin, The short and small target development is for semiconductors to improve their integration. As for packaging technology, there are chip scale packages (CSP), multi-chip packages (IVIuiti-Chip Module, MCM) and other packaging technologies. Since the semiconductor process technology has developed to line width O.lSgm component production, there are many breakthroughs in improving the accumulation, so how to develop It has become a very important issue to achieve the corresponding small volume packaging to achieve the purpose of product shrinkage. In addition, whether it is applied to the electric month) or consumer products, in order to reduce the volume of the product and save packaging costs, multiple Multi-chip-type packages with chips packaged together will be one of the future trends. The multi-chip type package can package a processor chip and a memory chip, or a logic circuit chip and a memory chip (including DRAM and Flash Memory). Together, it can not only reduce costs, reduce package size, but also shorten the signal transmission path, improve the performance of the signal, and enable chips of different processes to be integrated into a package, and special integration processes must be used for production. The multi-chip package can be applied to multi-chip systems of various Lion and various application frequencies, such as: ig memory chip + microprocessor chip + resistor + capacitor + inductance. 3 —-,. — __ _ ___ This paper size屮; fl 屮 国 阼 家 榡 家 () 规 4 rules 210X297 mm) '~~~ ------- (" Read the precautions before filling this page), ιτ 线 4 4989 4 403 5 t \ v f.doc / 008 A7 V. Description of the invention (>) 2. Memory chip (DRAM) + logic circuit chip + memory chip (Flash Memory); 3. | Page than chip (Anal. g) + logic circuit chip + memory chip (including DRAM ", SRAM, Flash Memory) + resistance + electric valley inductance ... and so on. Please refer to FIG. 1, which shows a conventional multi-chip package. Most of the carriers currently applied to multi-chip type packages use multi-level PCBs as a substrate 10, and a plurality of wafers 12 are adhered to the substrate 10 with an insulating adhesive 14. The bonding pads on the chip 2 are connected to the contacts on the substrate 10 by the wires 16 to form electrical conduction. In addition to the connection between the chip 12 and the substrate 10, in addition to the above-mentioned method of wire bonding, a flip chip or controlled collapse chip connection (C4) can also be used to use bumps as the connection. After that, the chip 12 and the connecting portion are packaged with resin 18, and the electrical connection between the entire package and the circuit board can be performed by the conventional Ball Grid Array (BGA) method, with the solder ball 20 Engage with contacts on a circuit board. However, it is known that the disadvantages of such a multi-chip type package are that the chips are juxtaposed on the same plane, so the area and volume occupied by the package are relatively large 'and the signal path between the chips is relatively long. In addition, even if this multi-chip package uses flip-chip technology as the connection between the chip and the carrier, although the packaging area can be slightly reduced, the connection between the chips still uses printed wiring (not shown) on the substrate 10, and It cannot effectively improve the problem of shortening the signal path or reducing the overall package area and volume. In order to reduce the area and volume of a multi-chip type package, a face-to-face multi-chip type packaging method has been disclosed in U.S. Patent No. 4 孓 Paper News Λ Zhengcheng China Laughs: Standard (('NS) (2i 〇x 297 / > tl ---- Read the precautions before reading this page, and then turn this page) -5 ° ¢) 449894 4 03 5 t \ vf doc / 008 Λ 1 ______ B7 _ — V. Description of the invention (Today) ~ '533 1235. Please refer to FIG. 2, which is a schematic cross-sectional view of a conventional face-to-face multi-chip type package. The conventional face-to-face multi-chip package is mainly configured by placing the surfaces of the two chips 30 and 32 with components facing each other, and the tape automatic bonding method (Tape Bonding (TAB)) is used to join the inner leg ( Inner Lead Bonding (ILB), the two chips 30 and 32 are electrically connected to a film carrier 38 (film carrier) with wires by using bumps 34 and 36 respectively; and the part bonded on the outer feet (Outer Lead Bonding, OLB) ), The shell [] is connected to a lead frame 40 ('lead frame'), and a solder ball 42 is also arranged between the two chips 30, 32, so that the two chips 30, 32 are connected to each other. The two wafers 30, 32 together with the film carrier 38 and a part of the lead frame 40 are covered with a resin 44 by a mold. It is known that the disadvantage of this multi-chip type package is that the packaging method using automatic film bonding also needs to be connected to the circuit board through a lead frame or other carrier. The signal transmission path is also increased; in addition, because the connection between the chips is carried through the film Therefore, the pad configuration on the wafer still uses the line layout or peripheral layout. For semiconductor chips with a local concentration in the future, the I / O nodes Increasing this configuration will not be enough, and will not increase the enthusiasm of the package. Therefore, one object of the present invention is to provide a face-to-face multi-chip package, which can package multiple chips on the same carrier. Another object of the present invention is to provide a face-to-face type multi-chip package, which shortens the signal transmission path between chips and improves the efficiency of the chip. It is still another object of the present invention to provide a face-to-face multi-chip * inch package, in which the wafers are arranged face-to-face to reduce the area and volume of the package. Another object of the present invention is to provide a face-to-face multi-chip package junction 5 _ wood paper recognition scale 垅; 11 valve solid home 摞 嗲 ((, NS) Λ4 said (2 彳 0X297 male foot) (Notes for filling in this page)

-1T -線 A7 B7 4〇35tw f.doc/008 五、發明説明（) 構’其中晶片之金屬墊採面陣列式配置，以提高整體封裝 之積集度。 本發明還有一目的在於提供一種面對面型多晶片封 裝’利用裸露部份晶片背面，以提高其散熱效能。 爲達成本發明之上述和其他目的，本發明提出一種面 對面型多晶片封裝係採用覆晶技術，將多個晶片彼此面對 面配置，並利用凸塊使其彼此電性連接，同時將多個晶片 封裝在同一承載器上。 訂 此外，依照本發明之一較佳實施例，本發明之面對面 型多晶片封裝在封裝時可利用異方性導電膠塡入晶片之 間’以改善晶片間之電性連接。而由於採用覆晶技術’晶 片上金屬墊之配置可採用面陣列方式，以提高封裝積集 度，並且在封裝灌膠時可使部份晶片背面裸露，或配置一 散熱片以提高其散熱效果。 線 再則，本發明之面對面型多晶片封裝結構，其承載器 可以是導線架、軟片型承載器、印刷電路板，玻璃等；且 可應用於各種類型之封裝，包括：錫球格狀陣列封裝 (BGA)、電路板上晶片封裝(c〇B)、玻璃上晶片封裝(COG>， 多晶片型晶片尺寸封裝（MCCSP)等。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖所繪示爲一種習知多晶片型封裝。 第2圖所繪示爲習知面對面多晶片型封裝的剖面示意 6 本紙沐尺度这川中國囤家標?1* ( (’NS )以現格（210X 297公势} 449894 4035twf.doc/008 A7 B7 五、發明説明（i ) 圖。 第3A、3B圖所繪示爲依照本發明之第一較佳實施例 一種面對面型多晶片封裝之剖面示意圖。 第3C、3D圖所繪示爲依照本發明之第一較佳實施例 一種具有散熱設計之面對面型多晶片封裝剖面示意圖。 第4A圖所繪示爲依照本發明之第二較佳實施例，-種面對面型多晶片封裝之剖面示意圖。 第4B、4C圖所繪示爲依照本發明之第二較佳實施例 一種具有散熱設計之面對面型多晶片封裝剖面示意圖。 第5A、5B圖所繪示爲依照本發明之第二較佳實施例 一種面對面型多晶片封裝之剖面示意圖。 第5C、5D圖所繪示爲依照本發明之第一較佳實施例 一種具有散熱設計之面對面型多晶片封裝剖面示意圖。 圖示標號說明： 10 :基材 12 ' 30 ' 32 ' 58 14 :絕緣膠 18 ' 44 :樹脂 34、36 :凸塊 40 :導線架 5〇 :晶片座 54、84 :外導腳部份 68 :金屬墊 58a ' 60a ' 62a ' 64a 60、62、64、66 :晶片 16、94 :導線 20 :錫球 38 :軟片承載器 42 :錫球 52、82 :內導腳部份 56、86 :導腳 70 :凸塊 66a:具有金屬墊之表面 (劫先閱讀背而之注意事項再读寫本頁) 本紙张尺度邊州中國國家標埤（（'NS > Λ4規柏（210X297公釐） 44989 4-1T -line A7 B7 40355tw f.doc / 008 V. Description of the invention () Structure ′ The metal pads of the wafer are arranged in an array arrangement to improve the integration of the overall package. Another object of the present invention is to provide a face-to-face type multi-chip package ', which utilizes the exposed part of the back of the chip to improve its heat dissipation performance. In order to achieve the above and other objectives of the present invention, the present invention proposes a face-to-face type multi-chip package which uses flip-chip technology to arrange a plurality of wafers face to face with each other, and uses bumps to electrically connect each other, and simultaneously packages a plurality of wafers. On the same carrier. In addition, according to a preferred embodiment of the present invention, the face-to-face type multi-chip package of the present invention can use an anisotropic conductive adhesive to be inserted between the chips' during packaging to improve the electrical connection between the chips. Due to the use of flip-chip technology, the configuration of the metal pads on the wafer can adopt the surface array method to improve the package accumulation, and the back of some chips can be exposed when the package is filled, or a heat sink can be provided to improve its heat dissipation effect. . In addition, the carrier of the face-to-face multi-chip package structure of the present invention can be a lead frame, a flexible carrier, a printed circuit board, glass, etc .; and can be applied to various types of packages, including: solder ball grid arrays Package (BGA), chip-on-board package (COB), chip-on-glass package (COG), multi-chip-type chip size package (MCCSP), etc. In order to enable the above and other objects, features, and advantages of the present invention It is more obvious and easy to understand. The preferred embodiment will be described in detail below with the accompanying drawings, which will be described in detail as follows: Brief description of the drawings: Figure 1 shows a conventional multi-chip package. Figure 2 shows Shown as a cross-section of a conventional face-to-face multi-chip package. 6 Paper size, which is the standard of the Chinese storehouse? 1 * (('NS) to the present (210X 297 public power) 449894 4035twf.doc / 008 A7 B7 V. Invention Explanation (i) Figures. Figures 3A and 3B are schematic cross-sectional views of a face-to-face multi-chip package according to the first preferred embodiment of the present invention. Figures 3C and 3D are shown as the first according to the present invention. A preferred embodiment has a heat dissipation design Cross-sectional schematic diagram of a face-to-face type multi-chip package. Fig. 4A illustrates a cross-sectional schematic diagram of a face-to-face type multi-chip package according to the second preferred embodiment of the present invention. Figs. 4B and 4C illustrate the multi-chip package according to the present invention. The second preferred embodiment is a schematic cross-sectional view of a face-to-face type multi-chip package with a heat dissipation design. Figures 5A and 5B are schematic cross-sectional views of a face-to-face type multi-chip package according to a second preferred embodiment of the present invention. Section 5C 5D is a schematic cross-sectional view of a face-to-face multi-chip package with a heat-dissipating design according to the first preferred embodiment of the present invention. The symbol description: 10: substrate 12 '30' 32 '58 14: insulation glue 18 '44: Resin 34, 36: Bump 40: Lead frame 50: Wafer holder 54, 84: Outer guide pin portion 68: Metal pad 58a' 60a '62a' 64a 60, 62, 64, 66: Wafer 16 , 94: Conductor 20: Tin ball 38: Foil carrier 42: Tin ball 52, 82: Inner guide pin part 56, 86: Guide pin 70: Bump 66a: Surface with metal pad (read first and read later) (Please read and write this page again) (( 'NS > Λ4 Regulation Bo (210X297 mm) 449 894

4 03 5 lw f. d o c/OOS A7 B7 66b :晶片背面 74 :塡充材質 80 :可撓性膠片 98 :散熱片 92 :接點 實施例 一般封裝技術可大略分爲幾階段： 1.承載器(Carder)之選擇：依照產品之需求選擇適當 之晶片承載器，比如導線架(Lead Frame)、軟片型承 載器（film carrier)、玻璃或印刷電路板（PCB)等。其 中軟片型承載器大多用於軟片自動接合（Tape Automatic Bonding，TAB)技術。 2·晶片與承載器之電性接合：目前之技術包括打導 線（wire bonding)、軟片自動接合（TAB)及覆晶技術 (flip chip or controlled collapse chip connection, C4)。 rl rr\ k i 屮 it •τ 消 IV 合 ΐί 五、發明说明（“） 58b、60b、62b ' 64b 72 :線型導電材料 76 :絕緣材質 78a 、 78b 、 88a 、 88b 90 :基材 96 :錫球 ("先間讀背面之注意事項再填寫本頁) 3·包裝及成型：將晶片及晶片與承載器接合部份以 樹脂、陶瓷或其他包裝材質覆蓋，以保護元件及接 合部份。 ^ζΜΜΛΜΆ 請參照第3乂、3Β圖，其所繪示爲依照本發明之第一 較佳貫施例，—種面對面型多晶片封裝之剖面示意圖。在 此氧施例中，本發明之面對面型多晶片封裝係採用導線架 本紙ίΜ 度相中國搜家樣冷（（'NS ) Λ4娜（2!0Χ 297公楚） 44989 4 A7 B7 4 03 5 twf d oc/00 8 五、發明説明（q ) 作爲承載器，一般導線架包括：一晶片座50(die pad)及多 個導腳56(lead)，而導腳56又區分爲內導腳部份52及外 導腳部份54。將多個晶片58、60、62、64、66，封裝在 一體積與這些晶片體積總和約略相同的封裝中，其中晶g 58、60、62、64、66比如是動態隨機存取記憶體(DRAM)、 唯讀記憶體(R〇M)、靜態隨機存取記億體（SRAM)、快閃記 憶體（Flash Memory)、邏輯電路晶片（LOGIC)或類比晶片 (ANALOG)等各種積體電路晶片，均可應用於本發明之封 裝中。晶片 58、60、62、64 ' 66 之一表面 58a、60a、62a ' 64a、66a上均具有多個金屬墊68(pad)，而本發明的特徵 之一就是在晶片與晶片之連接方式採用覆晶技術（Flip Chip)，在金屬墊68上配置凸塊70(Bump)，晶片S8、60、 ，-" 線 、64、66彼此面對面（face-to-face)配置，利用凸塊70 作彼此之電性連接。由於採用覆晶技術，因此金屬墊68 可採用面陣列配置（Area Array)，分布在晶片的整個表面 上，適用於未來高積集度、多輸入/輸出接點(I/O Nodes)的 半導體元件。 it i\ .1. yli A V\ 打 印 至於晶片58' 60、62、64、66與導線架電性接合部份， 可以利用習知打導線方式（wire bonding)，以線型導電材料 72，比如金線、鋁線或其他金屬線，將部份金屬墊68與 導腳56之內導腳部份52。當然亦可以採用覆晶技術，利 用凸塊70與內導腳部份52電性連接(如第3B圖所示）。 接著，晶片58、60、62、64、66間會塡入塡充材質74， 比如環氧樹脂（Epoxy)等絕緣材質，或者塡入異方性導電膠 (Anisotropic Conductive Paste, ACP)，以改善凸塊 70 間的 _ _ 本..'氏乐尺度埤川中國囚笑:標冷(('NS )八4規梠（210X297公釐〉 44989 4 4035twf.doc/〇〇8 A7 B7 u4 03 5 lw f. Doc / OOS A7 B7 66b: back of the chip 74: filling material 80: flexible film 98: heat sink 92: contact example The general packaging technology can be roughly divided into several stages: 1. Carrier (Carder) selection: Select the appropriate chip carrier according to the needs of the product, such as lead frame, film carrier, glass or printed circuit board (PCB), etc. Among them, film-type carriers are mostly used for Tape Automatic Bonding (TAB) technology. 2. Electrical connection between the chip and the carrier: current technologies include wire bonding, TAB, and flip chip or controlled collapse chip connection (C4). rl rr \ ki 屮 it • τ elimination IV combined 5. V. Invention Description (") 58b, 60b, 62b '64b 72: Linear conductive material 76: Insulating material 78a, 78b, 88a, 88b 90: Substrate 96: Tin ball (" Read the precautions on the back first and then fill out this page) 3. Packaging and molding: Cover the joints of wafers and wafers with the carrier with resin, ceramic or other packaging materials to protect the components and joints. ^ ζΜΜΛΜΆ Please refer to Figures 3 and 3B, which are shown in accordance with the first preferred embodiment of the present invention, a cross-sectional schematic diagram of a face-to-face type multi-chip package. In this oxygen embodiment, the face-to-face type of the present invention Multi-chip packaging system uses leadframe paper ΜΜ phase Chinese searcher-like cold (('NS) Λ4na (2! 0 × 297 Gongchu) 44989 4 A7 B7 4 03 5 twf d oc / 00 8 V. Description of the invention (q As a carrier, a general lead frame includes: a die pad 50 and a plurality of guide pins 56, and the guide pins 56 are divided into an inner guide pin portion 52 and an outer guide pin portion 54. Multiple wafers 58, 60, 62, 64, 66, packaged in a volume and the sum of the volume of these wafers is approximately In the same package, crystal g 58,60,62,64,66 such as dynamic random access memory (DRAM), read-only memory (ROM), static random access memory (SRAM), Various integrated circuit chips such as flash memory, logic circuit chip (LOGIC) or analog chip (ANALOG) can be used in the package of the present invention. One of the chips 58, 60, 62, 64 '66 The surfaces 58a, 60a, 62a '64a, 66a each have a plurality of metal pads 68 (pads), and one of the features of the present invention is the use of flip chip technology in the wafer-to-wafer connection method. A bump 70 (Bump) is arranged on the top, and the chips S8, 60, and-" lines, 64, 66 are arranged face-to-face with each other, and the bumps 70 are used for electrical connection with each other. Due to the use of flip-chip technology Therefore, the metal pad 68 can adopt an area array configuration and is distributed on the entire surface of the wafer, which is suitable for future semiconductor elements with high accumulation and multiple input / output nodes (I / O Nodes). It i \ .1. Yli AV \ Printed on the 58 '60, 62, 64, 66 of the chip and the electrical connection of the lead frame, you can Conventional manner with a play wires (wire bonding), to 72, such as gold, aluminum or other metal wire linear conductive material, the inner portion of the metal pad 68 and the leads 56 of the guide pin part 52. Of course, a flip-chip technology can also be used, and the bump 70 is electrically connected to the inner guide pin portion 52 (as shown in FIG. 3B). Next, the wafers 58, 60, 62, 64, and 66 will be filled with a filling material 74, such as an insulating material such as epoxy, or anisotropic conductive paste (ACP) to improve _ _ Ben: between the 70 bumps: 氏 's music scale Xichuan Chinese prison laugh: standard cold ((' NS) eight 4 gauge (210X297 mm) 44989 4 4035twf.doc / 〇〇8 A7 B7 u

i\· A 五、發明説明（名） 電性連接效果。§純裝及成型的部{分，則採用絕緣材質 76 ’比如環氧基樹脂（Ep〇xy)，包覆晶片座5〇、晶片58 ' 60、6,2、64、66及內導腳部份52。 f參照第3C、3D圖，其所繪示爲依照本發明之第一 較佳貫施例，一種具有散熱設計之面對面型多晶片封裝剖 面示意圖。針對多晶片封裝的散熱考量，可裸露部份晶片 之背面58b、60b，如第3c圖所示，如此的包裝技巧不但 可以縮減整體封裝厚度’且讓晶片背面裸露將可以提供較 佳的散熱路徑，提高散熱效能。當然，爲提高散熱效果， 亦可以增加散熱片’比如將散熱片78a配置在部份晶片背 面58b、60b、62b，或者將散熱片78b配置在晶片座50背 面，且裸露於絕緣材質76外。 而後續將導腳56折彎成型（f0rrning)的部份，以及導腳 56與電路板間以表面焊接技術（surface M〇Unt Technique, SMT)接合部份’由於與習知技術相同，在此不再贅述。 此外’値得一提的是，本實施例中雖然所採用的導線 架爲具有晶片座之一般型導線架，然而熟習該項技術者應 知’本發明知封裝結構亦可應用於不具晶片座之導線架， 比如晶片上有導腳封裝(Lead On Chip, LOC)或導腳上有晶 片封裝（Chip On Lead, COL)等之導線架，由於其結構與前 述實施例類似，在此不再贅述。 第二較佳實施例 請參照第4A圖，其所繪示爲依照本發明之第二較佳 實施例，一種面對面型多晶片封裝之剖面示意圖。在此實 施例中，本發明之面對面型多晶片封裝係採用軟片型承載 1----- 一___________ 本紙张尺成通川中阈阀家標呤（（'NS ) Λ4規格（210X297公楚 (ΪΑ先閲讀背而之II-意事項再楨寫本页) 訂i \ · A V. Description of the Invention (Name) Electrical connection effect. §Purely assembled and molded parts {Insulation material 76 ', such as epoxy resin (Epoxy), is used to cover the wafer holder 50, wafer 58' 60, 6, 2, 64, 66 and inner guide pins Section 52. f With reference to Figures 3C and 3D, a schematic cross-sectional view of a face-to-face multi-chip package with a heat dissipation design according to the first preferred embodiment of the present invention is shown. For the heat dissipation considerations of multi-chip packages, the backsides 58b and 60b of some chips can be exposed, as shown in Figure 3c. Such packaging techniques can not only reduce the overall package thickness, but also expose the backside of the chip to provide a better heat dissipation path. To improve heat dissipation efficiency. Of course, in order to improve the heat dissipation effect, heat sinks may also be added. For example, the heat sinks 78a are arranged on the back surfaces of the wafers 58b, 60b, 62b, or the heat sinks 78b are arranged on the back surface of the wafer holder 50 and exposed outside the insulating material 76. And then the guide pin 56 is bent and formed (f0rrning), and the joint portion between the guide pin 56 and the circuit board is surface joint technology (SMT), because it is the same as the conventional technology, here No longer. In addition, it is mentioned that although the lead frame used in this embodiment is a general type lead frame with a chip holder, those skilled in the art should know that the package structure of the present invention can also be applied without a chip holder. A lead frame, such as a lead frame on a chip (Lead On Chip, LOC) or a chip package (Chip On Lead, COL), has a structure similar to that of the previous embodiment, and will not be repeated here. To repeat. Second Preferred Embodiment Please refer to FIG. 4A, which is a schematic cross-sectional view of a face-to-face multi-chip package according to a second preferred embodiment of the present invention. In this embodiment, the face-to-face multi-chip package of the present invention adopts a soft-film type to carry 1 -----___________ This paper ruler becomes a standard valve in Tongchuan (('NS) Λ4 specification (210X297) (ΪΑRead the back II-Issue before writing this page) Order

4 4989 44 4989 4

4035(wt.d〇c/〇〇S 五、發明说明（*?)4035 (wt.d〇c / 〇〇S V. Description of the invention (*?)

JST 器作爲承載器’一般軟片型承載器包括一可撓性膠片如 及多個導腳86，而導腳86亦區分爲內導腳部份82及外罇 腳部份' 84。晶片 58、60、62、64、66 之一表面 58a、6〇a、 62a、64a、66a上均具有多個金屬墊68，而本實施例的特 徵之一就是在晶片與晶片之連接方式，以及晶片與軟片邀 承載器間的連接，均採用覆晶技術(FliP chlp) ’在金屬驾 68上配置凸塊70(BumP)，晶片58、60、62、64、66彼牝 面對面（face-to-face)配置，利用凸塊70作彼此之電性趫 接。由於採用覆晶技術’因此金屬墊68可採用面陣列鸵 置（Area Array)，分布在晶片的整個表面上’適用於来來 高積集度、多輸入/輸出接點(I/0 Nodes)的半導體兀件° ί 於晶片58、60、62、64、66與導腳86電性接合部份’亦 採用覆晶技術，利用凸塊70與內導腳部份82電性連接 接著，晶片58、6〇、62、64、66間會塡入塡充材質74 ’ 比如環氧樹脂等絕緣材質，或者塡入異方性導電膠’以改 善凸塊7〇間的電性連接效果。最後包裝及成型的部份， 則採用絕緣材質76，比如環氧基樹脂，包覆晶片58、6〇、 62、64、66及內導腳部份82。 ^3-「屮""'^^G r-''--in肾合 "" 請參照第4Β、4C圖’其所繪示爲依照本發明之第= 較佳實施例’一種具有散熱設計之面對面型多晶片封裝剖 面示意圖°針對多晶片封裝的散熱考量，可裸露部份或全 部晶片之背面5仙、60b、62b、64b、66b，如第4Β圖所 示，如此的包裝技巧不但可以縮減整體封裝厚度，且讓晶 片背面裸露將可以提供較佳的散熱路徑，提高散熱效能。 當然，爲提高散熱效果’亦可以增加散熱片，比如將散熱 家射（rNS) ^麟（210>< 297公能） Γ Λ4989 4 A7 4035lwf.doc/008 B7 五、發明说明（广） 片88a配置在部份晶片背面58b、60b、62b，或者將散熱 片88b配置在晶片背面64b、66b，且裸露於絕緣材質76JST device as a carrier 'A general film-type carrier includes a flexible film such as a plurality of guide pins 86, and the guide pins 86 are also divided into an inner guide leg portion 82 and an outer heel portion '84. One of the surfaces 58a, 60a, 62a, 64a, 66a of the wafers 58, 60, 62, 64, 66 has a plurality of metal pads 68, and one of the features of this embodiment is the connection method between the wafer and the wafer. As well as the connection between the wafer and the film carrier, the chip 70 (BumP) is configured on the metal driver 68, and the chips 58, 60, 62, 64, 66 face each other (face- to-face) configuration, the bumps 70 are used for electrical connection with each other. Due to the use of flip-chip technology, the metal pads 68 can be area arrays distributed on the entire surface of the wafer. It is suitable for high-level accumulation, multiple input / output nodes (I / 0 Nodes). The semiconductor components of the chip are used to electrically connect the chip 58, 60, 62, 64, 66 and the guide pin 86. The chip-on technology is also used, and the bump 70 is electrically connected to the inner guide pin portion 82. Then, the chip The filling materials 74, 58, 60, 62, 64, and 66 will be filled with a filling material 74 ', such as an epoxy resin or an anisotropic conductive adhesive, to improve the electrical connection between the bumps 70. The final packaging and molding part is made of insulating material 76, such as epoxy resin, which covers the chips 58, 60, 62, 64, 66 and inner guide pin part 82. ^ 3-`` 屮 " " '^^ G r -''-- in Shenhe " " Please refer to Figs. 4B and 4C, which are shown as "the preferred embodiment according to the present invention" A cross-sectional schematic diagram of a face-to-face multi-chip package with a heat-dissipation design. For the heat dissipation considerations of a multi-chip package, the back of some or all of the chip can be exposed by 5 cents, 60b, 62b, 64b, 66b, as shown in Figure 4B. Packaging techniques can not only reduce the overall package thickness, but leaving the back of the chip exposed can provide a better heat dissipation path and improve heat dissipation efficiency. Of course, to improve the heat dissipation effect, heat sinks can also be added, such as thermal radiation (rNS) ^ Lin (210 > < 297 public energy) Γ Λ4989 4 A7 4035lwf.doc / 008 B7 V. Description of the invention (Wide) Sheet 88a is arranged on the back of some wafers 58b, 60b, 62b, or heat sink 88b is arranged on the back of wafer 64b , 66b, and exposed to insulating material 76

外。I 而後續將導腳86折彎成型（forming)的部份，以及導腳 %與電路板間以表面焊接技術（Surface Mount Technique, SMT)接合部份，由於與習知技術相同’在此不再贅述。 第三較佳實施Μ 請參照第5Α圖，其所繪示爲依照本發明之第三較佳 實施例，一種面對面型多晶片封裝之剖面示意圖。在此實 施例中，本發明之面對面型多晶片封裝係採用印刷電路板 或玻璃作爲承載器，一般印刷電路板或玻璃承載器包括一 基材90，比如是FR-4、FR-5、ΒΤ或玻璃等’而基材90 表面具有多個接點91 2,甚至包括印刷電路(Print Circuit,未 繪示）。若基材90是直接利用電路基板(mother board) ’亦 即採用電路板上晶片封裝COB，或者爲錫球格狀陣列封裝 (BGA)之基板（substrate)，則基材90係由多層絕緣材質及 印刷電路（銅箔）壓合而成。晶片58、60、62、64、66之一 表面58a、60a、62a、64a、66a上均具有多個金屬墊68， 而晶片與晶片之連接方式，採用覆晶技術(Flip Chip)，在 金屬墊68上配置凸塊70(Bump)，晶片58、60、62、64 ' 66彼此面對面（face-to-face)配置，利用凸塊70作彼此之 電性連接。由於採用覆晶技術，因此金屬墊68可採用面 陣列配置（Area Array)，分布在晶片的整個表面上，適用 於未來高積集度、多輸入/輸出接點（I/O Nodes)的半導體元 件。至於晶片58、60、62 ' 04、66與基材90之接點92 (β先閱讀背而之注意事項再填寫本莨) 訂 1 2 2 呆紙张尺度邊川屮國囹家K (('⑽）Λ4坭梠(TlOx 297^fi ) 4 4989 4 A7 4035twf.doc/〇〇8 B7 五 '發明説明（丨丨） 電性接合部份’則採用打導線方式，利用導線94與接點92 電性連接。接著，晶片58、60、62、64、όό間會塡入塡 充材質74，比如環氧樹脂等絕緣材質’或者塡入異方性導 電膠，以改善凸塊70間的電性連接效果。最後包裝及成 型的部份’則採用絕緣材質76 ’比如環氧基樹脂’包覆部 份基材90及其上之接點92與晶片58、60、02、64、66。 請參照第5Β圖’若基材90爲錫球格狀陣列封裝(BGA)之 基板，則在基材90的另一面(未配置晶片的一面)會配置有 多個錫球96(solder ball) ’以期與電路基板連接，而錫球 96係藉由基材90中之通孔及印刷電路（未繪示)與接點92 連接。 請參照第5C、5D圖，其所繪示爲依照本發明之第三 較佳實施例，一種具有散熱設計之面對面型多晶片封裝剖 面不意圖。針對多晶片封裝的散熱考墓’可裸露部份晶片 之背面58b、60b，如第5C圖所示，如此的包裝技巧不但 可以縮減整體封裝厚度，且讓晶片背面裸露將可以提供較 佳的散熱路徑，提高散熱效能。當然，爲提高散熱效果， 亦可以增加散熱片，比如將散熱片98配置在部份晶片背 面58b、60b，且裸露於絕緣材質76外。 綜上所述，本發明之面對面型多晶片封裝至少具有下 列優點·‘ 1. 本發明之面對面型多晶片封裝，可降低封裝後之面 積及體積，且藉由覆晶技術與金屬墊之面陣列配置’可以 大大提高封裝的積集度。 2. 本發明之面對面型多晶片封裝，直接以凸塊作爲晶outer. I The bending part of the guide pin 86 is subsequently formed, and the joint portion between the guide pin% and the circuit board is connected by Surface Mount Technique (SMT), because it is the same as the conventional technique. More details. Third Preferred Implementation Please refer to FIG. 5A, which is a schematic cross-sectional view of a face-to-face type multi-chip package according to a third preferred embodiment of the present invention. In this embodiment, the face-to-face multi-chip package of the present invention uses a printed circuit board or glass as a carrier. Generally, the printed circuit board or glass carrier includes a substrate 90, such as FR-4, FR-5, BT Or glass, and the surface of the substrate 90 has a plurality of contacts 91 2, and even includes a printed circuit (Print Circuit, not shown). If the substrate 90 is directly using a mother board, that is, a chip package COB on a circuit board, or a substrate of a solder ball grid array package (BGA), the substrate 90 is made of a multilayer insulation material And printed circuit (copper foil) laminated. One of the surfaces 58a, 60a, 62a, 64a, 66a of the wafers 58, 60, 62, 64, 66 has a plurality of metal pads 68, and the connection method between the wafers and the wafers uses Flip Chip technology. Bumps 70 (bumps) are disposed on the pads 68, and the wafers 58, 60, 62, 64 '66 are face-to-face arranged, and the bumps 70 are used for electrical connection with each other. Due to the flip-chip technology, the metal pad 68 can adopt an area array configuration and is distributed on the entire surface of the wafer. It is suitable for future high-concentration semiconductors with multiple input / output nodes (I / O Nodes). element. As for the contacts 92 of the wafers 58, 60, 62 '04, 66 and the substrate 90 (β, please read the back of the note before filling in this note) Order 1 2 2 paper size edge side of the country Kawasaki K ((( '⑽） Λ4 坭 梠 (TlOx 297 ^ fi) 4 4989 4 A7 4035twf.doc / 〇〇8 B7 Five' Explanation of the invention (丨 丨) Electrical connection part 'uses a wire method, using wire 94 and contacts 92 Electrical connection. Then, the chip 58, 60, 62, 64, and 6 will be filled with a filling material 74, such as an insulating material such as epoxy resin, or an anisotropic conductive adhesive, to improve the bonding between the bumps 70. Electrical connection effect. The final packaging and molding part is covered with an insulating material 76 'such as epoxy resin' to cover part of the substrate 90 and its contacts 92 and the chip 58, 60, 02, 64, 66 Please refer to FIG. 5B. If the substrate 90 is a substrate of a solder ball grid array package (BGA), a plurality of solder balls 96 (solder ball 96) will be arranged on the other side of the substrate 90 (the side where the wafer is not arranged). ) 'In order to connect to the circuit substrate, the solder ball 96 is connected to the contact 92 through the through hole in the substrate 90 and the printed circuit (not shown). Please refer to Figures 5C and 5D It is shown that according to the third preferred embodiment of the present invention, a cross-sectional multi-chip package with a heat-dissipating design is not intended to be a cross-section. For the multi-chip package's heat-dissipation test grave, the back surfaces of the chips 58b, 60b can be exposed As shown in Figure 5C, such packaging techniques can not only reduce the overall package thickness, but also expose the back of the chip to provide a better heat dissipation path and improve heat dissipation efficiency. Of course, to improve the heat dissipation effect, you can also add heat sinks, such as The heat sink 98 is arranged on the back surfaces 58b and 60b of some of the chips, and is exposed outside the insulating material 76. In summary, the face-to-face multi-chip package of the present invention has at least the following advantages · '1. Face-to-face multi-chip of the present invention Packaging, which can reduce the area and volume after packaging, and through the flip-chip technology and the surface array configuration of the metal pads, the accumulation degree of the package can be greatly improved. 2. The face-to-face multi-chip package of the present invention directly uses bumps as the package. crystal

Jk张尺度珀;丨1屮國探家椋f ( ('NS ) Λ4規柊（21〇X297公f ) (先聞讀背而之注意事項再填寫本S ) 訂 線 449894 4035iwf.d〇c/008 A7 B7 五、發明説明（（了） 片與晶片間之m性連接’縮短晶片與晶片的訊號傳輸路 徑’提尚整體^裝的效能，並由於凸塊採用藤列配置， 可應用於未來_積輯出接關半導體元件^ 3. 本發明之面對面型多晶片封裝，由於可採用裸晶的 封裝方式，可提咼其散熱效能，亦可藉由散熱片之配置’ 增加其散熱量。Jk Zhang Jiubao; 丨 1 屮 National Detective Family 椋 f (('NS) 44 Regulations (21〇X297 公 f) (first read the back of the precautions and then fill out this S) Line 449894 4035iwf.d〇c / 008 A7 B7 V. Description of the invention (()) The m-type connection between the chip and the chip 'shortens the signal transmission path between the chip and the chip' improves the overall performance of the package, and because the bumps are arranged in a rattan configuration, they can be applied to The future _ builds out related semiconductor components ^ 3. The face-to-face multi-chip package of the present invention can improve its heat dissipation performance due to the bare-chip packaging method, and can also increase its heat dissipation capacity through the configuration of heat sinks .

4. 本發明之面對面型多晶片封裝，其晶片可以爲 DRAM、ROM、SRAM、Flash Memory、LOGIC 或 ANALOG 等各種積體電路晶片’因此本發明之封裝可應用於各種不 同功能或各種頻率之領域’比如可應用於通訊器材、電腦 系統等，甚至作爲阜一系統晶片。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (^先閱讀背'6之注意事項再填寫本页> 訂 Λ ii .1 ;·/ί 印 關家椟埤((，NS ) Λ4規格（210X297公犮）4. The face-to-face multi-chip package of the present invention can be a variety of integrated circuit chips such as DRAM, ROM, SRAM, Flash Memory, LOGIC, or ANALOG. Therefore, the package of the present invention can be applied to various fields with different functions or frequencies. 'For example, it can be applied to communication equipment, computer systems, etc., and even as a Fuyi system chip. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (^ Please read the precautions of the back '6 before filling in this page> Order Λ ii .1; · / IND Seal Guan Jiayi ((, NS) Λ4 Specification (210X297) 犮

Claims (1)

經濟部中央標準局員工消費合作社印裝 ^'4 49 8 9 4 A8 B8 4 03 5i\\ i'.doc/OOii D〇 六、申請專利範圍 1. 一種面對面型多晶片封裝，包括： 一導線架，該導線架至少具有一晶片座及複數個導腳， 且每一該些導腳分別具有一外導腳部份及一內導腳部份； 複數個晶片，配置於該晶片座上，每一該些晶片之一 表面分別具有複數個金屬墊，且該些晶片以具有該些金屬 墊之該表面彼此面對面配置； 複數個凸塊，配置於該些晶片之間的該些金屬墊上， 用以使得該些晶片彼此相互電性連接； 複數個導電材料，連接部份該些金屬墊及該些導腳之 該內導腳部份；以及 一絕緣材質，包覆該晶片座、該些晶片及該些導腳之 該內導腳部份。 2. 如申請專利範圍第1項所述之面對面型多晶片封 裝，其中該些晶片間更塡充一環氧樹脂。 3. 如申請專利範圍第1項所述之面對面型多晶片封 裝，其中該些晶片間更塡充一異方性導電膠。 4. 如申請專利範圍第1項所述之面對面型多晶片封 裝，其中該些導電材料包括金屬線。_ 5. 如申請專利範圍第1項所述之面對面型多晶片封 裝，其中該些導電材料包括凸塊。 6. 如申請專利範圍第1項所述之面對面型多晶片封 裝，其中該絕緣材質包括環氧樹脂。 7. 如申請專利範圍第1項所述之面對面型多晶片封 裝1其中該些金屬墊在些晶片上採用面陣列式配置。 8. 如申請專利範圍第1項所述之面對面型多晶片封 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部尹央標準局員工消費合作社印製 4 4989 4 as B8 403 5 Uvfdt1c/008_^_ 六、申請專利範圍 裝，其中該絕緣材質暴露出部份該些晶片之另一表面。 9. 如申請專利範圍第1項所述之面對面型多晶片封 裝，其中該面對面型多晶片封裝更包括一散熱片配置於該 晶片座，並裸露於該絕緣材質之外。 10. 如申請專利範圍第1項所述之面對面型多晶片封 裝，其中該面對面型多晶片封裝更包括一散熱片配置於部 份該些晶片之另一表面，並裸露於該絕緣材質之外。 Π.—種面對面型多晶片封裝，包括： 一基材，該基材之一表面上至少具有複數個接點； 複數個晶片，配置於該基材具有該些接點之該表面上， 每一該些晶片之一表面分別具有複數個金屬墊，且該些晶 片以具有該些金屬墊之該表面彼此面對面配置； 複數個凸塊，配置於該些晶片之間的該些金屬墊上， 用以使得該些晶片彼此相互電性連接； 複數個導線，連接部份該些金屬墊及該些線路；以及 一絕緣材質，包覆部份該基材及該些晶片。 12. 如申請專利範圍第11項所述之面對面型多晶片封 裝，其中該基材包括印刷電路板。 13. 如申請專利範圍第11項所述之面對面型多晶片封 裝，其中該基材包括錫球格狀陣列封裝基材。 14. 如申請專利範圍第11項所述之面對面型多晶片封 裝，其中該基材包括玻璃。 15. 如申請專利範圍第11項所述之面對面型多晶片封 裝，其中該些晶片間更塡充一環氧樹脂 16. 如申請專利範圍第11項所述之面對面型多晶片封 (請先閱讀背面之注意事項再填寫本頁) 訂 梦！ 本紙張尺度逋用中國國家榡準（CNS > A4规格（210X297公釐） 經濟部中央標準局貝工消費合作社印製 44989 ^ 会88 4〇35tWi'd〇C/〇〇S_D8_ 六、申請專利範圍 裝，其中該些晶片間更塡充一異方性導電膠。 Π.如申請專利範圍第11項所述之面對面形多晶片封 裝，其中該絕緣材質包括環氧樹脂。 18. 如申請專利範圍第11項所述之面對面形多晶片封 裝，其中該絕緣材質包覆部份該基材及該些晶片，且暴露 出部份該些晶片之另一表面。 19. 如申請專利範圍第11項所述之面對面型多晶片封 裝，其中該些金屬墊在些晶片上採用面陣列式配置。 20. 如申請專利範圍第11項所述之面對面型多晶片封 裝，其中該面對面型多晶片封裝更包括一散熱片配置於部 份該些晶片之另一表面，並裸露於該絕緣材質之外。 21. —種面對面型多晶片封裝，包括： 一承載器，該承載器至少複數個導腳，且每一該些導 腳分別具有一外導腳部份及一內導腳部份； 複數個晶片，每一該些晶片之一表面分別具有複數個 金屬墊，且該些晶片以具有該些金屬墊之該表面彼此面對 面配置； 複數個第一凸塊，配置於該些晶片之間的該些金屬墊 上，用以使得該些晶片彼此相互電性連接； 複數個第二凸塊，連接部份該些金屬墊及該些導腳之 該內導腳部份；以及 一絕緣材質，包覆該些晶片及該些導腳之該內導腳部 份。 22. 如申請專利範圍第21項所述之面對面型多晶片封 裝，其中該承載器包括導線架。 (請先閣讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 449894 4 03 5twt'.doc/008 ABCD 六、申請專利範圍 23. 如申請專利範圍第21項所述之面對面型多晶片封 裝，其中該承載器包括軟片型承載器。 24. 如申請專利範圍第21項所述之面對面型多晶片封 裝，其中該些晶片間更塡充一環氧樹脂。 25. 如申請專利範圍第21項所述之面對面型多晶片封 裝，其中該些晶片間更塡充一異方性導電膠。 26. 如申請專利範圍第21項所述之面對面型多晶片封 裝，其中該絕緣材質包括環氧樹脂。 27. 如申請專利範圍第21項所述之面對面型多晶片封 裝，其中該些金屬墊在些晶片上採用面陣列式配置。 28. 如申請專利範圍第21項所述之面對面型多晶片封 裝，其中該絕緣材質暴露出部份該些晶片之另一表面。 29. 如申請專利範圍第21項所述之面對面型多晶片封 裝，其中該面對面型多晶片封裝更包括一散熱片配置於部 份該些晶片之另一表面，並裸露於該絕緣材質之外。 (請先聞讀背面之注意事項再填寫本页) 訂 經濟部中央樣準局員工消費合作社印裝 本紙張尺度逋用中國國家樣率（CNS ) A4規格（210X297公嫠）Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs ^ '4 49 8 9 4 A8 B8 4 03 5i \\ i'.doc / OOii D〇6. Patent application scope 1. A face-to-face multi-chip package, including: a wire Frame, the lead frame has at least a wafer base and a plurality of guide pins, and each of these guide pins has an outer guide pin portion and an inner guide pin portion; a plurality of wafers are arranged on the wafer base, Each of the wafers has a plurality of metal pads on a surface thereof, and the wafers are arranged facing each other with the surface having the metal pads; a plurality of bumps are disposed on the metal pads between the wafers, For electrically connecting the wafers to each other; a plurality of conductive materials, connecting the metal pads and the inner guide pin portions of the guide pins; and an insulating material covering the wafer holder, the The chip and the inner guide pin portions of the guide pins. 2. The face-to-face multi-chip package described in item 1 of the scope of patent application, wherein the wafers are filled with an epoxy resin. 3. The face-to-face multi-chip package as described in item 1 of the scope of patent application, wherein the wafers are further filled with an anisotropic conductive adhesive. 4. The face-to-face multi-chip package as described in item 1 of the patent application scope, wherein the conductive materials include metal wires. _ 5. The face-to-face multi-chip package described in item 1 of the patent application scope, wherein the conductive materials include bumps. 6. The face-to-face multi-chip package as described in item 1 of the patent application scope, wherein the insulating material includes epoxy resin. 7. The face-to-face multi-chip package 1 described in item 1 of the scope of the patent application, wherein the metal pads are arranged in a surface array on the wafers. 8. Face-to-face multi-chip package as described in item 1 of the scope of patent application (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) Ministry of Economic Affairs Yin Printed by the Consumer Standards Cooperative of the Central Bureau of Standards 4 4989 4 as B8 403 5 Uvfdt1c / 008 _ ^ _ VI. Application for a patent package, in which the insulating material exposes part of the other surface of the chips. 9. The face-to-face multi-chip package according to item 1 of the patent application scope, wherein the face-to-face multi-chip package further includes a heat sink disposed on the chip holder and exposed outside the insulating material. 10. The face-to-face multi-chip package according to item 1 of the patent application scope, wherein the face-to-face multi-chip package further includes a heat sink disposed on the other surface of some of the chips and exposed outside the insulating material . Π. A face-to-face multi-chip package, comprising: a substrate having at least a plurality of contacts on one surface of the substrate; a plurality of wafers disposed on the surface of the substrate having the contacts, each One surface of each of the wafers has a plurality of metal pads, and the wafers are arranged facing each other with the surface having the metal pads. A plurality of bumps are disposed on the metal pads between the wafers. So that the chips are electrically connected to each other; a plurality of wires connecting a part of the metal pads and the circuits; and an insulating material covering a part of the substrate and the chips. 12. The face-to-face multi-chip package as described in item 11 of the patent application scope, wherein the substrate comprises a printed circuit board. 13. The face-to-face multi-chip package as described in item 11 of the patent application scope, wherein the substrate comprises a solder ball grid array packaging substrate. 14. The face-to-face multi-chip package as described in item 11 of the patent application scope, wherein the substrate comprises glass. 15. The face-to-face multi-chip package as described in item 11 of the scope of patent application, wherein an epoxy resin is filled between the wafers. 16. The face-to-face multi-chip package as described in item 11 of the scope of patent application (please first Read the notes on the back and fill out this page) This paper is in Chinese National Standard (CNS > A4 size (210X297mm). Printed by Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs, 44989 ^ Meeting 88 4〇35tWi'd〇C / 〇〇S_D8_ VI. Patent Application Range mounting, in which the wafers are filled with an anisotropic conductive adhesive. Π. The face-to-face multi-chip package described in item 11 of the patent application scope, wherein the insulating material includes epoxy resin. 18. If applying for a patent The face-to-face multi-chip package described in item 11 of the scope, wherein the insulating material covers a part of the substrate and the wafers, and exposes another surface of some of the wafers. The face-to-face multi-chip package described in item 1, wherein the metal pads are arranged in an array on the wafers. 20. The face-to-face multi-chip package described in item 11 of the patent application scope, wherein the face-to-face multi-chip package It also includes a heat sink disposed on the other surface of some of the chips and exposed outside the insulating material. 21. A face-to-face multi-chip package including: a carrier, the carrier being at least plural Guide pins, each of which has an outer guide pin portion and an inner guide pin portion; a plurality of wafers, a surface of each of the wafers has a plurality of metal pads, and the wafers are The surfaces with the metal pads are arranged face to face with each other; a plurality of first bumps are disposed on the metal pads between the wafers, so that the wafers are electrically connected to each other; a plurality of second bumps , The inner pad portion of the metal pads and the guide pins of the connecting portion; and an insulating material covering the inner pad portion of the chips and the guide pins. The face-to-face multi-chip package described in item 21, wherein the carrier includes a lead frame. (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) ) 449894 4 03 5twt'.doc / 008 ABCD 6. Application scope of patent 23. Face-to-face type multi-chip package as described in item 21 of the scope of application for patent, where the carrier includes a film carrier. 24. If the scope of patent application Item 21 The face-to-face multi-chip package described above, wherein the wafers are further filled with an epoxy resin. 25. The face-to-face multi-chip package described in item 21 of the patent application scope, wherein the wafers are further filled with an alien 26. The face-to-face multi-chip package described in item 21 of the patent application, wherein the insulating material includes epoxy resin. 27. The face-to-face multi-chip package described in item 21 of the patent application, wherein The metal pads are arranged in an array on the wafers. 28. The face-to-face multi-chip package described in item 21 of the patent application scope, wherein the insulating material exposes part of the other surface of the wafers. 29. The face-to-face multi-chip package as described in item 21 of the scope of patent application, wherein the face-to-face multi-chip package further includes a heat sink disposed on the other surface of some of the chips and exposed outside the insulating material . (Please read the precautions on the back before filling out this page) Order Printed by the Consumer Cooperatives of the Central Bureau of Procurement, Ministry of Economic Affairs This paper uses the China National Sample Rate (CNS) A4 (210X297)
TW088100113A 1999-01-06 1999-01-06 Face-to-face multi-chip package TW449894B (en)

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US8119446B2 (en) 2001-12-31 2012-02-21 Megica Corporation Integrated chip package structure using metal substrate and method of manufacturing the same
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8119446B2 (en) 2001-12-31 2012-02-21 Megica Corporation Integrated chip package structure using metal substrate and method of manufacturing the same
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US8835221B2 (en) 2001-12-31 2014-09-16 Qualcomm Incorporated Integrated chip package structure using ceramic substrate and method of manufacturing the same
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
US9136246B2 (en) 2001-12-31 2015-09-15 Qualcomm Incorporated Integrated chip package structure using silicon substrate and method of manufacturing the same
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers

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