TW587319B - Ball grid array semiconductor packaging with heat sink channel - Google Patents

Ball grid array semiconductor packaging with heat sink channel Download PDF

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Publication number
TW587319B
TW587319B TW090109240A TW90109240A TW587319B TW 587319 B TW587319 B TW 587319B TW 090109240 A TW090109240 A TW 090109240A TW 90109240 A TW90109240 A TW 90109240A TW 587319 B TW587319 B TW 587319B
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor package
packaging
patent application
scope
Prior art date
Application number
TW090109240A
Other languages
Chinese (zh)
Inventor
Ying-Jie Chen
Tz-Yi Tian
Jeng-Yuan Lai
Jian-Ping Huang
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW090109240A priority Critical patent/TW587319B/en
Application granted granted Critical
Publication of TW587319B publication Critical patent/TW587319B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The present invention provides a ball grid array (BGA) semiconductor packaging with heat sink channel penetrating through the package structure, which includes a substrate for adhering at least one semiconductor chip thereon, and the semiconductor chip is electrically coupled with the substrate, so as to be connected with the external device through the solder balls welded on the substrate; configuring multiple grounding openings on the substrate surface outside the semiconductor chip; conducting mold pressing with the packaging mold having a plurality of tapers to form a plurality of taper longitudinal channels connected with the grounding openings of the substrate on the packaging after completing the packaging process; and, the crossed area of the longitudinal channel is expanded and enlarged from the narrow portion of the grounded openings of the substrate toward the top of packaging encapsulation, so that the air flow rate is inversely proportional to the crossed area of the channel, and the air is accelerated through the grounded openings with smaller cross section area, and rapidly carries out the thermal energy from the substrate surface for achieving the effect of natural chip cooling.

Description

JO / J丄y 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明（1 ) 【發明領域】： 本發明係關於一種I * 、 干等體封褒件，尤指一種具有錐 狀散熱通道俾以調節散敎 ，即散熱逮率之半導體封裝件。【發明背景】： 半導體封裝件種類繁多，其中以球概陣列（謹Gnd Array)半導體裝置因具有高密度輸入/輸出端（1/〇 C0nnectlGn)而成為現今之封裝主流。由於m是種腸 半導體封裝件内之半導體晶片可具有較高密度之電子電路 (EleCtronic Circuits )及電子元件（Eiectr〇nic Components)，故在運作時會產生較多之熱量如無法即 時有效逸散將嚴重損及半導體晶片之壽命；然而因包覆晶 片之封裝膠體為導熱性不良之樹脂材質所形成，所以散熱 效率往往不佳而影響到半導體晶片之性能。 為提高BGA半導體封裝件之散熱效率，遂有於bgA 半導體裝置内加設散熱片，抑或以冷卻空氣或液體（c〇〇led Air 〇r Liquid)通過半導體裝置表面等方式為之。第1圖 所示之結構，乃在一黏接有半導體晶片U之基板1〇上， 藉以如銀膠之熱固性膠黏劑104黏接一散熱件19,並以 封裝樹脂（未圖示）所形成之封裝膠體13包覆該半導體 晶片11及散熱件19。封裝結構内增置散熱件19將明顯 使得封裝件的整體重量增加，同時限制封裝件之尺寸大 小’並且添設散熱件亦會使封裝成本提高，故而開發以加 強空氣對流方式形成自然冷卻之封裝裝置，俾以奸解半導 體晶片周圍之熱積存問題。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1 16253 請 先 閱 讀 背 面 之 注 意 事 項 % 本 頁 裝 訂 587319JO / J 丄 y Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (1) [Field of Invention]: The present invention relates to an I *, stem, etc. body seal, especially a cone-shaped heat dissipation channel. The semiconductor package is used to adjust the dispersion, that is, the heat dissipation rate. [Background of the Invention]: There are many types of semiconductor packages. Among them, Gnd Array semiconductor devices have become the mainstream of packaging today because of their high-density input / output terminals (1/0 C0nnectlGn). Since m is a semiconductor chip in the intestinal semiconductor package, it can have higher-density electronic circuits (EleCtronic Circuits) and electronic components (Eiectronic components), so it will generate more heat during operation. It will seriously damage the life of the semiconductor wafer; however, because the encapsulation gel covering the wafer is formed of a resin material with poor thermal conductivity, the heat dissipation efficiency is often poor and affects the performance of the semiconductor wafer. In order to improve the heat dissipation efficiency of the BGA semiconductor package, a heat sink is added in the bgA semiconductor device, or cooling air or liquid (c00led Air 0r Liquid) is passed through the surface of the semiconductor device. The structure shown in FIG. 1 is a substrate 10 bonded to a semiconductor wafer U, and a heat sink 19 is bonded by a thermosetting adhesive 104 such as silver glue, and is sealed by a sealing resin (not shown). The formed encapsulant 13 covers the semiconductor wafer 11 and the heat sink 19. The addition of a heat sink 19 in the package structure will obviously increase the overall weight of the package, and at the same time limit the size of the package, and the addition of heat sinks will also increase the cost of the package. Therefore, it is developed to strengthen the air convection to form a naturally cooled package. The device solves the problem of heat accumulation around the semiconductor wafer. The size of this paper is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 1 16253 Please read the notes on the back first% Binding on this page 587319

五、發明說明（2 ) 經濟部智慧財產局員工消費合作社印製 曰本專利特開平第8-70082號案係揭露一種踢片載具 式半導體封裝件（Tape Carrier Package )，如第2 A圖（上 視圖）及第2B圖（透視剖面圖）所示，此種封裝結構乃 以複數條繫條105 ( Tie Bar)固接一晶片座101俾以安置 所封裝之半導體晶片11，該晶片座101外圍環設一 Tcp 導腳群102俾供該晶片11與眾多内導腳103( Inner Leads) 導電連結，該項技術之特點係於該等繫條105上建構多個 樹脂材質具縱貫通道1 8之架體1 5 ( Hole Frame Body )， 該等架體15設置之原理係依據白努力定律（Bern〇uUi，s Equation ):P+l/2mv2 = k(P 表示壓力，m 表示質量， v表示速度，k表示常數），則壓力差（a P)會形成速度 場，又根據理想氣體理論中壓力（P)係與溫度（T)呈 正比’因此半導體晶片11運轉產生的熱能會提高晶片周 圍溫度，進而使壓力增加，俾以形成一熱空氣上升，冷空 氣回補之熱對流速度場，達到自然冷卻晶片的效果。惟該 項技術包含之該等架體15係額外黏設於封裝結構1内， 使得封裝成本增加，同時，為維持該等架體15縱貫通道 之暢通俾確保封裝件之散熱功能，須於模壓製程完成 後重複實施去渣作業，致使使封裝時程延長並且增加製程 步驟的繁瑣性。 【發明概述】： 本發明之主要目的即在提供一種具有複數條縱貫封 裝結構的錐形散熱通道之半導體封裝件，其中，該等散熱 通道係自基板之接地開孔（Ground Opening )向上逐漸外 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 2 16253 (請先閱讀背面之注意事項&lt; 裝— ht本頁) 訂·· •線· A7 B7 五、發明說明（ 擴至封裝膠體頂部，寰以扭q^ ^ 異M ^昇基板表面之熱對流速度，俾 利加速逸散半導艚Θ y ^ + 干等骽日日片運作時產生的熱能。 本發明之另一 φΐη --------------裝--- (請先閱讀背面之注意事項β寫本頁) 的為提供一種得以配合半導體 =運作時產熱量多寡自動調節散熱速率，俾以自然冷卻 !體晶片而無須額外增添任何散熱結構，兼具節省成本 及環保概念之半導體封裝件。 本發月之再目的係提供一種無須額外增設其他部 件’僅須略為調整封裝模具並配合適用基板即可實施極 具製程便利性之半導體封裝件。 線· 鑒於上述及其他目的，本發明所提供之具有縱貫散 熱通道的半導體封裝件，係包括：一半導體晶片；一基板， 該基板中央預設有一提供該半導體晶片黏置之晶片接置 區，且於該晶片接置區外之適當位置上開設有複數個接地 開孔，並且，在該基板表面佈設多條自該晶片接置區向外 延伸而連接至該等接地開孔之銅跡線；多條用以導電連結 該aa片與基板之金線’·提供該半導體封裝件與外部裝置電 性連接之多數銲球；以及一用以包覆半導體晶片並於成型 經濟部智慧財產局員工消費合作社印製 後形成多條窄口部連接該接地開孔的錐狀縱貫通道之封裝 膠體。 本發明半導體封裝件之特點係於該基板之接地開孔 上方形成有多數個連通該接地開孔並逐漸朝上外擴而開口 於封裝膠體頂面之外露縱貫通道，該貫穿通道係呈一上寬 下窄之喇A狀型態，其通道截面積自連接基板表面接地通 孔之窄部逐部擴大至封裝膠體頂面。根據理想氣體觀點， 16253 587319 A7 -------B7__________ 五、發明說明（4 ) 壓力（P)與溫度（τ)係呈正比，因而半導體晶片運作 產生熱能使得晶片周圍溫度增加時，壓力亦隨之提昇；另 據白努力方程式（Bernoulli’s Equation) : P + 1/2 mv2 = k (其中P為壓力，m表示質量，k為常數），當空氣流經 該貫穿通道時，壓力差（△!&gt;)形成速度場，然壓力（p) 本身又與截面積（A)呈反比，因而在空氣總流量不變的 狀態下’縱貫通道内的空氣流動速度係與貫穿通道之截面 積成一反比關係。遂而當空氣流經具有較小截面積之接地 開孔時流速較快，俾使基板表面的熱量得以快速藉由空氣 攜離，達到自然冷卻晶片的效果；同時，隨著半導體晶片 作功量增大，晶片周圍溫度升高導致熱對流速率提昇，加 快空氣通過基板通道之速率致使散熱效率增加以形成得依 半導體晶片產生熱量多寡自動調節散熱速率之封裝裝置。 【圖式簡單說明】： 以下茲以較佳具體例配合附圖進一步詳細說明本發 明之特點與功效： 第1圖係為習知具散熱件之半導體封裝件之剖面示 trgi · 圃 ， 第2A圖及第2B圖係為曰本專利特開平第8_70082 號之半導體封裝件之上視圖及透視剖視圖； 第3圖係為本發明第一實施例之半導體封裝件之剖 面示意圖； 第4圖係為本發明半導體封裝件之上視透視圖； 第5圖係為本發明半導體封裝件實施模壓製程之剖 I-------------- I I (請先閱讀背面之注意事項β寫本頁) 訂_ · --線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 4 16253 587319 B7 五、發明說明（5 ) 面示意圖； 第6圖係為用以製作本發明半導體封裝件之模壓模 /、 ’上模模具局部立體放大圖； 、 • 1111 —II---裝--- (請先閱讀背面之注意事項寫本頁) 第7圖係為本發明半導體封裝件内該貫通道結構之 4面不意圖；以及， 第8圖係為本發明第二實施存 X苑例之+導體封裝件内該 貫通道結構之剖面示意圖。 【發明詳細說明】： 農一實施例： 如第3圖所示者為本發明第一實施例之半導體封裝 件之剖視圖。 該第一實施例之半導體封裝件係包括有一基板2〇, 黏置於該基板20上之半導體晶片21，藉以導電連結該基 板20與晶片21之多數金線22，俾供該半導體封裝件2 與外部裝置電性連結之多數銲球24，以及用以包覆該半 導體晶片21及多數金線22之封裝膠體23。 經濟部智慧財產局員工消費合作社印製 該基板 20 係具有一如 BT(Bismaleimide Triazine) 樹脂、環氧樹脂、聚亞醯胺樹脂、三氮雜苯樹脂等材料製 成之芯層200 ( Core)，該芯層200上表面200a之中央處 預先定義出一晶片接置區201，且於該晶片接置區201外 圍佈設有多數之第一導電跡線（未圖示），相對地，該芯 層200下表面200b亦佈設有多條第二導電跡線（未圖示）， 並藉由開設於該芯層200中之貫穿孔（Vias )(未圖示） 導電連結該第一導電跡線與第二導電跡線（均未圖示）； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） 5 16253 587319 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（6 ) 為保護該第一導電跡線與第二導電跡線得與外界隔離，於 該芯層200之上、下表面2〇〇a，200b上分別塗覆有用以覆 蓋該第一導電跡線（未圖示）之上拒銲劑層250 ( Solder Mask )及用以覆蓋該第二導電跡線（未圖示）之下拒銲 劑層251，但使該第一導電跡線（未圖示）終端之鲜墊（未 圖示）及第二導電跡線（未圖示）終端之銲塾202分別外 露出該上拒銲劑層2 5 0與下拒銲劑層2 51上形成之開口 t。 該基板20位於該晶片接置區201外的適當位置上藉 由習知之鑽洞技術（drill)開設有複數個貫穿基板20且 截面積為A之接地開孔26 ( Ground Opening )，第4圖係 為本發明半導體封裝件之上視透視圖，如圖所示，自該芯 層上表面（未圖示）之晶片接置區201向外延伸形成多條 連接該接地開孔之銅跡線203 ( Copper Trace )俾以增強 該接地開孔26對於半導體晶片21之溫度感應。 如第3圖所示，該半導體晶片21係以習用之銀膠或 聚亞醯胺膠片（Polyimide Tape)等膠黏劑204黏接至該 基板200晶片接置區201上，兩者黏接完成後，即以金線 22導電連接該半導體晶片21與該等導電跡線終端之銲墊 (未圖示），俾使該半導體晶片21導電地連接至該基板 20，隨即進行膠體封裝。 參閲第5圖，將該半導體裝置2先置入一封裝用模 具27中進行模壓（Molding)，而形成一用以包覆該半導 體晶片21及眾金線22之封裝膠體23。該模具27具有一 裝--- (請先閱讀背面之注意事項寫本頁) . —線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 6 16253 ^/319 A7 五、發明說明（7 ) 上模270及一得盥綠u财μ ，、以上模270合模之下模271所構成，如 第5圖及第6圖（兮®及&amp;… μ圖係為上模之局部立體放大圖）所示， 該上模270模穴内對應於該基板20接地開孔26之上方， 形成有複數個與上模27〇開槽形成塊m 一體成型之錐體 273，該錐體273目士 ^ 具有一頂部274及一底部275，且該底 邛275之截面積係顯著地大於該頂部274截面積；合模後， 該錐體273頂部274係銜接至基板20接地開孔26上，並 藉由錐體273底部275與該上模270之開槽形成塊272相 連’俾使脫模後之封裝件具有多個縱剖面形似喇^狀具有 寬口部281及窄口部28〇且其窄口部28〇係與該接地開孔 26連通之縱貫通道28，如第7圖所示。 於封裝結構内形成該等喇队狀縱貫通道28將有效增 進封裝件之整體散熱效率。如第7圖所示，藉由連接該晶 片接置區201且傳熱良好的鋼跡線203有效地將半導體晶 片21運作時產生之熱量傳遞至基板2()之接地開孔26， 透過基板20表面的接地開孔26窄口逐漸向上外擴而外露 出封裝膠體23頂面230以構成一錐形縱貫通道28，利用 該縱貫通道28由窄至寬不同截面積的變化，不僅使得攜 有熱量之熱空氣往上移動時具有宽闊的逸散空間；同時， 於該縱貫通道28内空氣總流量不變的狀態下，截面積與 空氣流動速度成反比，使得空氣行經截面積較小之接地開 孔26時流速增加俾以快速攜離基板20表面的熱量並且加 速冷空氣回補（如第7圖接地開孔26處之箭號所示）之 動作；同時，當半導體晶片21作功（Work)量愈大，晶 II 丨！ ί — — ! — - I I (請先閱讀背面之注意事項寫本頁) 訂· · -線- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 7 16253 經濟部智慧財產局員工消費合作社印製 587319 五、發明說明（8 片周圍溫度上升愈多時’依據白努力定律及理想氣體理論 得知熱對流速度相對加快，故而加速冷空氣回補使散熱速 率增高，該縱貫通道28得視晶片21產熱量多寡而得自動 調節封裝件散熱速率。 第二實施例： 第8圖所示者係為本發明第二實施例之半導體封裝 件之剖視圖。其結構大致同於前述之第一實施例，不同處 僅在於該第二實施例之封裝結構係於膠體封裝完成後復藉 以導熱膠劑390提供一散熱件39黏接至封裝膠體33頂面 330，該散熱件39兩側並外伸有彎折部俾以黏著於該接地 開孔36上方處之基板30表面，用以協助基板3〇表面進 灯散熱；半導體晶片31運作時產生之熱量傳遞至該接地 開孔3 6後，邛分熱量得以透過該散熱件3 9直接逸散到大 氣中，進一步提昇封裝件之散熱效能，且該散熱件係 黏設於接地開孔36上方之基板3〇表面，亦不致影響縱貫 通道38内之熱對流。 上述之具體實施例僅係用以詳細說明本發明之特點 及功效，而非以之限定本發明之可實施範圍，在未脫離本 發明所揭示之技術範疇與精神下，任何運用本發明所完成 之等效改變及修飾，均應仍為本發明下揭之申請專利範圍 所涵蓋。 【符號標號說明】： 1，2 半導體封裝件 1〇,20,30基板 裝--- (請先閱讀背面之注意事項@寫本頁) 訂·· --線. 200 芯層 200a,200h 试 ® !·、V. Description of the invention (2) The case of Japanese Patent Laid-Open No. 8-70082 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs discloses a tape carrier package (Tape Carrier Package), as shown in Figure 2A (Top view) and FIG. 2B (perspective sectional view), this package structure is fixed with a plurality of tie bars 105 (Tie Bar) to a wafer holder 101 俾 to house the packaged semiconductor wafer 11, the wafer holder 101 peripheral ring is provided with a Tcp guide pin group 102 俾 for the chip 11 to be conductively connected with a plurality of inner guide pins 103 (Inner Leads). The feature of this technology is to construct multiple resin materials with vertical channels on the ties 105. The frame body of 1 8 (Hole Frame Body), the principle of setting of these frame bodies 15 is based on the Bernoulli's Law (Bernouui, s Equation): P + l / 2mv2 = k (P represents pressure, m represents mass , V represents velocity, k represents constant), then the pressure difference (a P) will form a velocity field, and according to the ideal gas theory, the pressure (P) is proportional to the temperature (T) ', so the thermal energy generated by the operation of the semiconductor wafer 11 will be Increase the temperature around the wafer, which will increase the pressure. Forming a rising hot air, cool air covering the heat convection velocity, to achieve the effect of natural cooling of the wafer. However, the frames 15 included in this technology are additionally glued into the packaging structure 1, which increases the packaging cost. At the same time, in order to maintain the smooth passage of the channels of the frames 15 and ensure the heat dissipation function of the package, After the molding process is completed, the slag removal operation is repeatedly performed, which causes the packaging time to be extended and the complexity of the process steps to be increased. [Summary of the Invention]: The main purpose of the present invention is to provide a semiconductor package with a plurality of tapered heat dissipation channels running through the packaging structure, wherein the heat dissipation channels are gradually upward from the ground openings of the substrate. The size of this paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 2 16253 (Please read the precautions on the back first <install — ht page) Order ·· • Line · A7 B7 V. Description of the invention (Extended to the top of the packaging colloid, the heat convection speed of the substrate surface is reversed by q ^ ^ different M ^ liters, which accelerates the dissipation of the semiconducting 艚 Θ y ^ + thermal energy generated during the operation of daily solar films. The other φΐη -------------- install --- (please read the precautions on the back β first to write this page) is to provide a kind of automatic adjustment for the amount of heat generated when the semiconductor is in operation. The heat dissipation rate is based on natural cooling! The semiconductor chip does not need to add any additional heat dissipation structure, and has a cost-saving and environmentally friendly semiconductor package. The purpose of this issue is to provide a package that does not need to add additional components. Mould In combination with the applicable substrate, a semiconductor package with great process convenience can be implemented. In view of the above and other objectives, the semiconductor package provided with a through-radiation channel provided by the present invention includes: a semiconductor wafer; a substrate, A center of the substrate is provided with a wafer receiving area for adhering the semiconductor wafer. A plurality of grounding openings are provided at appropriate positions outside the wafer receiving area, and a plurality of self-mounting wafers are arranged on the surface of the substrate. The contact area extends outward and is connected to the copper traces of the ground openings; a plurality of gold wires for conductively connecting the aa chip and the substrate '. Most solder balls that provide the semiconductor package with electrical connections to external devices And a packaging gel for covering a semiconductor wafer and forming a plurality of narrow mouth-shaped conical through-channels connected to the ground opening after printing by an employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economics. The semiconductor package of the present invention The feature is that a plurality of ground openings are formed above the ground opening of the substrate to communicate with the ground opening and gradually expand upward and outward, and the opening is exposed outside the top surface of the packaging gel. A through channel, which has a wide A and a narrow A shape, and the cross-sectional area of the channel is enlarged from the narrow part of the ground through hole on the surface of the connection substrate to the top surface of the encapsulant. According to the ideal gas perspective, 16253 587319 A7 ------- B7__________ 5. Description of the invention (4) The pressure (P) is directly proportional to the temperature (τ), so when the heat generated by the operation of the semiconductor wafer increases the temperature around the wafer, the pressure will also increase; Bernoulli's Equation: P + 1/2 mv2 = k (where P is the pressure, m is the mass, and k is the constant). When air flows through the through passage, the pressure difference (△! &Gt;) forms the velocity In the field, the pressure (p) itself is inversely proportional to the cross-sectional area (A). Therefore, under the condition that the total air flow is constant, the air flow velocity in the through channel is inversely proportional to the cross-sectional area of the through channel. Then, when the air flows through the grounded opening with a small cross-sectional area, the flow rate is faster, so that the heat on the substrate surface can be quickly carried away by the air to achieve the effect of naturally cooling the wafer; at the same time, as the semiconductor wafer performs work, As the temperature increases, the convection rate of the wafer increases, and the rate of air passing through the substrate channel increases the heat dissipation efficiency to form a packaging device that automatically adjusts the heat dissipation rate according to the amount of heat generated by the semiconductor wafer. [Brief description of the drawings]: The following is a detailed description of the features and effects of the present invention with better specific examples and the accompanying drawings: Figure 1 is a cross-section of a conventional semiconductor package with heat sink. Figures and 2B are top and perspective cross-sectional views of the semiconductor package of Japanese Patent Laid-Open No. 8_70082; Figure 3 is a schematic cross-sectional view of the semiconductor package of the first embodiment of the present invention; Figure 4 is The top perspective view of the semiconductor package of the present invention; FIG. 5 is a cross-section of the semiconductor package of the present invention during the molding process I -------------- II (Please read the precautions on the back first β write this page) Order _ ·-Line · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) 4 16253 587319 B7 V. Description of the invention ( 5) Schematic view; Figure 6 is a partial enlarged perspective view of the mold used to make the semiconductor package of the present invention, and 'upper mold'; 1111 —II --- install --- (Please read the back (Note on this page) Figure 7 is the invention 4 inner surface of the semiconductor package member through the channel structure is not intended; and FIG. 8 lines + schematic cross-sectional view of the channel configuration of the package through the inner conductor of the second embodiment Yuan embodiment of the invention X memory. [Detailed description of the invention]: An embodiment of the farm: As shown in FIG. 3, a cross-sectional view of the semiconductor package of the first embodiment of the present invention. The semiconductor package of the first embodiment includes a substrate 20, a semiconductor wafer 21 adhered to the substrate 20, and a plurality of gold wires 22 that electrically connect the substrate 20 and the wafer 21 to the semiconductor package 2 A plurality of solder balls 24 electrically connected to an external device, and a packaging gel 23 for covering the semiconductor wafer 21 and a plurality of gold wires 22. The substrate 20 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has a core layer 200 (Core) made of materials such as BT (Bismaleimide Triazine) resin, epoxy resin, polyurethane resin, and triazabenzene resin. In the center of the upper surface 200a of the core layer 200, a wafer receiving area 201 is defined in advance, and a plurality of first conductive traces (not shown) are arranged around the wafer receiving area 201. In contrast, the core A plurality of second conductive traces (not shown) are also arranged on the lower surface 200b of the layer 200, and the first conductive traces are conductively connected through vias (not shown) provided in the core layer 200. And second conductive traces (none of which are shown); This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 Gongchu) 5 16253 587319 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs V. Invention Note (6) In order to protect the first conductive trace and the second conductive trace from the outside, the upper and lower surfaces of the core layer 200, 200a, and 200b are respectively coated to cover the first conductive trace. Solder resist layer 250 on a trace (not shown) (Sol der Mask) and a solder resist layer 251 for covering the second conductive trace (not shown), but a fresh pad (not shown) and a second end of the first conductive trace (not shown) The solder pads 202 at the ends of the conductive traces (not shown) respectively expose openings t formed in the upper solder resist layer 250 and the lower solder resist layer 251. The substrate 20 is located at an appropriate position outside the wafer receiving area 201. A plurality of ground openings 26 (Ground Opening) penetrating through the substrate 20 and having a cross-sectional area A are opened by a conventional drilling technique, FIG. 4 It is a top perspective view of the semiconductor package of the present invention. As shown in the figure, a plurality of copper traces connected to the ground opening are formed outward from the wafer receiving area 201 on the upper surface (not shown) of the core layer. 203 (Copper Trace) to enhance the temperature sensitivity of the ground opening 26 to the semiconductor wafer 21. As shown in FIG. 3, the semiconductor wafer 21 is adhered to the substrate 200 wafer receiving area 201 with a conventional adhesive 204 such as silver glue or polyimide tape, and the two are completed. Then, the semiconductor wafer 21 and the pads (not shown) of the conductive trace terminals are conductively connected with the gold wire 22, and the semiconductor wafer 21 is conductively connected to the substrate 20, and then gel-packed. Referring to FIG. 5, the semiconductor device 2 is first placed in a packaging mold 27 for molding, so as to form a packaging gel 23 for covering the semiconductor wafer 21 and the gold wire 22. The mold 27 has a package --- (Please read the precautions on the back to write this page). --- The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 6 16253 ^ / 319 A7 V. Description of the invention (7) The upper mold 270 and Yide green 财 μ are composed of the upper mold 270 and the lower mold 271, as shown in Fig. 5 and Fig. 6 (兮 ® and &amp; ... μ) As shown in a partial enlarged view of the upper mold), a plurality of cones 273 integrally formed with the upper mold 27 slot forming block m are formed in the upper mold 270 cavity corresponding to the ground opening 26 of the substrate 20 The cone 273 has a top 274 and a bottom 275, and the cross-sectional area of the bottom 275 is significantly larger than the cross-sectional area of the top 274. After the mold is closed, the top 274 of the cone 273 is connected to the base plate 20. The ground opening 26 is connected to the slot forming block 272 of the upper mold 270 through the bottom 275 of the cone 273, so that the package after demolding has a plurality of longitudinal sections with a wide opening 281 and The narrow mouth portion 28 and its narrow mouth portion 28 are through channels 28 communicating with the ground opening 26, as shown in FIG. The formation of these parallel channels 28 in the package structure will effectively increase the overall heat dissipation efficiency of the package. As shown in FIG. 7, the steel traces 203 connected to the wafer receiving region 201 and having good heat transfer effectively transfer the heat generated during the operation of the semiconductor wafer 21 to the ground opening 26 of the substrate 2 (), and pass through the substrate The grounding opening 26 on the 20 surface gradually expands upward and outward to expose the top surface 230 of the encapsulant 23 to form a conical through channel 28. The use of the through channel 28 changes from narrow to wide different cross-sectional areas, which not only makes When the hot air carrying heat moves upward, it has a wide space for dissipating. At the same time, under the condition that the total air flow in the through passage 28 is constant, the cross-sectional area is inversely proportional to the air flow speed, so that the air passes through the cross-sectional area. The flow velocity of the smaller ground opening 26 increases to quickly remove the heat from the surface of the substrate 20 and accelerate the action of cold air replenishment (shown by the arrow at ground opening 26 in Figure 7). At the same time, when the semiconductor wafer 21 The greater the amount of work, the crystal II 丨! ί — —! —-II (Please read the notes on the back first to write this page) Order · · -Line-Printed on the paper by the Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economy Standards for Chinese papers (CNS) A4 (210 X 297 mm) 7 16253 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 587319 V. Description of the invention (when the ambient temperature of the 8 tablets increases more, according to the White Effort Law and Ideal Gas Theory, it is known that the heat convection speed is relatively faster, so the cold Air replenishment increases the heat dissipation rate, and the through channel 28 may automatically adjust the heat dissipation rate of the package depending on the amount of heat generated by the chip 21. Second embodiment: The one shown in FIG. 8 is the semiconductor of the second embodiment of the present invention A cross-sectional view of the package. The structure is substantially the same as the first embodiment described above, except that the package structure of the second embodiment is that after the colloidal package is completed, a thermally conductive adhesive 390 is used to provide a heat sink 39 for bonding to the package. The top surface 330 of the colloidal body 33, and two bent portions 两侧 extending from both sides of the heat sink 39 to stick to the surface of the substrate 30 above the ground opening 36 to assist the surface of the substrate 30. The lamp dissipates heat; after the heat generated during the operation of the semiconductor chip 31 is transferred to the ground opening 36, the divided heat can be directly dissipated into the atmosphere through the heat dissipating member 39, further improving the heat dissipation efficiency of the package, and the heat dissipating member. It is adhered to the surface of the substrate 30 above the ground opening 36, and it will not affect the thermal convection in the vertical channel 38. The specific embodiments described above are only used to explain the features and effects of the present invention in detail, but not to limit it. Without departing from the technical scope and spirit disclosed by the present invention, any equivalent changes and modifications made by using the present invention shall still be covered by the scope of the patent application disclosed by the present invention. Explanation of Symbols and Symbols: 1,2 Semiconductor Packages 10, 20, 30 Substrates --- (Please read the precautions on the back @write this page first) Order ··-Wires ! ·,

587319 A7 B7 五、發明說明（9 ) 經濟部智慧財產局員工消費合作社印製 201 晶片接置區 202 銲墊 203,303 鋼跡線 104,204,304 膠黏劑 105 繫條 101 晶片座 102 TCP導腳 103 内導腳 12,22 金線 13,23,33 封裝膠體 230,330 封裝膠體頂面 14,24,34 錄球 15 架體 250,251 上、下拒銲劑層 26,36 接地開孔 27 封裝模具 270 上模 271 下模 272 開槽形成塊 273 錐體 274 錐體頂部 275 錐體底部 18,28,38 縱貫通道 280 窄口部 281 寬口部 19,39 散熱件 390 導熱膠劑 (請先閱讀背面之注意事項痛 裝—— 兄寫本頁) •線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 9 16253587319 A7 B7 V. Explanation of the invention (9) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, 201 Chip placement area 202 Solder pads 203, 303 Steel traces 104, 204, 304 Adhesive 105 Tie 101 Wafer holder 102 TCP guide pin 103 Inner guide pin 12,22 Gold wire 13,23,33 Encapsulated gel 230,330 Encapsulated colloid top surface 14,24,34 Recording ball 15 Frame 250,251 Upper and lower solder resist layers 26,36 Grounding hole 27 Packaging mold 270 Upper mold 271 Lower mold 272 Slot formation block 273 Cone 274 Cone top 275 Cone bottom 18,28,38 Through channel 280 Narrow mouth 281 Wide mouth 19,39 Heat sink 390 Thermal adhesive (Please read the precautions on the back first —————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————–––––––––––.

Claims (1)

第90109240號專利申請案 申請專利範圍修正本 (92年11月2 7曰） 一種具得貫穿整體封裝結構之通道之半導體封裝件，係 包括： -基板’該基板中央預設有—晶片接置區，並於該晶 片接置區外之部位上開設有多數之接地開孔； -半導體晶片，其係黏接至該基板之晶片接置區上， 並與該基板形成電性藕接關係； 多數之導電元件，其係植接於該基板無晶片接著之表 面；以及 一封裝膠體’用以包覆該半導體晶片而成型於該基板 表面，俾以開設複數個具窄口部以與該基板接地開孔相通 連之錐狀貫通道。 2.如申請專利範圍帛！項之半導體封裝件，其中，該半導 體封裝件係為一 BGA半導體封裝件。 如申請專利項之半導體封裝件，其中，該接地 開孔係貫穿該基板俾以形成一通孔。 4.如申請專利範圍第】項之半導體封裝件，其中，於該基 板表面上佈設多條連結該晶片接置區與該等接地開孔之 銅跡線（Copper Trace)。 5·如申印專利範圍第】項之半導體封裝 元件係指銲球。 °亥¥電 〇 · 5月利範圍第Κ平导體封裝件，其十，該封裝 谬體係藉—封裝模具俾供㈣封裝樹脂注人固化所構成 1 16253 7·如申請專利範圍帛i項之半導體封農件，其中，對應於 该基板接地開孔之上方形成有—底部與封裝模具的上模 相連之錐體結構，俾供該封裝膠體成型脫模後形成_錐 狀貫通道。 8. 如申請專利範圍第7項之半導體封裝件，其中，該錐體 結構係具有—頂部及—底部，且該底部之截面積係明顯 地大於該頂部之截面積。 9. 如申請專利範圍第！ 5戈7項之半導體封裝件，其中，該 錐狀貫通道係縱貫開設於該封裝件内並且外露於^ 膠體上。 1〇·如申請專利範圍第！項之半導體封裝件，其中，該封裝 膠體上得接置-散熱件，並藉由該散熱件兩側之彎折部 黏接至該接地開孔周圍之基板表面上。 U· 一種具有貫穿通道之半導體封裝件製法，係包含： ^先備一基板，於該基板中央預置一晶片接置區，並於 該晶片接置區外之部位開設複數個接地開孔； 、 施以上片及銲接作業； 進行膠體封裝步驟，藉由一具有複數個錐體結構之封 裝模具實施模壓，俾以形成一具有多條錐狀貫通道且以其 貫通道窄口部與該接地開孔相通連之封裝膠體。 〃 12·如申請專利範圍第η項之半導體封裝件製法，其中，該 接地開孔係貫穿該基板俾以形成一通孔。 13.如申請專利範圍第η項之半導體封裝件製法，其中，於 該基板表面上佈設多條連結該晶片接置區與該等接地開 2 16253 孔之銅跡線（C〇Pper Trace)。 η.如申請專利範圍第u項之半 導電元件係指輝球。 u法，其中’該 =申請專利範《η項之半導體封裝件製法 封裝模具係由一上楛 、Τ ^ 者。 上Μ #“上模合模之下模所構成 16.:申請專利範圍第u項之半導體封裝件製法，其中，兮 明顯地大&quot;！ 其令該底部截面積係 具之上=截面積，並藉由該底部連接於封裝模 17:申請專利範圍第〗丨項之半導體封裝件製法，1中 錐狀貫通道係縱貫開設於該封 :μ 膠體上。 了我仵内並且外露於該封裝 18.如申請專利範圍 封I职〜θ J^牛導體封裝件製法，其中，該 折；點接一散熱件，並藉由該散熱件兩側之彎 折。P黏接至該接地開孔周圍之基板表面上。 3 16253No. 90109240 Patent Application Amendment to Patent Scope (November 27, 1992) A semiconductor package with a channel that runs through the overall package structure, which includes:-a substrate, which is preset in the center of the substrate-a wafer connection Area, and a plurality of grounding openings are provided on the part outside the wafer receiving area;-a semiconductor wafer, which is adhered to the wafer receiving area of the substrate, and forms an electrical connection relationship with the substrate; Most conductive elements are implanted on the surface of the substrate without a wafer; and a packaging gel is used to cover the semiconductor wafer and is formed on the surface of the substrate, and a plurality of narrow openings are formed to communicate with the substrate. A conical through channel connected to the ground opening. 2. If the scope of patent application is 帛! The semiconductor package of claim 1, wherein the semiconductor package is a BGA semiconductor package. For example, the semiconductor package of the patent application, wherein the ground opening is formed through the substrate to form a through hole. 4. The semiconductor package according to item [Scope of the patent application], wherein a plurality of copper traces (Copper Trace) connecting the chip receiving area and the ground openings are arranged on the surface of the substrate. 5 · Semiconductor package components such as those in the scope of application for printed patents refer to solder balls. ° 海 ¥ 电 · The range of K-flat conductor package in May, tenth, the packaging system borrows-packaging mold 俾 for packaging resin injection and curing constitutes 1 16253 7 · as the scope of patent application 项 item In the semiconductor package, a cone structure is formed above the ground opening of the substrate to connect the bottom of the packaging mold to the upper mold of the packaging mold, so that the packaging colloid can be formed into a cone-shaped through channel after being demolded. 8. The semiconductor package of claim 7 in which the cone structure has-a top and a-bottom, and the cross-sectional area of the bottom is significantly larger than the cross-sectional area of the top. 9. If the scope of patent application is the first! The semiconductor package of 5 items and 7 items, wherein the tapered through channel is opened in the package and is exposed on the colloid. 1〇 · If the scope of patent application is the first! The semiconductor package according to claim 1, wherein the packaging colloid needs to be connected with a heat sink, and is bonded to the surface of the substrate around the ground opening through the bent portions on both sides of the heat sink. U · A method for manufacturing a semiconductor package with a through channel, comprising: ^ first preparing a substrate, presetting a wafer receiving area in the center of the substrate, and opening a plurality of ground openings outside the wafer receiving area; The above-mentioned sheet and welding operations are performed; a colloidal packaging step is performed, and compression is performed by a packaging mold having a plurality of cone structures, so as to form a plurality of cone-shaped through channels and the narrow mouth portion of the through channels and the ground The encapsulating gel connected with the openings. 〃 12. The method of manufacturing a semiconductor package according to item η of the patent application, wherein the ground opening is formed through the substrate 俾 to form a through hole. 13. The method for manufacturing a semiconductor package according to item η of the patent application scope, wherein a plurality of copper traces (Copper Trace) connecting the wafer receiving area and the grounding openings with 2, 16253 holes are arranged on the surface of the substrate. η. The semi-conductive element according to item u of the patent application scope refers to a glow ball. u method, where ‘this = application method of semiconductor package manufacturing method of item η The packaging mold is made by one of the above, T ^.上 Ｍ # “The upper mold is closed and the lower mold is composed of 16 .: The method for manufacturing a semiconductor package under the scope of application for patent item u, where Xi is significantly larger &quot; It makes the bottom cross-sectional area above the cross-sectional area. And by the method of manufacturing the semiconductor package with the bottom connected to the packaging mold 17: the scope of the patent application, the tapered through channel is opened in the seal: μ colloid. It is inside and exposed to The package 18. According to the scope of the patent application, the manufacturing method of the θJ ^ cattle conductor package, wherein the fold; a point is connected to a heat sink, and the two sides of the heat sink are bent. P is bonded to the ground On the surface of the substrate around the opening. 3 16253
TW090109240A 2001-04-18 2001-04-18 Ball grid array semiconductor packaging with heat sink channel TW587319B (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI695466B (en) * 2019-05-31 2020-06-01 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof
TWI714296B (en) * 2019-10-04 2020-12-21 欣興電子股份有限公司 Package substrate and manufacturing method thereof
CN112635432A (en) * 2019-10-09 2021-04-09 欣兴电子股份有限公司 Package substrate and manufacturing method thereof
US11373927B2 (en) 2018-05-30 2022-06-28 Unimicron Technology Corp. Package substrate and manufacturing method having a mesh gas-permeable structure disposed in the through hole

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11373927B2 (en) 2018-05-30 2022-06-28 Unimicron Technology Corp. Package substrate and manufacturing method having a mesh gas-permeable structure disposed in the through hole
TWI695466B (en) * 2019-05-31 2020-06-01 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof
TWI714296B (en) * 2019-10-04 2020-12-21 欣興電子股份有限公司 Package substrate and manufacturing method thereof
CN112635432A (en) * 2019-10-09 2021-04-09 欣兴电子股份有限公司 Package substrate and manufacturing method thereof

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