TWI256683B - A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor - Google Patents

A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor

Info

Publication number
TWI256683B
TWI256683B TW090114096A TW90114096A TWI256683B TW I256683 B TWI256683 B TW I256683B TW 090114096 A TW090114096 A TW 090114096A TW 90114096 A TW90114096 A TW 90114096A TW I256683 B TWI256683 B TW I256683B
Authority
TW
Taiwan
Prior art keywords
damascene structure
capacitor
manufacturing
dual
integrated circuit
Prior art date
Application number
TW090114096A
Other languages
English (en)
Chinese (zh)
Inventor
Sailesh Chittipeddi
Original Assignee
Agere Syst Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Syst Guardian Corp filed Critical Agere Syst Guardian Corp
Application granted granted Critical
Publication of TWI256683B publication Critical patent/TWI256683B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW090114096A 2000-06-16 2001-06-12 A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor TWI256683B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/596,382 US6762087B1 (en) 2000-06-16 2000-06-16 Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor

Publications (1)

Publication Number Publication Date
TWI256683B true TWI256683B (en) 2006-06-11

Family

ID=24387077

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090114096A TWI256683B (en) 2000-06-16 2001-06-12 A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor

Country Status (5)

Country Link
US (1) US6762087B1 (enExample)
JP (1) JP2002043433A (enExample)
KR (1) KR100727794B1 (enExample)
GB (1) GB2368722B (enExample)
TW (1) TWI256683B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120223413A1 (en) 2011-03-04 2012-09-06 Nick Lindert Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer
JP2013026599A (ja) * 2011-07-26 2013-02-04 Elpida Memory Inc 半導体装置の製造方法
WO2016182782A1 (en) 2015-05-08 2016-11-17 Cirrus Logic International Semiconductor Ltd. High denstiy capacitors formed from thin vertical semiconductor structures such as finfets

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633781A (en) 1995-12-22 1997-05-27 International Business Machines Corporation Isolated sidewall capacitor having a compound plate electrode
US6025226A (en) * 1998-01-15 2000-02-15 International Business Machines Corporation Method of forming a capacitor and a capacitor formed using the method
US6251740B1 (en) * 1998-12-23 2001-06-26 Lsi Logic Corporation Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit
US6156640A (en) 1998-07-14 2000-12-05 United Microelectronics Corp. Damascene process with anti-reflection coating
TW374948B (en) 1998-07-28 1999-11-21 United Microelectronics Corp Method of prevention of poisoning trenches in dual damascene process structures and dielectric layer windows
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6037216A (en) 1998-11-02 2000-03-14 Vanguard International Semiconductor Corporation Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process
TW389993B (en) 1998-11-18 2000-05-11 United Microelectronics Corp Method for producing thin film resistance of dual damascene interconnect
JP2000159698A (ja) * 1998-11-30 2000-06-13 Matsushita Electric Ind Co Ltd 芳香族メチリデン化合物、それを製造するための芳香族アルデヒド化合物、及びそれらの製造方法
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6320244B1 (en) 1999-01-12 2001-11-20 Agere Systems Guardian Corp. Integrated circuit device having dual damascene capacitor
US6346454B1 (en) * 1999-01-12 2002-02-12 Agere Systems Guardian Corp. Method of making dual damascene interconnect structure and metal electrode capacitor
US6365327B1 (en) 1999-08-30 2002-04-02 Agere Systems Guardian Corp. Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit
US6313025B1 (en) 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
US6281134B1 (en) 1999-10-22 2001-08-28 United Microelectronics Corp. Method for combining logic circuit and capacitor
US6228711B1 (en) * 1999-11-30 2001-05-08 United Microelectronics Corp. Method of fabricating dynamic random access memory
US6383858B1 (en) * 2000-02-16 2002-05-07 Agere Systems Guardian Corp. Interdigitated capacitor structure for use in an integrated circuit
US6664185B1 (en) * 2002-04-25 2003-12-16 Advanced Micro Devices, Inc. Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect

Also Published As

Publication number Publication date
KR20010113520A (ko) 2001-12-28
GB2368722B (en) 2004-12-01
JP2002043433A (ja) 2002-02-08
US6762087B1 (en) 2004-07-13
GB2368722A (en) 2002-05-08
KR100727794B1 (ko) 2007-06-14
GB0114308D0 (en) 2001-08-01

Similar Documents

Publication Publication Date Title
WO2004027834A3 (en) Mim capacitor structures and fabrication methods in dual-damascene structures
WO2004061916A3 (en) Method of forming a low-k dual damascene interconnect structure
WO2003060977A3 (en) Method for preventing undesirable etching of contact hole sidewalls in a preclean etching step
WO2004012254A8 (ja) 半導体装置の製造方法
TW200509403A (en) Semiconductor device including a capacitor having improved structural stability and enhanced capacitance, and method of manufacturing the semiconductor device
WO2002050894A3 (en) Structural reinforcement of highly porous low k dielectric films by cu diffusion barrier structures
WO2006063353A3 (en) Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step
ATE378799T1 (de) Photolithographisch hergestellter, integrierter kondensator mit selbst-ausgerichteten elektroden und dielektrika
SG125881A1 (en) Define via in dual damascene process
WO2002023625A3 (en) Semiconductor device and fabrication method therefor
DE69942090D1 (de) Leiterplattenmerkmale mit reduzierter parasitärer kapazität und deren herstellungsverfahren
TWI268538B (en) Metal-insulator-metal (MIM) capacitor structure formed with dual damascene structure
TW200603370A (en) Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask
SG128440A1 (en) Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics
WO2002029865A3 (en) Method of manufacturing a semiconductor component and semiconductor component thereof
TWI256683B (en) A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor
WO2009033837A3 (en) Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
SG147268A1 (en) Integrated circuit with simultaneous fabrication of dual damascene via and trench
TW200507173A (en) Method for manufacturing semiconductor device
KR100482025B1 (ko) 반도체 소자의 제조방법
US20020086519A1 (en) Stacked vias and method
TW200612537A (en) Interconnect structure and method of fabricating the same
KR100421657B1 (ko) 복합 반도체 소자의 콘택홀 제조 방법
KR101026475B1 (ko) 반도체 소자의 제조 방법
US8664743B1 (en) Air-gap formation in interconnect structures

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent