WO2009033837A3 - Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias - Google Patents

Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias Download PDF

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Publication number
WO2009033837A3
WO2009033837A3 PCT/EP2008/058306 EP2008058306W WO2009033837A3 WO 2009033837 A3 WO2009033837 A3 WO 2009033837A3 EP 2008058306 W EP2008058306 W EP 2008058306W WO 2009033837 A3 WO2009033837 A3 WO 2009033837A3
Authority
WO
WIPO (PCT)
Prior art keywords
ultra
deep vias
integrated circuits
dielectric layers
dimensional integrated
Prior art date
Application number
PCT/EP2008/058306
Other languages
French (fr)
Other versions
WO2009033837A2 (en
Inventor
Mark Todhunter Robson
Tulipe Douglas La Jr
Original Assignee
Ibm
Ibm Uk
Mark Todhunter Robson
Tulipe Douglas La Jr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/853,139 external-priority patent/US7704869B2/en
Priority claimed from US11/853,118 external-priority patent/US7723851B2/en
Application filed by Ibm, Ibm Uk, Mark Todhunter Robson, Tulipe Douglas La Jr filed Critical Ibm
Publication of WO2009033837A2 publication Critical patent/WO2009033837A2/en
Publication of WO2009033837A3 publication Critical patent/WO2009033837A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
PCT/EP2008/058306 2007-09-11 2008-06-27 Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias WO2009033837A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/853,118 2007-09-11
US11/853,139 US7704869B2 (en) 2007-09-11 2007-09-11 Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
US11/853,139 2007-09-11
US11/853,118 US7723851B2 (en) 2007-09-11 2007-09-11 Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias

Publications (2)

Publication Number Publication Date
WO2009033837A2 WO2009033837A2 (en) 2009-03-19
WO2009033837A3 true WO2009033837A3 (en) 2009-08-13

Family

ID=39766826

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/058306 WO2009033837A2 (en) 2007-09-11 2008-06-27 Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias

Country Status (2)

Country Link
TW (1) TW200924058A (en)
WO (1) WO2009033837A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012221998A (en) * 2011-04-04 2012-11-12 Toshiba Corp Semiconductor device and manufacturing method of the same
US9704880B2 (en) * 2013-11-06 2017-07-11 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for a semiconductor structure having multiple semiconductor-device layers
US10163897B2 (en) 2013-11-15 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Inter-level connection for multi-layer structures
US10036957B2 (en) 2016-01-29 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Post development treatment method and material for shrinking critical dimension of photoresist layer
CN115207203B (en) * 2022-09-15 2022-12-02 材料科学姑苏实验室 Method for realizing steep side wall of laminated etching in aluminum-based superconducting circuit

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841195A (en) * 1992-02-06 1998-11-24 Stmicroelectronics, Inc. Semiconductor contact via structure
US6180997B1 (en) * 1998-02-23 2001-01-30 Winbond Electronics Corp. Structure for a multi-layered dielectric layer and manufacturing method thereof
US6232663B1 (en) * 1996-12-13 2001-05-15 Fujitsu Limited Semiconductor device having interlayer insulator and method for fabricating thereof
US20020076916A1 (en) * 2000-12-20 2002-06-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, and method of manufacturing the same
US20020142235A1 (en) * 2001-04-02 2002-10-03 Nec Corporation Photo mask for fabricating semiconductor device having dual damascene structure
US20030129829A1 (en) * 2002-01-08 2003-07-10 David Greenlaw Three-dimensional integrated semiconductor devices
US20040232554A1 (en) * 2003-05-23 2004-11-25 Renesas Technology Corp. Semiconductor device with effective heat-radiation
US20040241984A1 (en) * 2003-05-28 2004-12-02 Christoph Schwan Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process
DE102004044686A1 (en) * 2004-09-15 2006-03-16 Infineon Technologies Ag Integrated circuit with vias that have two sections, and manufacturing process

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841195A (en) * 1992-02-06 1998-11-24 Stmicroelectronics, Inc. Semiconductor contact via structure
US6232663B1 (en) * 1996-12-13 2001-05-15 Fujitsu Limited Semiconductor device having interlayer insulator and method for fabricating thereof
US6180997B1 (en) * 1998-02-23 2001-01-30 Winbond Electronics Corp. Structure for a multi-layered dielectric layer and manufacturing method thereof
US20020076916A1 (en) * 2000-12-20 2002-06-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, and method of manufacturing the same
US20020142235A1 (en) * 2001-04-02 2002-10-03 Nec Corporation Photo mask for fabricating semiconductor device having dual damascene structure
US20030129829A1 (en) * 2002-01-08 2003-07-10 David Greenlaw Three-dimensional integrated semiconductor devices
US20040232554A1 (en) * 2003-05-23 2004-11-25 Renesas Technology Corp. Semiconductor device with effective heat-radiation
US20040241984A1 (en) * 2003-05-28 2004-12-02 Christoph Schwan Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process
DE102004044686A1 (en) * 2004-09-15 2006-03-16 Infineon Technologies Ag Integrated circuit with vias that have two sections, and manufacturing process

Also Published As

Publication number Publication date
WO2009033837A2 (en) 2009-03-19
TW200924058A (en) 2009-06-01

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