GB2368722B - A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor - Google Patents
A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitorInfo
- Publication number
- GB2368722B GB2368722B GB0114308A GB0114308A GB2368722B GB 2368722 B GB2368722 B GB 2368722B GB 0114308 A GB0114308 A GB 0114308A GB 0114308 A GB0114308 A GB 0114308A GB 2368722 B GB2368722 B GB 2368722B
- Authority
- GB
- United Kingdom
- Prior art keywords
- dual
- capacitor
- manufacturing
- integrated circuit
- circuit including
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000003990 capacitor Substances 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/596,382 US6762087B1 (en) | 2000-06-16 | 2000-06-16 | Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0114308D0 GB0114308D0 (en) | 2001-08-01 |
| GB2368722A GB2368722A (en) | 2002-05-08 |
| GB2368722B true GB2368722B (en) | 2004-12-01 |
Family
ID=24387077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0114308A Expired - Fee Related GB2368722B (en) | 2000-06-16 | 2001-06-12 | A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6762087B1 (enExample) |
| JP (1) | JP2002043433A (enExample) |
| KR (1) | KR100727794B1 (enExample) |
| GB (1) | GB2368722B (enExample) |
| TW (1) | TWI256683B (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120223413A1 (en) | 2011-03-04 | 2012-09-06 | Nick Lindert | Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer |
| JP2013026599A (ja) * | 2011-07-26 | 2013-02-04 | Elpida Memory Inc | 半導体装置の製造方法 |
| WO2016182782A1 (en) | 2015-05-08 | 2016-11-17 | Cirrus Logic International Semiconductor Ltd. | High denstiy capacitors formed from thin vertical semiconductor structures such as finfets |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025226A (en) * | 1998-01-15 | 2000-02-15 | International Business Machines Corporation | Method of forming a capacitor and a capacitor formed using the method |
| EP1020905A1 (en) * | 1999-01-12 | 2000-07-19 | Lucent Technologies Inc. | Integrated circuit device having dual damascene interconnect structure and metal electrode capacitor and associated method for making |
| EP1022783A2 (en) * | 1999-01-12 | 2000-07-26 | Lucent Technologies Inc. | Integrated circuit device having dual damascene capacitor and associated method for making |
| GB2356974A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
| GB2356973A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
| GB2365217A (en) * | 2000-02-16 | 2002-02-13 | Agere Syst Guardian Corp | Interdigitated capacitor structure for use in an integrated circuit |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5633781A (en) | 1995-12-22 | 1997-05-27 | International Business Machines Corporation | Isolated sidewall capacitor having a compound plate electrode |
| US6251740B1 (en) * | 1998-12-23 | 2001-06-26 | Lsi Logic Corporation | Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit |
| US6156640A (en) | 1998-07-14 | 2000-12-05 | United Microelectronics Corp. | Damascene process with anti-reflection coating |
| TW374948B (en) | 1998-07-28 | 1999-11-21 | United Microelectronics Corp | Method of prevention of poisoning trenches in dual damascene process structures and dielectric layer windows |
| US6174803B1 (en) | 1998-09-16 | 2001-01-16 | Vsli Technology | Integrated circuit device interconnection techniques |
| US6037216A (en) | 1998-11-02 | 2000-03-14 | Vanguard International Semiconductor Corporation | Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process |
| TW389993B (en) | 1998-11-18 | 2000-05-11 | United Microelectronics Corp | Method for producing thin film resistance of dual damascene interconnect |
| JP2000159698A (ja) * | 1998-11-30 | 2000-06-13 | Matsushita Electric Ind Co Ltd | 芳香族メチリデン化合物、それを製造するための芳香族アルデヒド化合物、及びそれらの製造方法 |
| US6303423B1 (en) * | 1998-12-21 | 2001-10-16 | Megic Corporation | Method for forming high performance system-on-chip using post passivation process |
| US6281134B1 (en) | 1999-10-22 | 2001-08-28 | United Microelectronics Corp. | Method for combining logic circuit and capacitor |
| US6228711B1 (en) * | 1999-11-30 | 2001-05-08 | United Microelectronics Corp. | Method of fabricating dynamic random access memory |
| US6664185B1 (en) * | 2002-04-25 | 2003-12-16 | Advanced Micro Devices, Inc. | Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect |
-
2000
- 2000-06-16 US US09/596,382 patent/US6762087B1/en not_active Expired - Lifetime
-
2001
- 2001-06-12 TW TW090114096A patent/TWI256683B/zh not_active IP Right Cessation
- 2001-06-12 GB GB0114308A patent/GB2368722B/en not_active Expired - Fee Related
- 2001-06-15 JP JP2001181366A patent/JP2002043433A/ja active Pending
- 2001-06-16 KR KR1020010034116A patent/KR100727794B1/ko not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025226A (en) * | 1998-01-15 | 2000-02-15 | International Business Machines Corporation | Method of forming a capacitor and a capacitor formed using the method |
| EP1020905A1 (en) * | 1999-01-12 | 2000-07-19 | Lucent Technologies Inc. | Integrated circuit device having dual damascene interconnect structure and metal electrode capacitor and associated method for making |
| EP1022783A2 (en) * | 1999-01-12 | 2000-07-26 | Lucent Technologies Inc. | Integrated circuit device having dual damascene capacitor and associated method for making |
| GB2356974A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
| GB2356973A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
| GB2365217A (en) * | 2000-02-16 | 2002-02-13 | Agere Syst Guardian Corp | Interdigitated capacitor structure for use in an integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010113520A (ko) | 2001-12-28 |
| JP2002043433A (ja) | 2002-02-08 |
| TWI256683B (en) | 2006-06-11 |
| US6762087B1 (en) | 2004-07-13 |
| GB2368722A (en) | 2002-05-08 |
| KR100727794B1 (ko) | 2007-06-14 |
| GB0114308D0 (en) | 2001-08-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20160612 |