TWI251353B - Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion - Google Patents

Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion Download PDF

Info

Publication number
TWI251353B
TWI251353B TW093129734A TW93129734A TWI251353B TW I251353 B TWI251353 B TW I251353B TW 093129734 A TW093129734 A TW 093129734A TW 93129734 A TW93129734 A TW 93129734A TW I251353 B TWI251353 B TW I251353B
Authority
TW
Taiwan
Prior art keywords
wafer
thermal expansion
layer
substrate
preparing
Prior art date
Application number
TW093129734A
Other languages
English (en)
Chinese (zh)
Other versions
TW200611423A (en
Inventor
Jeffrey M Peterson
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Application granted granted Critical
Publication of TWI251353B publication Critical patent/TWI251353B/zh
Publication of TW200611423A publication Critical patent/TW200611423A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
TW093129734A 2003-04-18 2004-09-30 Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion TWI251353B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/418,870 US6884645B2 (en) 2003-04-18 2003-04-18 Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion

Publications (2)

Publication Number Publication Date
TWI251353B true TWI251353B (en) 2006-03-11
TW200611423A TW200611423A (en) 2006-04-01

Family

ID=33159201

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093129734A TWI251353B (en) 2003-04-18 2004-09-30 Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion

Country Status (5)

Country Link
US (1) US6884645B2 (https=)
EP (1) EP1552548A2 (https=)
JP (1) JP2006523960A (https=)
TW (1) TWI251353B (https=)
WO (1) WO2004095554A2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612895B2 (en) * 2007-05-18 2009-11-03 Suss Microtec Inc Apparatus and method for in-situ monitoring of wafer bonding time
DE102009007625A1 (de) 2008-11-14 2010-05-20 Osram Opto Semiconductors Gmbh Verbundsubstrat für einen Halbleiterchip
CN113376403B (zh) * 2021-05-12 2023-02-28 北京航天控制仪器研究所 一种有冗余功能的mems加速度计检测模块及其制作方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57153445A (en) 1981-03-17 1982-09-22 Nec Corp Sos semiconductor substrate
JPH0770472B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 半導体基板の製造方法
JPH01189909A (ja) * 1988-01-26 1989-07-31 Nippon Telegr & Teleph Corp <Ntt> 複合半導体基板
US5365088A (en) * 1988-08-02 1994-11-15 Santa Barbara Research Center Thermal/mechanical buffer for HgCdTe/Si direct hybridization
US5849627A (en) 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
JPH04171811A (ja) * 1990-11-05 1992-06-19 Olympus Optical Co Ltd 半導体装置
US5308980A (en) * 1991-02-20 1994-05-03 Amber Engineering, Inc. Thermal mismatch accommodated infrared detector hybrid array
JP2669368B2 (ja) * 1994-03-16 1997-10-27 日本電気株式会社 Ｓｉ基板上化合物半導体積層構造の製造方法
US5610389A (en) * 1995-03-23 1997-03-11 Rockwell International Corporation Stabilized hybrid focal plane array structure
US5585624A (en) * 1995-03-23 1996-12-17 Rockwell International Corporation Apparatus and method for mounting and stabilizing a hybrid focal plane array
JP2671859B2 (ja) * 1995-04-14 1997-11-05 日本電気株式会社 赤外線検出素子及びその製造方法
US5714760A (en) * 1995-06-07 1998-02-03 Boeing North American, Inc. Imbalanced layered composite focal plane array structure
US5846850A (en) * 1995-09-05 1998-12-08 Raytheon Ti Systems, Inc. Double sided interdiffusion process and structure for a double layer heterojunction focal plane array
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US6045614A (en) 1996-03-14 2000-04-04 Raytheon Company Method for epitaxial growth of twin-free, (111)-oriented II-VI alloy films on silicon substrates
JP3480297B2 (ja) * 1997-10-10 2003-12-15 豊田合成株式会社 半導体素子
US6320206B1 (en) 1999-02-05 2001-11-20 Lumileds Lighting, U.S., Llc Light emitting devices having wafer bonded aluminum gallium indium nitride structures and mirror stacks
US6498113B1 (en) 2001-06-04 2002-12-24 Cbl Technologies, Inc. Free standing substrates by laser-induced decoherency and regrowth
JP2003218031A (ja) * 2002-01-28 2003-07-31 Toshiba Ceramics Co Ltd 半導体ウェーハの製造方法
US6562127B1 (en) * 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates

Also Published As

Publication number Publication date
EP1552548A2 (en) 2005-07-13
US20040209440A1 (en) 2004-10-21
TW200611423A (en) 2006-04-01
US6884645B2 (en) 2005-04-26
JP2006523960A (ja) 2006-10-19
WO2004095554A3 (en) 2004-12-23
WO2004095554A2 (en) 2004-11-04

Similar Documents

Publication Publication Date Title
US11192340B2 (en) Device modified substrate article and methods for making
EP1198835B1 (en) Dual wafer attachment process
JP6772711B2 (ja) 半導体積層構造体および半導体デバイス
US20080003778A1 (en) Low-temperature welding with nano structures
CN110931629A (zh) 一种用于高掺钪浓度氮化铝生长的结构
TW200849337A (en) Process for fabricating a structure for epitaxy without an exclusion zone
JP2010532570A5 (https=)
CN111599915A (zh) 一种基于种子层结构的高性能氮化铝钪的制备方法及其产品
US20170182744A1 (en) Device modified substrate article and methods for making
US9018077B2 (en) Methods for wafer bonding, and for nucleating bonding nanophases
KR102242125B1 (ko) 열팽창 매칭된 장치를 제공하는 이동 방법
TW200847346A (en) Applications of polycrystalline wafers
TWI251353B (en) Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion
US20150243629A1 (en) Methods for Wafer Bonding, and for Nucleating Bonding Nanophases
CN102832104B (zh) 从单个基底基板形成两个器件晶片的方法
WO2004067812A1 (ja) ダイヤモンド複合基板及びその製造方法
TWI529782B (zh) 雙階半導體基板及其製造方法
CN105197881A (zh) 一种利用金属材料扩散互溶实现硅-硅键合的方法
Hilner et al. Au wetting and nanoparticle stability on GaAs (111) B
Okada et al. Room temperature vacuum sealing using surfaced activated bonding with Au thin films [microresonator example]
Sasangka et al. Influence of bonding parameters on the interaction between Cu and noneutectic Sn-In solder thin films
Dang et al. Low homologous temperature (< 0.2) sputtering of indium films on silicon
Duzik et al. Low temperature rhombohedral single crystal SiGe epitaxy on c-plane sapphire
TWI299183B (en) Wafer structure and fabricating method thereof
CN101311349B (zh) 具有三维凹陷结构的硅及其制备方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees