TWI250484B - Low voltage differential signal clock data recovery device and method thereof - Google Patents

Abstract

The present invention relates to a low voltage differential signal (LVDS) clock data recovery device and a method thereof. The clock data recovery device receives a reference signal and a data signal, and the signal variation track of a data signal forms an eye diagram. The clock signal recovery device includes a phase lock loop (PLL), a double-edge tracking circuit and an eye center generator. The PLL is used to generate a plurality of PLL output signals; the double-edge tracking circuit is used to receive at least part of the plural PLL output signals to generate a left boundary signal of eye diagram and a right boundary signal of eye diagram. The eye center generator outputs an eye center signal corresponding to the eye center in accordance with the left boundary signal of eye diagram and the right boundary signal of eye diagram, thereby generating a plurality of sampled data signals with different phases.

Description

1250484 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a clock signal recovery device for a low voltage differential signal (lVDS) and a method thereof, particularly regarding a utilization phase The leading backward detector and phase interpolator are designed as clock data recovery devices for low voltage differential signals. [Prior Art] Since the advent of the LCD screen, the use of low-voltage differential signals (LVDS) to transport beryllium between the host and the display has become the most common method. The difference between the low voltage differential signal (^VDS) and the conventional single-ended signal is that it has a low voltage and saves power f characteristics. However, with the high-speed transmission of data signals, it is difficult to synchronize the data signals of the data signals. A variety of architectures have been proposed. For example, the previous recognition of > t ~ assumes that when the signal is transmitted, the architecture of the presentation item is symmetric at the design time ^ ^ ^ ^ ^. The circuit designed by the fake kind of fake Han is iron ~, can not avoid the channel with the influence of the environment; ^ ^ 35 application but the effect of material differences. Another example is the jin:: 椹: the use of the so-called "super-sampling" of the transmission line, and the use of the so-called "data" signal read several times and then judge, $ two, The way is to make a time, which means that the speed of reading data must be twice as fast as that of the shell. Therefore, on the one hand, a higher speed electric port is required to transmit several electromagnetic interference (EMI) effects, and the other side is not only Power consumption, and the correctness of the materials is reduced. In the case of high-speed data reading

TW1748F (Friends). ptd 1250484 V. Inventive Description (2) [Description of Information] The present invention is directed to providing a low voltage differential 2 = pulse data recovery device and method thereof, which can make a data signal After the passing of the central rain, the reading position of the data signal can still be set to the eye step. It can improve the noise and different rate caused by transmitting data signals. σ question. Improve the correctness of the received data signal and reduce the error data! The purpose of jii is to propose a clock of the low voltage differential signal - the data signal.资 == The complex device receives an external reference signal and the reply device spoon red 14 u belongs to the low voltage differential signal. The clock signal position signal ii;; the phase L path, a bilateral tracking circuit and an eye diagram center output a plurality of lock phase external reference signals to rate the external test. The frequency of the output signals of the phase-locked loops has a different f-rate phase. And multiple phase-locked loop output signals, phase-locked loop output ίί bilateral tracking circuit receives at least part of the position signal and the eye η data: the material signal exits the left edge of the eye. The circuit is used to receive at least the number. Eye center position signal generation Eye left position of the eye:: A phase-locked loop output signal, and according to the heart position signal. The signal at the right edge of the figure generates a position signal in the eye diagram to output the data signal: the side that is replied according to the center of the eye diagram data = the clock of a low voltage differential signal. The device is used to receive back = set. The clock signal returns to the 贫 and the poor material signal. Clock signal .TW1748F ( AUO ).ptd Page 6 l25〇484

The data edge generator, a bilateral chasing cluster Φ攸. A rain of A 4, invention description (3) S ί i ί includes a phase-locked loop, including = road and an eye center position letter _ _ a & _ ^ ^ ^ ^ ^ ^ ^ right, stinky ΐ Control circuit, - eye left position signal generator and one eye wheel output gamma generator. The phase-locked loop receives the external reference signal with a number to output the signal. The data edge generator receives the data signal. A small number of multiple 'phase t $ digraphs left boundary position signal generators receive to, the wheel:== number to generate a left phase; set the signal. The center of the eye diagram is rotated - the right edge of the eye is rotated by the phase loop circuit, and at least part of the position signal is received according to the eye path to output one eye, the position signal and the eye diagram right: into an eye diagram, the hair = Oh; And the number of the data signal. Going-rounding a center position corresponding to the eye diagram to make the clock signal phase 1* bit, t comparing the phase of the pulse signal with the left eye position of the left eye to the left boundary position of the eye diagram /, bit interpolated output signal d" interpolated round out "bit,? Find the center of the eye diagram by comparing the pulse signal [the right edge position of the eye diagram: two: ϋ 'ι. Finally, according to the center position of the two images in the eye diagram, a sample with different phase of the eye is generated as a narrow position signal, and the frequency of the fourth signal and the external reference signal are outputted, and some phase-locked loops are formed; Have a different phase. Its clever rate and some locks - a ^ right external reference signal for a top 74SFY AUO).ptd 1250484

The number period corresponds to the number of data signals and then two adjacent phase locks. n data bit intervals, η is the positive phase of the round-trip signal phase difference of 360 / 2 η characteristics, and the advantages can be more obvious and fit with the drawings, in detail to make the above objectives of the present invention understand, In the following, a preferred embodiment is as follows: [Embodiment] In this embodiment, a clock interval of a low voltage differential signal (UDS) has seven data intervals, that is, one in a Low-voltage differential signal ([There are seven data in the octave clock area. The external reference signal (10) input in the embodiment has a pulse range of 20 to 100 MHz, and the transmitted data bit rate is uQ~7〇〇. Mbps. A phase interpolator is used in the present invention. The phase interpolator functions to phase interpolate the two input signals, and the phase-interpolated signal can be phase-increasing or decreasing by the input control apostrophe. Please refer to FIG. 1 , which is a block diagram of a clock data recovery device for a low voltage differential signal according to a preferred embodiment of the present invention. The clock data recovery device 20 0 receives an external reference signal. 〇F and data signal D. Data The signal D belongs to the low voltage differential signal (LVDS) and has seven " data intervals. The clock nickname recovery device 2 includes a phase locked loop 2q1 (pll), a data edge generator 204 ( Data edge generator), a bilateral tracking generator). The bilateral tracking circuit 2〇2 includes a reset control circuit 11 B _ 11 S 1 1 II 1 TW1748F ( AUO). Ptd page 8 circuit 202 and an eye center position signal generating circuit 2 〇 3 (eye center 1250484 invention description ( 5) (reset control circuit) 205, an eye left position signal generation state 206 and an eye right boundary position signal generator 207. The lock phase circuit 20 1 receives an external reference signal 〇F to output a plurality of phase locked loop output signals CLK. The data edge generator 2〇4 receives the data signal d to output the chirp pulse signal P. The left edge position signal generator 2〇6 of the eye diagram receives at least a part of the lock=loop output signal CLK and the pulse signal p to Generating a left phase interpolated round-trip signal S-PI-L (not drawn 1) and outputting an eye left boundary position signal ^ LW. The eye right border position signal generator 2 0 7 receives at least a portion of the plurality of locks ^ The road outputs the detection signal CLK and the pulse signal p to generate a right phase interpolation wheel 仏遽S_PI-R (not drawn 1) and outputs an eye right boundary position signal RW Y eye center position signal generation circuit 2 0 3 Receive at least some of the locks The eye loop outputs a signal CLK and outputs an eye center position signal CE according to the left boundary position signal LW of the eye diagram and the boundary position k number RW of the eye diagram 1 (the signal change track of the feed signal D is not formed. One eye diagram. The hair position signal 疋 日 日 日 信号 信号 信号 2 2 2 2 2 2 2 2 2 输出 输出 输出 输出 输出 输出 日 日 守 守 守 守 守 守 守 守 守 守 守 守 日 日 日 日 日 日 日 日 日 日 日Interpolating the phase of the signal S PI L to obtain the left edge position of the eye diagram, the signal riding τ w ^ the insertion wheel and the wide LW. By comparing the phase of the pulse signal P with the right phase, the RW ^ is connected to the second S ~P 1~R phase to obtain the right border position signal signal Rw of the eye diagram and then find the center position of the eye diagram according to the left edge position signal LW of the eye diagram and the right boundary position of the eye diagram. The center position of the figure produces ^, set the signal CE. Finally, according to the eye center position signal CE, the phase-locked i / road ^ number of different phases of the sampling signal. Among them, the frequency of the multiple L CLK frequency and external reference Frequency of signal 0F phase five, invention description (6) :: one!: circuit round out of the letter system There are different phase signals = = 〇: - the signal period corresponds to the data output signal of ΐ = Γ θ, then the two adjacent lock phase replies, please see the table q / Gan 211 The degree / η is 7 in the embodiment of the present invention. The composition is a time portion of the embodiment of the clock data recovery device, which further illustrates the preferred real channel propagation of the present invention. /f replies to the device 2GG. How to make the data signal D through the eye diagram can still send the sampling signal of the data signal D to the circuit 0. First, the second picture, which shows the real circuit diagram of the phase-locked loop. Wherein the 'phase-locked loop 2〇1 includes a bias generator generator 301', a phase frequency comparator (pFD) 3〇2, a charge and discharge circuit (charge pufflp) 3〇3, and a replica bias circuit (Repiica) B 2 μ) 304, a voltage controlled oscillator (vc〇) 3〇5, a first group of differential number to single-ended signal circuit (DSC) 3〇6~312. The phase frequency comparator 302 is configured to compare the external reference signal 〇F with one of the plurality of phase-locked loop output signals CLK' to generate a charge/discharge control signal. The charge and discharge circuit 303 is configured to obtain a first output voltage according to the charge/discharge control signal. The replica bias circuit 306 replicates the first output voltage to obtain a second turn-on voltage. The voltage controlled oscillator 305 outputs a plurality of phase locked loop output signals CLK according to the first output voltage and the second output voltage. Since the reference clock transmitted by LVDS transmits 7 bits in one cycle, 7 differential signals are used in this voltage controlled oscillator 3 0 5 architecture to switch to single-ended signal circuits 3 0 6 to 312. . The seven differential signals are transferred to the single-ended signal circuit 306~

TW1748F (Friends). Ptd Page 10 1250484 V. Description of Invention (7) 31 2 is referred to as the first 312 in this example. Voltage control vibration iJ3〇5, moving the number to the single-ended signal circuit 3 〇 CLK will be equally spaced every second, the first loop difference of the output loop of the target loop 'And 14 out of 14 can produce 14 phases (multi-H turn to early signal circuit 306~312 to CLK ρ0 Γί. ρβ CLK-N6 included in the phase-locked loop output signal CLK) This is 7° =丨-彳4唬 period corresponds to n data bit intervals, η is = /2η V target / phase difference of multiple phase-locked loops CLK signal ί m ^ ° mountain phase-locked loop output signal cl κ After the first group difference η turns early, the signal circuits 306 312 312 can obtain a single-ended signal _~ 0^Dn _ = (the plurality of phase-locked loops CLK signal further includes a single-ended signal ~ D 〇 ~ / D6). Please refer to the figure ί, which shows a preferred implementation circuit of the differential signal to single-ended signal circuit. Therefore, a plurality of phase locked loop output signals CLK are generated by the voltage controlled oscillator 305 and the first set of differential signal to single-ended signal circuits 3〇6 to 312. The plurality of phase-locked loop output signals CLK are included in the differential signal CLK_p〇~ακ_p6, CLK_(four)~CLKJ6 and the single-ended signals D〇~D6, /D〇~/D6. The voltage of the single-ended signal d〇~D6 is the voltage level of the general digital signal, and the differential 1§ (:1^_?〇~CLK-P6, CLK-N0~CLK-N6 is the low voltage The voltage level of the differential signal. For the second part, please refer to Fig. 3, which is a circuit diagram of the implementation of the data edge generator and the bilateral tracking circuit. The eye left position signal generator 20 6 includes a first Phase ear ly/late detector-L 402 and a first phase interpolator (phase

TW1748F ( AUO).ptd Page 11 1250484 V. Description of the invention (8) interpolator-L) 405. The eye right border position signal generator 2 07 includes a second phase leading backward detector (p h a s e e a r 1 y / 1 a t e detector-R) 404 and a second phase interpolator-R 406. The first phase interpolator 405 is configured to receive at least a portion of the differential signals (at least a portion of the differential signals CLK_P0 CLK_P6, CLK_NO CLK — N6) and the left edge position signal LW of the eye to output a left phase Insert the output signal S - PI - L. The second phase interpolator 406 is configured to receive at least a portion of the differential signals (at least a portion of the differential signals CLK_P0 CLK CLK-P6, CLK — N0 CLK — N — N6) and the right edge position signal rw of the eye to output A right phase interpolates the output signal S - PI - R. In other words, the first phase interpolator 4 0 5 and the second phase interpolator 4 0 6 function to input two input signals (at least part of the differential signals CLK_P0 CLK__P6, CLKJ 〇 CLK CLK N6) Phase interpolation is performed, and the phase-interpolated signal can be input by the input control signal (ie, the left-eye position signal LW of the eye diagram and the right-side position signal RW of the eye diagram) (left phase interpolation output signal s - PI - L, right The phase interpolated output signal S-PI-R) is adjusted for phase increase or decrease. For further explanation, please refer to the fourth drawing, which shows the implementation circuit diagram of the phase interpolator. In the second phase interpolator 405 of the first embodiment, the input terminals CLK1, /CLK1 are connected to the differential signals CLKj6, cu μ of the plurality of phase-locked loop input signals CLK, and the other input terminal CLK2 / CLK2 is connected to the differential signals CLK_P0, CLK_N0 in the input signal CLK of multiple phase-locked loops. In addition, w[i], / w[i] ? . _ 〇~11 ' represents the switch that can control the current flowing through it. When the number of switches is larger, the current flowing through the current is larger, and the speed of the signal rise can be controlled to achieve the purpose of controlling the phase. The phase-internal difference j〇5 of Fig. 3

TW1748F (Friends).ptd 1250484 V. Inventive Note (9), W[i], /W[i] receives the output of 6-bit shift register-1 as control. Please refer to FIG. 5 at the same time, which is an output waveform diagram simulated by the first phase internal difference 405. The curves <〇>, <1>, <2>, <3> are the differential signals CLK_P0, CLK of the plurality of phase-locked loop input signals CLK of the output signals of the voltage-controlled oscillators 300, respectively -PI, CLK - P2, CLK - P3 ' and the curves A, B, C, D, E are the differential signals CLK_N6, CLK_P6, CLK - P 〇, CLK J0 of the input signal CLK from the plurality of phase-locked loops The output signal of the group differential signal after phase interpolation. Curve A: The 6-bit shift register-L output has five 1s. Curve B: The 6-bit shift register-L output has four 1s. Curve C: The 6-bit shift register-L output has three 1s. Curve D: The 6-bit shift register-L output has two 1s. Curve E: 6-bi t shi f t register-L output has 1 case. Therefore, in the middle of the differential signal CLK-P0~CLK-P1, it can be divided into six regions, and can be divided into six phases. The first phase leading backward detector 40 2 includes a 6-bit shift register (L). The second phase leading backward debt detector 402 includes a second shift register 408 (6-bit shift r*egist^. The first phase leading backward detector 402 compares the phase of the pulse signal p with the phase-interpolated output signal S — PI—L phase, the second phase leading backwards, the second crying 404, the phase of the pulse signal p, and the phase of the right phase interpolating wheel signal s — p丨. That is, the first phase leading backward detector 4 〇2 and the second phase first backward detector 404 are used to compare the phases of the two input signals, and the results of the direct ratio _ are stored in the first displacement register 4〇7 and the second displacement temporarily.

1250484 V. Description of the invention (10) The first 08 phase/two thousand displacement register 407 and the second displacement register 408 determine the bit to be added, the salt T\05, and the second phase interpolator 406 The output phase edge ϊ = motion / first phase lead behind the Na 402 production 404 generated Λ K K - L1 and the second phase leading backward detector: Λ 制 signal CLK-R1 will make the first displacement I w 分别M m two / temporary storage output eye left boundary position signal J 艮 right boundary position signal RW. The first - == (four) receiving the left edge position of the eye diagram signal coffee position k 5 tiger RW to output the same purpose to the same direction from the vertical ς ΡΤ τ 盘士士moving left phase interpolation output signal insertion output signal "1-R, That is, the eye diagram is left and n篦 is inflated. The opposite 'reset control circuit 20 5 produces: ff : Ϊ CU — L2 and the second reset signal CLK-R2 will make the first ί : After the detector 4 〇 2 and the second phase leading backward detector 4 0 4 艮Γ heart movement, that is, the i 2 of the left and right borders of the eye diagram: the way of inward retraction, outward extension, can The eye diagram opens the smallest left and right borders. Please refer to the 6th m: signal CLK-L1, CLK_R1, CLK_L2, clk_r2 and the left and right borders of the eye diagram. #& The way to find the left edge of the eye is: when the data vaporization occurs in the range to the left of the eye diagram, that is, the right side of the data age change phase interpolating signal S-PI-L, then The first phase Γ Γΐ 402 is controlled by the left edge position signal of the eye diagram: the output of the f Τ is decremented by 1, so that the left phase interpolates the output signal --- Becomes the new interpolated output signal phase left

1250484 V. Description of invention (11) s/iVT, that is to say, the phase of the pulse signal p lags behind the left phase interpolated output. The phase of the second PI-L, the first phase leads the backward stalker 2〇6 control brother? The ::interpolator 405' causes the phase of the new left phase interpolated output signal 匕一 P I - L to increase. The third circle right is said by the shell material that the position of the D branch is in the first phase interpolator 4 0 5 through the #3 diagram / - differential signal to single-ended signal circuit (dsc_l) 4 left 'this eye diagram The left side will enter the locked state (like = DFF in the figure - L1 ❺ output control), so that the phase of the left phase interpolation output h number S - PI L does not change. The spectacle p gangs i must be locked from the left - under the cautious ox, the left side enters the locked state, ::: the first phase interpolator 405 outputs the left phase > the voice = * D the right side of the ^ 1-1 'that is Say the phase of the pulse wave signal ρ: the phase of the first left phase interpolated output signal S - PI - L will be unlocked = Ϊ, the second brother finds the right edge of the eye diagram, the data signal D changes Position 疋 in the right phase interpolates the output signal, to the left of pi R . Ϊ position SI; the anger detector 4 〇 4 by the right edge position of the eye map, the output of the first displacement register 408 will be increased by 1, so that the phase of the ancient S-PI-R is reduced, becoming a new eye 吏: = = = phase of the wave P is ahead of the phase of the left phase interpolated output signal s pi r brother: = first behind the detector 2〇7 controls the second phase interpolator 4〇6, making a new The phase of the left phase interpolated output signal ^耵^ is reduced. The position of the Λ 信 信 〇 是 是 是 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 At the right of the eye, the right side of the eye is smashed into the locked state (this locked shape)

1250484

The phase of the output signal S_PI_R is unchanged by the rotation of DFF-R1 in Fig. 3. Go, so that the right phase interpolation must be changed by the next data signal D. The right side of the field & _ enters the locked state, and the phase interpolated output signal s — pi — R of the left-phase interpolator 405 outputs the right phase behind the left. Phase interpolation input - message 'speaks' the state of the pulse signal P. The phase of -^ -L will unlock the lock. However, when the data signal D changes completely, for example, the phase or the right of the phase change is received or the position of the data signal D changes - straight: the pulse frequency of C is changed.

ΓίΓ Erli interpolator 405 or 406 cannot be aligned with the boundary of the eye diagram because ί; 4=4"7 and the input of the second displacement register 408 are χι and χ2 ΓΛ , HUNTER) ^ # ^ :: Additional signals from register 408 are clocked into the source. Counting m in the τ3 diagram, "_6 sends out a pulse signal; the first-weight and the second reset signal CU. The signal provided by the counter has a different effect from the change of the data signal D as a signal of the CLK signal of the phase-locked loop circuit.

=RCr^R) The first reset signal CU-L2 and the second reset signal jK_R2 provided by the flute are not affected by the locked state of DFF-L1 and DFF-R1 in Fig. 3, and the input first displacement is temporarily stored. The 407 and the second shift register 408 move the outputs of the first phase interpolator 4 〇5 and the second phase interpolator 〇6 in a direction away from the boundary of the eye. In other words, the reset control circuit 2〇5 is used to reset the eye left position signal generator 2 〇 6 after the solid state period

1250484

And the eye, the right boundary position signal generator 2 〇 7. 〇 Part 2 'Please refer to Figure 7, which shows the circuit diagram of the implementation of the eye center position signal generation circuit. The eye center position signal generating circuit 203 includes a third phase interpolator 901 and a voltage control delay circuit (vcdl) 9〇2. The third phase interpolator 9. 0 1 is used according to the left edge position signal of the eye diagram, the right border position signal RW of the eye diagram and at least part of at least part of the differential signal CLK_p 〇 CLK CLK — P6 ' CLK — NO 〜 CLK — N6 to generate an eye center position signal CE ° voltage control delay circuit 9〇2, and generate a plurality of sampling signals having different phases according to the eye center position signal CE. Further, the eye left boundary position signal Lw and the eye right border position signal RW received by the third phase interpolator 902 generate a data sampling signal at the center of the eye through the third phase interpolator 9 〇1. Then, the voltage control delay circuit 902 of the 7th stage outputs, and samples 7 data in each input clock interval. Here, since there are 24 control signals, the phase interpolation signal of the third phase interpolator 9〇1 is the interval signal in the differential signal CLK_P0~CLK_P6, CLK_N0~CLK-N6 (for example) CLK — P5, CLK — P0). Since the first phase interpolator 405 and the second phase interpolator 406 have only 12 control signals, the signals for phase interpolation are adjacent signals of the differential signals CLK_P0 CLK_P6 and CLK —N0 CLK CLKJ6. (eg CLK-P5, CLK-P6). Referring to Figure 8, a comparison of the original sampled signal with the sampled signal produced by the present invention is shown. After the program analog data signal D is transmitted, the position of the data interval falls after the position corresponding to the clock signal interval, that is, the data signal D changes to the left of the eye diagram. The original data sampling position is D1, and the circuit of the present invention

TW1748F (Friends).ptd Page 17 1250484 V. Inventive Note (14) The sampling position can be set later than the original data sampling setting. After the real phase leading backward detection clock data recovery device of the present invention can still be positioned, the transmission problem can be improved, so that the receiving data is comprehensive, although it is not intended to limit the scope of the present invention and the scope of protection of the invention. quasi. The design of the device and the phase of the application is to send the data of the information signal to the invention. When the position of the post-exposure is inserted, the correctness of the signal can be used. As a result of the improvement of the reading position of the time processor and a better familiarity of the various patents as Bj, it can be seen that the set time of the new sampling position β1 is the time signal of the clock signal D1 generated by the simple locking circuit. *, so the data recovery device can be read more correctly, and the material signal of the low voltage differential signal is transmitted through the channel to the center of the eye image and the asynchronous noise is reduced. The embodiment discloses that, as the skilled person does not deviate from the change and retouching, the scope is defined by

1250484 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a clock signal of a differential signal according to the present invention. A low voltage of the preferred embodiment is shown in FIG. 3, which is a phase lock return V. It is a circuit diagram of the shell target of the slanting and happy edge. Circuit diagram. ,;,,, and the implementation of the circuit and the bilateral tracking circuit. Objective: The circuit diagram of the implementation of the interpolator. Figure 6 shows the output waveform of the 7-bit analog 4 05 analog. ΛΐΚ1 with the left and right sides of the eye. , · —R1, C_ diagram. The implementation circuit of the signal generating circuit at the center of the eye is shown in Fig. 8. The comparison chart of the horse is shown. , '彳§号 and the sampling letter produced by the present invention. Figure 9 shows the _ _ 10th green display heartbeat: back: nine sets, structure diagram. Circuit. A preferred embodiment of the ak to early h circuit No. 200 description: clock data recovery device 2 〇 1 · phase locked circuit 202: bilateral tracking circuit 203: eye center position signal generating circuit 204: data edge Generator 205: reset control circuit 2〇6: eye diagram left boundary position signal generator

TW1748F (友达).ptd Page 19 1250484 Schematic description 207 Eye right position signal generator 301 Bias generator 302 Phase frequency comparator 303 Charge and discharge circuit 304 Copy bias circuit 305 Voltage control oscillator 402 One phase leading backward detector 404 second phase leading backward detector 405 first phase interpolator 406 second phase interpolator 407 first displacement register 408 second displacement register 306~312, 409, 410: differential signal to single-ended signal circuit 9 0 1 · · third phase interpolator 902 : voltage control delay circuit

TW1748F ( AUO).ptd第20页

Claims (1)

1250484 /,, the patent application scope of the pulse letter No. 1 back to the clock signal recovery device of the electric signal, ^, belongs to the low voltage differential signal, the clock Zhao Jia - phase-locked loop, is used to receive The external reference to the phase-locked loop output signal, the two phases of the phase-locked circuit are the same as the frequency of the I: respectively, and the phase-locked loops have different phases of the ii-knife; The bilateral tracking circuit 'receives at least part of the zirconium, the signal, and generates a pulse according to the data signal; number:: road wheel: =, writes a letter to the tiger, to output a left edge position of the eye diagram ::2^ right boundary position signal; and eye diagram one eye center position signal generation circuit, which is used for the eye loop output pure, the eye center position signal J = jade according to the eye left position signal and the eye right The boundary position beer road ^ eye center position signal, the eye center position signal generation ^ outputs a plurality of more identical sampling signals of the data signal according to the eye center position signal. The device of claim 1, wherein the phase-locked return includes: a phase-frequency comparator for comparing the external reference signal with one of the phase-locked loop output signals to Generating a charge/discharge control signal, a charge and discharge circuit, based on the charge/discharge control signal Page 21 TW1748F ( AUO). ptd 1250484 VI, f please patent range a first output voltage; to get a two copy bias circuit, copy the second round of output voltage, · and music output voltage, a voltage control oscillation Cry, skill 4th 4 go _ output voltage turns out the locks; loop output 匕 2 rounds of power 璧 and the second oscillator also includes a series of differential U-turns::: voltage control: - the first group of differential signals to the single-ended us Tiger 35 "circuit state, m and differential signal turn | terminal letter; electric U loop in the phase-locked loop output signal, if the external u wheel out To n data bit intervals, n # is a positive number;:: f period is the phase of the phase loop output signal corresponding to the second degree = then the adjacent one of the circuit 4 includes the third item of the patent application scope The device, the 'bilateral tracking edge' is used to receive the data signal, and the data generates a pulse wave according to the edge of the data signal for a lifetime. Some locks: edge, set signal generator, Receiving the work; dividing the position by the * nickname and the pulse signal to The left edge position of the eye diagram is reduced to: the left edge position signal generator of the eye diagram comprises: a phase lock returning first phase interpolator for receiving at least part of the rainout signals and a left boundary of the eye diagram Position signal to rotate the left phase of the Mawtu X output left - the first phase leading backward debt detector is used to receive the pulse port ^, at least part of the phase lock and loop output signals and the left phase 1250484 VI. Applying for the patent range to insert the signal, to rotate the interpolator according to the left boundary of the eye diagram: = adjust the left phase of the left phase of the left phase of the phase-locked loop output by the signal 'the signal; _ δ ~ generation state, receiving i less position signal, the pulse wave signal to rotate the eye to the right eye position of the first eye position signal generator comprises: the wheel out signal and the eye picture right == less: phase interpolation Turn out the signal; and set l旒, to sneak a second phase leading backward detector, the field to pick up «k, at least part of the 4b', turn out 俨觫^-bei w, road round out signal and The right seventh 旒 轮 旒 该 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Position ^ generator and the right boundary position of the eye diagram 5: The device of claim 4, wherein the driving position signal generating circuit comprises: a second phase interpolator for receiving the left side of the eye Number, the right border position signal of the eye diagram and at least part of Yun the plurality of signals to generate the center of the eye location signals; and a voltage controlled delay circuit, a plurality of different phases of the sampled signal according to the position of the center of the eye. 6. The device of claim 5, wherein the first phase interpolating output portion of the right edge of the graph is divided into the output and the right is received by the pulse phase interpolating the two-phase interpolated output signal to the eye Figure > Generator. The eye center position position signal loop signal is generated. Reset control 1250484 6. The patent scope circuit includes a counter that receives the data signal, and receives a fixed number of the data signal during the fixed period. Thereafter, the reset control circuit outputs a first reset signal and a second reset signal to the eye left boundary position signal generator and the eye right border position signal generator. 7. The device of claim 6, wherein the first phase leading backward detector generates a first interval message according to the output signals of the two phase locked loops, wherein the first interval signal is enabled. The first phase leading backward detector compares the phase of the pulse signal with the phase of the left phase interpolated output signal. If the phase of the pulse signal lags behind the phase of the left phase interpolated output signal, the first phase The leading backward detector controls the first phase interpolator 'to increase the phase of the left phase interpolated output signal, and vice versa, does not change the phase of the left phase interpolated output signal. 8. The device of claim 7, wherein the first phase leading backward detector receives the first reset signal, and when the first reset signal is enabled, the left edge position signal control of the eye diagram The first phase interpolator reduces the phase of the left phase interpolated output signal. 9) The device of claim 6, wherein the second phase collar and the trailing detector generate the signal according to the two phase-locked loops, and the first threshold is enabled. The second phase leads the 'pre-detector to compare the phase of the pulse signal with the phase of the right phase interpolated output signal. If the phase of the pulse signal leads the 1-bit of the left phase interpolated output signal, Then the second phase leads the backward detector to control the second phase interpolator, so that the phase of the right phase interpolated output signal is reduced by minus, otherwise, 1250484 VI. Scope of application for patents No change # The text is the phase of the right phase interpolated output signal. The device of claim 9, wherein the first-signal enabler receives the second reset signal, and when the second weight is placed, the right border of the map The position signal controls the second phase: 3 丨, the phase of the right phase interpolated output signal increases. 4 interpolation edge generation;! : the device of the fourth item, wherein the data is first-rounded; the extension; the circuit, the mutual exclusion, the mutually exclusive idle end receives the U-input and the round-out #, the delay circuit Jr Z Bellow's the delay circuit - the Haidi two-input receiver receives the data and couples the pulse to the output of the pulse. ^^唬, the method of recovering the clock signal of the two-pulse: tjf two-signal signal from the end of the mutex is used to receive the j-phase loop with the external reference signal and the U-clock signal recovery device. , - crying the clock signal recovery device package:: electricity: bit - set: map "sheng circuit, ^ side to:: include electricity? and 1 map signal generator:: 2, set signal generator and _ eye Right: f control to rotate the H: number, the edge of the data is produced; C is a small part of the complex number 哕, the left edge of the eye is π w / DQ connected to the data signal center: the signal =:== Received to the boundary position signal: the left boundary position of the eye diagram; the production second-left phase-~bit inner finger refers to the output signal and the wheel: ― HV174SF ( AUO). Ptd Page 25 1250484 “, patent application scope — ___ — — ___ right border Position signal, the part of the phase-locked loop outputs: - the position signal generating circuit receives at least "the road according to the left side of the eye diagram; and the center position of the eye diagram deletes k to generate an eye center position. 唬 and the right border of the eye diagram The location trace forms an eye diagram, and the method includes ^^, the signal change track of the data signal a•borrow Comparing the phase I of the pulse wave to obtain the edge: the edge u only the target bit and the left phase interpolated output letter % b. by comparing the pulse wave standing signal; the phase of the ,, obtaining the right side of the eye diagram » the target position and the right phase interpolated output signal c. by the left boundary position of the eye diagram, the second 5 signal; 唬, find the center position of the eye diagram and the right boundary position of the eye diagram to generate the eye center a position signal; and according to the center position of the eye diagram, d: sampling a signal according to one of the phases of the center of the eye; a唬, generating a plurality of the data signal, wherein the frequency of the phase-locked loop rim= The same, and the phase locks have the reference signal of the == part, and the output 仏 says that there are different phase signals L 'single: the signal of the bit part parameter - the phase lock, the interval, n The system is a positive integer, and the phase difference between the two adjacent, < road output signals is 360/2n degrees. The Department 3, as in the method of claim 12, wherein 'the method makes the household The circuit has a counter that receives the data and receives the number during a fixed period. Information μ reset control circuit outputs a reset signal to a brother of _ Page 26 1250484 /, patent application scope: reset signal to the left edge position signal generator of the eye diagram and the right position signal generator of the eye diagram. 1 4. The method of claim 13, wherein the method further comprises a first phase leading signal generator comprising a first phase leading backwards, and a first phase interpolator, The first phase leading backward detector detects: a left edge position signal of the eye diagram, and the first phase interpolator rotates the left phase interpolation output signal according to the left boundary position signal of the eye. ^ 1 5 · + The method of claim 14, wherein in the method step a, 'the phase of the pulse signal is compared with the left phase interpolated output signal by the first phase leading backward detector The phase is such that when the phase of the pulse signal lags behind the phase of the left phase interpolating wheel signal, the phase of the left phase 1 interpolated output signal is increased, and conversely, the phase of the left phase interpolated output signal is not changed. 16. The method of claim 5, wherein the phase of the left phase interpolated output signal is increased according to the left phase position signal of the eye diagram that the first phase term is behind. The method of claim 16, wherein the phase of the left phase interpolated output signal is reduced according to the first reset indicator. 18. The method of claim 17, wherein the left boundary position signal of the eye corresponds to a left boundary of the eye. The method of claim 18, wherein the method further comprises: the second phase leading edge detector and the second phase interpolator, the second phase The leading backward detector outputs a right boundary position signal of the eye, and the second phase interpolator according to the eye TW1748F (友达).ptd Page 27 1250484 —1~6. Apply for a patent. The right border position signal is round. 20·If Shenshe is as straight as ~ μ right phase interpolates the output signal. In the step b, by the method of the 19th item of the traverse, wherein the phase of the method is compared with the phase of the right phase interpolated by the first detector, the pulse signal is phased to lead the right phase: Phase 'When the pulse signal interpolates the phase of the output signal and the phase of the signal, the phase of the right phase signal is reduced. Conversely, the right phase interpolation wheel does not change the two phases [the method of the collar item... according to the first right phase interpolation output; ^: two: the right border position signal of the eye diagram is reduced by one 22·2 as claimed The method of claim 21, wherein the two 1 signal increases the bit of the right phase interpolated output signal. χ “#. For the method of claim 22, the straight line, # boundary position signal corresponds to a right boundary of the eye diagram. - The middle eye diagram is right 2 4. As in the method of claim 23, The output signal of the diagnosis and the output of the second phase interpolator; the shovel 4 determines the left boundary of the eye diagram and the right boundary. "The tiger will be -25. , the reset circuit is such that the phase of the left phase interpolation of the first phase interpolator and the phase of the right phase interpolation output of the second phase interpolator are far from the eye The phase center of the graph moves. ° 2 6 · If the method of claim 25, the method of the eye center position signal generation circuit includes: _ third phase: crying disk two voltage control delay circuit, third phase interpolator coupling Connect the voltage control delay on page 28 TW1748F (AUO). Ptd 1250484 VI. Apply for a patent range circuit. The method of claim 26, wherein in the method step c, 'the third phase interpolator is connected to at least a portion of the phase-locked loops to turn off the signal' and according to the eye diagram The boundary position signal and the eye right border position signal output the eye center position signal. The method of claim 27, wherein in the method step c, the voltage control delay circuit receives the eye center position signal to output a plurality of phase numbers of the data signal. In order to receive a data signal and _ external ^ j = know pulse data reply method, use the change to form an eye diagram, the resource = test signal, the signal of the data signal, the method is used in the i ^ 2 Including seven data bit position signals, the method includes: a center position to generate an eye center a · by the external reference chain, the frequency of the phase lock signals and the external table to generate a plurality of phase lock signals The phase-locked loop output signal has the same frequency as the 仏 仏 , and the β 同 ^ ^ 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉The quasi-low-level and low-level quasi-change c· generates a left-phase interpolation input d by the adjacent two negative signals of the signals · §, and outputs signals by two adjacent adjacent plugs; μ The t phase-locked signal generates a right phase. e. by comparing the phase of the pulse signal signal, finding the _+ bit of the eye diagram and the left boundary of the left phase interpolation output signal; 1250484 6. Patent application range f. Find a right boundary of the eye by comparing the phase of the pulse signal with the phase of the right phase interpolation output signal; and d. by the two locks separated by a phase signal, the left boundary and the right boundary, finding a center position of the eye diagram, and generating a center position signal of the eye diagram at a center position of the eye diagram; wherein phases of the phase lock signals respectively correspond to the data signals The seven data bit intervals; wherein the eye center position signal is used as a sampling signal of the data signal. TW1748F ( AUO).ptd第30页